Department of Electrical and Electronics Engineering Logic Circuits Laboratory EXPERIMENT-5 COMBINATIONAL LOGIC CIRCUITS

Similar documents
Chapter 3 Combinational Logic Design

Digital Electronics 8. Multiplexer & Demultiplexer

Department of Electrical and Electronics Engineering Logic Circuits Laboratory EXPERIMENT-1 BASIC GATE CIRCUITS

CHW 261: Logic Design

Digital Electronics. Functions of Combinational Logic

BEE 2233 Digital Electronics. Chapter 1: Introduction

ELECTROVATE. Electromania Problem Statement Discussion

MSI Design Examples. Designing a circuit that adds three 4-bit numbers

COMBINATIONAL CIRCUIT

Combinational Logic. Combinational Logic Design Process, Three State Buffers, Decoders, Multiplexers, Encoders, Demultiplexers, Other Considerations

UNIVERSITI TEKNIKAL MALAYSIA MELAKA FAKULTI KEJURUTERAAN ELEKTRONIK DAN KEJURUTERAAN KOMPUTER DENC 2532 ECADD

2 Building Blocks. There is often the need to compare two binary values.

Combinational Circuits DC-IV (Part I) Notes

Function Table of an Odd-Parity Generator Circuit

Combinational Logic Circuits. Combinational Logic

Encoders. Lecture 23 5

Logic Symbols with Truth Tables INVERTER A B NAND A B C NOR C A B A B C XNOR A B C A B Digital Logic 1

Digital Fundamentals 8/25/2016. Summary. Summary. Floyd. Chapter 1. Analog Quantities

16 Multiplexers and De-multiplexers using gates and ICs. (74150, 74154)

Digital Demultiplexer (1x8)

Digital Logic and Design (Course Code: EE222) Lecture 14: Combinational Contd.. Decoders/Encoders

UNIT III. Designing Combinatorial Circuits. Adders

Sr. No. Instrument Specifications. TTL (Transistor-Transistor Logic) based on bipolar junction transistors

Combinational logic. ! Regular logic: multiplexers, decoders, LUTs and FPGAs. ! Switches, basic logic and truth tables, logic functions

CONTENTS Sl. No. Experiment Page No

ECE COMBINATIONAL BUILDING BLOCKS - INVEST 14 DATA TRANSFER

4:Combinational logic circuits. 3 July

Electronics. Digital Electronics

Satish Chandra, Assistant Professor, P P N College, Kanpur 1

Digital Fundamentals

Lab 2: Combinational Circuits Design

Chapter 3 Digital Logic Structures

Solutions. ICS 151 Final. Q1 Q2 Q3 Q4 Total Credit Score. Instructions: Student ID. (Last Name) (First Name) Signature

ICS 151 Final. (Last Name) (First Name)

Aim. Lecture 1: Overview Digital Concepts. Objectives. 15 Lectures

Analog to Digital Conversion

Schmitt Trigger Inputs, Decoders

Digital Applications (CETT 1415) Credit: 4 semester credit hours (3 hours lecture, 4 hours lab) Prerequisite: CETT 1403 & CETT 1405

Unit 3. Logic Design

Digital Fundamentals

Combinational Circuits: Multiplexers, Decoders, Programmable Logic Devices

EXPERIMENT NO 1 TRUTH TABLE (1)

Laboratory Manual CS (P) Digital Systems Lab

CS302 - Digital Logic Design Glossary By

UNIT-IV Combinational Logic


In this lecture: Lecture 8: ROM & Programmable Logic Devices

Unit level 4 Credit value 15. Introduction. Learning Outcomes

Project Part 1 A. The task was to design a 4 to 1 multiplexer that uses 8 bit buses on the inputs with an output of a single 8 bit bus.

Digital Applications (CETT 1415) Credit: 4 semester credit hours (3 hours lecture, 4 hours lab) Prerequisite: CETT 1403 & CETT 1405

Gates and Circuits 1

The figures and the logic used for the MATLAB are given below.

Lecture 15 Analysis of Combinational Circuits

FUNCTION OF COMBINATIONAL LOGIC CIRCUIT

EE19D Digital Electronics. Lecture 1: General Introduction

Logic Circuit Design

Lecture Topics ECE 341. Lecture # 4. Decoder. 2-to-4 Decoder Circuit

Digital Fundamentals. Introductory Digital Concepts

Data output signals May or may not be same a input signals

Department of Electronics and Communication Engineering

CS302 Digital Logic Design Solved Objective Midterm Papers For Preparation of Midterm Exam

UNIT-1. Basic signal processing operations in digital communication

Module 4: Design and Analysis of Combinational Circuits 1. Module-4. Design and Analysis of Combinational Circuits

Function Table of 74LS138, 3-to-8 Decoder +5V 6 G1 4 G2A 5 G2B. 4-to-16 Decoder using two 74LS139, 3-to-8 Decoder

Experiment 5: Basic Digital Logic Circuits

Logic Families. Describes Process used to implement devices Input and output structure of the device. Four general categories.

7.1. Unit 7. Fundamental Digital Building Blocks: Decoders & Multiplexers

Combinational Logic Design CH002

Chapter-1: Introduction

Gates and and Circuits

LOGIC DIAGRAM: HALF ADDER TRUTH TABLE: A B CARRY SUM. 2012/ODD/III/ECE/DE/LM Page No. 1

Electrical, Electronic and Communications Engineering Technology/Technician CIP Task Grid

Topic Notes: Digital Logic

Lab #10: Finite State Machine Design

TABLE 3-2 Truth Table for Code Converter Example

(CSC-3501) Lecture 6 (31 Jan 2008) Seung-Jong Park (Jay) CSC S.J. Park. Announcement

Lecture 3: Logic circuit. Combinational circuit and sequential circuit

Programmable Logic Arrays (PLAs)

DIGITAL ELECTRONICS. Methods & diagrams : 1 Graph plotting : - Tables & analysis : - Questions & discussion : 6 Performance : 3

Overview. This lab exercise requires. A windows computer running Xilinx WebPack A Digilent board. Contains material Digilent, Inc.

CMOS Digital Logic Design with Verilog. Chapter1 Digital IC Design &Technology

Subject: Analog and Digital Electronics Code:15CS32

Programmable Logic Arrays (PLAs)

LOGIC GATES AND LOGIC CIRCUITS A logic gate is an elementary building block of a Digital Circuit. Most logic gates have two inputs and one output.

Dr. Cahit Karakuş ANALOG SİNYALLER

Combinatorial Logic Design Multiplexers and ALUs CS 64: Computer Organization and Design Logic Lecture #14

CSE208W Lecture #1 Notes Barry E. Mapen

4-bit counter circa bit counter circa 1990

MAHALAKSHMI ENGINEERING COLLEGE TIRUCHIRAPALLI

Exercise 1: EXCLUSIVE OR/NOR Gate Functions

LIST OF EXPERIMENTS. KCTCET/ /Odd/3rd/ETE/CSE/LM

In this experiment you will study the characteristics of a CMOS NAND gate.

Exercise 2: OR/NOR Logic Functions

WaveSmart Wave Division Multiplexing (WDM)

Code No: R Set No. 1

Subtractor Logic Schematic

Lecture 2. Digital Basics

Solution for Elec Circuits and Communication Fundamentals

SRV ENGINEERING COLLEGE SEMBODAI RUKMANI VARATHARAJAN ENGINEERING COLLEGE SEMBODAI

Practical Workbook Logic Design & Switching Theory

Transcription:

5.1 Preliminary Study Simulate experiment using an available tool and prepare the preliminary report. 5.2 Aim of the Experiment Implementation and examination of MULTIPLEXER and DEMULTIPLEXER circuits and their basic operations by using MSI logic elements. 5.3 Basic Theory In this experiment, multiplexer and demultiplexer logic circuits will be examinate according to the fourth experiment. 5.3.1 Multiplexers The process of Multiplexing means transmitting more than one knowledge by using less channel or line. A digital multiplexer is a combinational circuits which select only one of the input data and than give it to the output line. Selecting any of the in the selection process at the input line is controlled by select lines. In Fig. 5.1, a multiplexer has 2 N input, N select input and 1 output. This multiplexer circuit with 2 N inputs and 1 output multiplexer is called Nx1. In general, 2x1, 4x1, 8x1, 16x1 multiplexer circuits can ben created. Figure 5.1 The general apprence of Multiplexer Circuit In Fig. 5.2 and Table 5.1 shows the 4x1 multiplexer circuit and its truth table. As shown in Fig. 5.2, 4 binary inputs and 2 select line required to select one of these binary inputs are available. According to the select data which is applied to the select line be selected and output data is transfered to the output line. For a further information a selective multiplexer circuits is alsa referred as data selector. If the multiplexed data more than 1 bit, similary, requried multiplexer circuits can be generated. For example, when we would likte to multiplex the data block as A4 A3 A2 A1 and B4 B3 B2 B1, in Fig. 5.3, we can see the multiplexer circuits which makes this process. As in Fig. 5.3, block A is S=0, S=1 the B block of information transferred to the selected output. 1

Table 5.1 Truth table of 4x1 Multiplexer S 1 S 0 Y 0 0 I0 0 1 I1 1 0 I2 1 1 I3 Figure 5.2 4x1 Multiplexer circuit Figure 5.3 Quad 2x1 multiplexer 2

5.3.2 Demultiplexers Demultiplexer circuit is one of the combinational circuits which operates opposite to multiplexer circuits. A demultiplexer circuit with N select lines is transmit the input data by using one input line to the 2 N output lines according to the select data. In Fig. 5.4, a demultiplexer has 1 input, 2 N output and N select lines. Figure 5.4 The general apprence of Demultiplexer Circuit In general, 1x2, 1x4, 1x8, 1x16 demultiplexer circuits can ben created. In Fig. 5.5 and Table 5.2 shows the 1x4 demultiplexer circuit and its truth table. This circuit is also 2x4 decoder circuit. The diffrence between 2x4 decoder and 1x4 demultiplexer circuits are the input lines which are used in decoder circuit are select lines for the demultiplexer circuits. Enable line in decoder circuit is input line for demultiplexer circuit. Figure 5.5 1x4 Demultiplexer circuit Table 5.2 Truth table of 1x4 Demultiplexer INPUTS OUTPUTS E A B D 0 D 1 D 2 D 3 1 X X 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 1 0 0 0 1 0 0 1 1 0 0 0 1 3

5.4 Components Used In This Experiment Cadet Masterlab experiment set 74LS151 (1 quantity) 74LS153 (1 quantity) 74LS155 (1 quantity) 74LS157 (1 quantity) 74LS04 (1 quantity) LED (10 quantity) 270 ohm (1 quantity) Connection Cables 5.5 Experiment Study 1. 2. 3. 4. Set up and examine 8x1 multiplexer circuits by using 74LS153 and 74LS157 IC chip. Set up and examine 1x4 demultiplexer circuits by using 74155 IC chip. A two bits comparator will be implemented. The numbers A and B consist of 2 bits. If A B the output of the circuit is equal to 1. Otherwise the output is 0. Design the circuit with one 4x1 MUX and minimum number of external gates. A two bits comparator will be implemented. The numbers A and B consist of 2 bits. If A B the output of the circuit is equal to 0. Otherwise the output is 1. Design the circuit with one 8x1 MUX and minimum number of external gates. 5.6 Experiment Problems 1. Set up and examine 16x1 MUX using 2x1 MUX. 2. Set up and examine 16x1 MUX using 4x1 MUX. 3. Set up and examine DEMUX circuit by using 4x1 DEMUX which can select four bits data groups. 5.7 Catalog Information 1. 74LS151 Catalog Information 2. 74LS153 Catalog Information 4

3. 74LS155 Catalog Information 4. 74LS157 Catalog Information 5