ISSUE: March 2016 Improving Loop-Gain Performance In Digital Power Supplies With Latest- Generation DSCs by Alex Dumais, Microchip Technology, Chandler, Ariz. With the consistent push for higher-performance and higher-power-density power supplies, switching frequencies are rising, which is causing digital controllers to adapt to market trends. Microchip s dspic33ep GS series of digital signal controllers, which is aimed at power supply applications, is a primary example. These devices have introduced new features that reduce the execution time of the linear difference equation (LDE) and reduce overall system delays. Ultimately, these features help achieve higher sampling rates of the control loop(s) and mitigate phase erosion, thereby leading to improved loop-gain performance. In a digital power supply unit (PSU) there are several factors that impact loop-gain performance that are specific to the microcontroller. These factors include maximum sampling rate, time required to execute compensator algorithm(s), sampling/conversion time of the analog-to-digital converter (ADC), and microcontroller operating speed. For converters employing peak-current-mode control, the speed of the comparator and the accuracy/speed of the control digital-to-analog converter (DAC) will also have an impact on the PSU loop-gain performance. All of these factors need to be considered when selecting a microcontroller for a given application. This article examines how the dspic33ep GS devices can help improve loop-gain performance for the next generation of power supplies. Higher Operating Frequency The most noticeable feature of the new dspic33ep devices is the increase in operating frequency. The operating frequency of these devices has increased to 70 MHz, which is a maximum increase of 20 million instructions per second (MIPS) over the existing dspic33fj devices. If we take a control loop that executes at a rate of 250 khz and is 60 instructions, this consumes a total of 15 MIPS or 30% of the available resources on the dspic33fj devices. This same control loop code consumes only 20% of the available CPU resources on the dspic33ep processor when executed at the same sampling frequency. If the same percentage of MIPS is consumed after migrating to the dspic33ep devices then this allows the control loop to be executed at a rate of 350 khz. Further analysis shows that phase erosion is reduced by 29% at a given crossover frequency. Equation 1 shows the calculation of phase erosion due to sampling vs. crossover frequency. Compensator Requirements And Overhead In most PSUs that employ a digital compensator, the control of the power stage is typically governed by a simple LDE. While the LDE approach is well known and commonly used, digital implementations are conducive to implementing nonlinear control algorithms. Nonlinear techniques, however, are beyond the scope of this article. The size of the LDE depends on the order of the compensator and the method used to transform the continuous frequency function to a discrete frequency function (forward/backward Euler, bi-linear transform, etc.) Simply put, the LDE is a mathematical expression that uses linear combinations of the control errors and previous control outputs to produce the current control output. See equation 2 for an example of a 3P3Z linear difference equation. (1) 2016 How2Power. All rights reserved. Page 1 of 8
It can be seen that for the 3P3Z compensator there are seven multiplications and seven additions that need to occur, in order to determine the desired control output. This type of arithmetic is well suited for the architecture of the dspic33 devices. These instructions can be processed in seven single-cycle instructions using the multiply and accumulate (MAC) instruction. However there is going to be additional software overhead that includes push/pop working registers, loading data in/out of working registers, resetting arrays, and clamping/scaling the control output. This overhead can potentially impact the control loop execution rate, which leads to reduced phase margins. Alternate Working Registers As shown earlier, with the increased MIPS the execution time for the control loop has dropped quite a bit. However, this can be improved even further on the dspic33ep GS devices with the addition of alternate working registers. These devices incorporate two additional banks of 15 working registers that can be made persistent. This means data such as clamp limits, scaling factors, pointers to coefficients, etc. can be preloaded into appropriate alternate working registers at the device initialization stage. These register banks can then be associated to a given interrupt priority level, which only the control loop software would have access to. This will then eliminate the need to push/pop working registers onto the stack and will reduce the overhead of getting data into work registers when executing the compensator algorithm. Fig. 1 shows an example of how to successfully utilize an alternate working register set using Microchip s hardware accelerated compensator functions. It is important to remember that certain registers are required for particular instructions, which impose limitations on where data can be placed. (2) Fig. 1. Example of an alternate working register. 2016 How2Power. All rights reserved. Page 2 of 8
Let s consider the impact of the alternate working registers on MIPS consumption for high-frequency control loops. A compensator algorithm that may have been called every other switching cycle on the dspic33fj devices may now be called every switching cycle and would still utilize the same percentage of MIPS. The phase erosion due to the sampling process was given in equation 1. The amount of phase degradation depends on the crossover frequency and sampling frequency. Therefore if the sampling rate is doubled, the phase degradation is reduced by half. This means that the phase erosion went from a 29% reduction due to device operating speeds to a 50% reduction when including the use of the alternate working registers. To illustrate the reduction in phase erosion due to increased sampling frequency, consider a system with a 175- khz sampling frequency and 10-kHz bandwidth, the phase erosion is calculated as roughly 10. The same system with 350-kHz sampling frequency would have only 5 of phase erosion. This additional phase margin can be achieved with the dspic33ep device while utilizing the same percentage of MIPS as the dspic33fj devices. It has been shown that higher sampling frequencies can be obtained with the use of alternate working registers and the faster operating speeds of the dspic33ep devices, leading to reduced phase erosion. Next, let s discuss other device specific peripherals and techniques that can improve phase margin leading to improved loop-gain performance. An Improved ADC The dspic33ep GS devices include a new 12-bit ADC that incorporates multiple successive approximation register (SAR) cores. The devices are capable of sampling multiple analog inputs simultaneously and having dedicated 12-bit results available in less than 300 ns. The dedicated SAR cores are continuously tracking the input signal, which means there is zero sampling time required. When the ADC sees a trigger event it will automatically start the conversion process. Remembering that the sampling/conversion time is seen as a delay in the control loop, these new ADC features will minimize the overall sampling/conversion latency, which will help with phase-margin erosion. One unique feature of the ADC is its capability to generate the interrupt before conversion completes. This ADC early interrupt feature, when enabled, helps to reduce the time from when the ADC completes conversion to the start-of-control-loop software (interrupt). The maximum selectable early interrupt timing is eight ADC clocks (Tads). At the fastest throughput this reduces the time taken to get into the compensator algorithm by 114 ns. This is yet another way to reduce the total latency in the control-loop software. Fig. 2 illustrates the impact of the ADC s early interrupt on control-loop latency. 2016 How2Power. All rights reserved. Page 3 of 8
Fig. 2. ADC early interrupt timing. Another ADC module feature is the inclusion of multiple digital comparators that can be configured to give an interrupt when the converted analog result is outside (or within) a given set of limits. This may not seem like a feature that directly impacts the sampling frequency, but it most definitely can. Fewer MIPS are consumed when software is offloaded from the CPU and only executed in a fault condition. This means that we may be able to increase the sampling rate of the control loop. This is highly software dependent and not all applications may be able to take advantage of this new feature. However, it can reduce the CPU work load when it comes to examples like input voltage and temperature monitoring. To reduce the time from ADC trigger-to-control output write back even further, the PWM interrupt service routine (ISR) could be used instead of the ADC ISR and the ADC early interrupt feature. In a general use case, the PWM triggers the ADC to start conversion but now it will also generate its own interrupt event at the same time. With the compensator algorithm placed inside the PWM ISR, the software will start executing the compensator algorithm before the control feedback data is available from the ADC. There is roughly 143 ns between software execution and completion of the ADC conversion. This means there needs to be a minimum of 10 instructions placed before reading the ADC result buffer when the microcontroller is operating at maximum device frequency. If the compensator algorithm is structured in such a way that this technique can be used, it will reduce the time taken to get into the compensator routine by 45%. See Fig. 2 for an early interrupt timing example with PWM interrupt service routine. It is important to note that this method should only be applied with the predictable timing of the dedicated SAR cores. The Compensator Algorithm The structure of the compensator algorithm plays an important role in the time it takes to update the control output variable. With the alternate working registers, the algorithm can be written in such a way as to minimize the computations required prior to updating the control output. In this case, the only required computations will be multiplying the current error with coefficient B0 and then adding that result to the accumulated output from the previous cycle. 2016 How2Power. All rights reserved. Page 4 of 8
Of course the backward normalization and clamping is still there but this will significantly reduce the controloutput write back time without requiring a dedicated accumulator. Fig. 3 shows an example of how the compensator algorithm can be arranged to achieve the quickest update time. The control-output write back time can now occur in less than 300 ns upon entering the compensator algorithm. It will become clear how this is useful in the following sections. Minimizing Phase Erosion Fig. 3. Block diagram of the 3P3Z hardware accelerated compensator. Now let us consider the impact of all these different features on phase erosion. In systems with voltage-mode control and average-current-mode control, it is possible to sample the output capacitor voltage or inductor current at 50% of the off-time. The most common approach is to sample at 50% on-time to allow enough time to process the control algorithm before the start of the next PWM cycle. With all the features mentioned above it is easily possible to sample the control feedback signals during the off-time and write back to control output before the start of the next PWM cycle. Fig. 4 shows the estimated duty cycle limits for an example implementation across switching frequencies while Fig. 5 illustrates a timing diagram of 50% off-time. The increase in phase margin is dependent on duty cycle but if averaged at 50% duty cycle the phase erosion drops by half compared to the 50% on-time measurement. 2016 How2Power. All rights reserved. Page 5 of 8
Fig. 4. On-time duty cycle versus switching-frequency limitation with 50%min/max on/off-time triggering. The dspic33ep GS devices feature an immediate update mode that when enabled will update the PWM parameters within the current cycle when the special function register (SFR) is written to. This applies to phase, period, deadtime and duty cycle all with a resolution of 1 ns. In the 50% off-time scenario, it was mentioned that the control-output write back had to occur before the start of the next PWM cycle and this limits what the maximum on-time is for a given switching frequency. With immediate updates enabled, this is no longer the case. This feature now allows duty cycle limits and/or switching frequency limits to increase even further, which will help in reducing phase-margin erosion once again. Fig. 5 illustrates the timing for both 50% off-time implementations. 2016 How2Power. All rights reserved. Page 6 of 8
Fig. 5. Trigger timing diagram for 50% on-/off-time. The best case for reducing phase margin erosion is to sample the control feedback signal at 50% on-time while ensuring that the new control output is applied to the trailing edge of the current PWM cycle as shown in Fig. 5. This implies that the active edge of the PWM duty cycle is being updated based on the output of the compensator that was just called in the same PWM cycle. This would give the best phase margin possible in a digital system. One should note that this is the optimum use case but cannot be implemented in all applications due to limitations with minimum on-time. See Fig. 4 for minimum on-time as a percentage of the switching period across different switching frequencies. For example, if we look at a boost PFC switching at 100 khz, the minimum on-time requirement would be slightly less than 10% of the period (1 µs). As the minimum duty cycle occurs at the peak of the ac line voltage, at nominal 220-V input voltage, the duty cycle requirement is around 22% leaving ample headroom for the immediate update to occur with large variations in the control output. As input voltage increases further, the immediate update would be disabled and there would be a slight reduction in phase margin. However, this would occur outside of the nominal conditions. 2016 How2Power. All rights reserved. Page 7 of 8
An example was carried out using a synchronous buck converter in which all of the techniques discussed in this article were incorporated. The results showed that the sampling rate increased from every other PWM cycle (175 khz) to every PWM cycle (350 khz) without requiring more MIPS, the compensator software was written for quick write back to the control-output variable, the PWM interrupt was generated for processing the control loop, and 50% on-time trigger with immediate updates was enabled. What was observed was an increase in phase margin of roughly 16. The loop-gain performance started out as marginally stable with only 46 of phase margin and ended up being very close to an analog counterpart at 62. The techniques for reducing phase erosion in this paper are not a cure-all; however they are applicable to a wide range of designs and will provide some degree of loop-gain enhancement. About The Author As an applications engineer for Microchip s 16-bit Microcontroller Division, Alex Dumais supports Microchip s dspic digital signal controllers (DSCs) for switch-mode power supplies. He is involved in product definition, device validation, creating training and documentation collateral, as well as customer support. He also designs and develops power-supply reference designs, such as those for ac-dc converters, dc-dc converters, lighting and solar applications, to demonstrate the capabilities of the DSCs. Alex received his bachelor s degree from Arizona State University and has since been working in the power-electronics field supporting digital control. For further reading on digital power control techniques, see the How2Power Design Guide, locate the Popular Topics category and select Digital Power. 2016 How2Power. All rights reserved. Page 8 of 8