Design and Implementation of Modified High Speed Vedic Multiplier Using Modified Kogge Stone ADD ER Swati Barwal, Vishal Sharma, Jatinder Singh Abstract: The multiplier speed is an essential feature as the multiplier forms an important part of many systems like FIR filters, microprocessors, DSPs etc. The multiplier is slow as compared to other parts of the system hence it is the speed determining factor of the system. An improvement in multiplier speed eventually leads to an improvement in speed of the overall system. The multiplier speed not only depends on the multiplication technique used it also depends on the type of adder employed for the addition of the partial products. The proposed work is based on the vedic multiplication technique and high speed modified Kogge Stone adders have been used. An 8 bit multiplier is realized using modified 4 bit multipliers which intern are realized using modified 2bit vedic multipliers. The design is simulated using Xilinx 14.7 software tool. Keywords: vedic multiplier, Urdhva-tiryagbhyam sutra, Kogge Stone adder. I. Introduction There are various algorithms available to carry out multiplication such as the Booth algorithm, the Array algorithm etc. but each of it has its own limitation in terms of delay and area occupied. The multipliers based on the vedic multiplication technique Urdhva-tiryagbhyam sutra seem to be faster than the other techniques in terms of speed and also occupy less area. The speed of the multiplier to a large extent depends on the speed of the adder employed to calculate the sum of the partial products. The conventional Ripple carry adder introduces a large dealy in the multiplier structure hence reducing its speed to a great extent. Carry Look Ahead adder though better than ripple carry adder in terms of speed but it still lags behind the Kogge Stone adder. The Kogge Stone adder introduces minimum delay into the multiplier structure hence is the adder of choice. A. Vedic Mathematics Sri Bharati Krishna Tirthaji in between 1911-1918 derived vedic mathematics from the ancient Vedas.The Vedas are the sacred scriptures of the Hindus. The word veda is derived from Sanskrit and it means knowledge.the vedic mathematics is a treasure of various sutras. There are a total of 16 sutras, each sutra is a kind of technique to solve various problems based on arithmetic, geometry etc. B. Urdhva-Tiryabhgyam sutra Out of the 16 sutra that have been listed the urdhva-tiryabhgyam sutra is used to derive the product of two number ( be it binary or decimal ) based on the vertical and crosswise technique.this method of multiplication is fast compared to the conventional method of calculating,shifting and adding the partial products. C. Multiplication Technique using Urdhva-Tiryabhgyam sutra Fig 1. Binary number vedic multiplication[6] www.ijlera.com 2018 IJLERA All Right Reserved 32 Page
II. Adders Adders form an essential component of the multipliers, infact the speed of the multiplier to a large extent depends on the speed of the adder. Different types of adders with different area to delay tradeoff are present. Our aim is to select the adder which provides the best tradeoff between the area occupied by it and the delay that it introduces. A. Ripple Carry adder Fig 2.Ripple Carry Adder The ripple carry adder is a parallel type of adder and it is one of the oldest adders available. The architecture of the adder makes use of full adders. The number of full adders used is equal to the number of bits to be added, therefore the number of adders employed increases with the number of bits to be added hence it occupies larger area for higher bit number additions. In addition this adder is rather slow because only when the carry produced by one full adder ripples to the next adder will the next adder be able to add. On the whole ripple carry adder is not a good choice when it comes to designing a high speed 8x8 bit multiplier with minimum area requirements. B. Carry Look Ahead adder Fig 3. Carry- Look Ahead adder A Carry-Lookahead adder is a parallel adder design. It reduces the delay to a large extent when compared to the delay introduced by the Ripple carry adder. Logic gates are used to examine the lower order bits of the two numbers that are to be added in order to observe whether a higher order carry will be generated or not. We need to first define two variables : P i = A i B i, Gi = Ai Bi The sum output and carry output are represented in terms of these two variables : Si = Pi Ci, C i +1 = Gi + Pi Ci Where Gi is termed as carry generate which generates the carry when both Ai, Bi are one regardless of the input carry. Pi is termed as carry propagate since it propagates the carry from Ci to Ci +1. The carry output Boolean function of each stage in a 4 stage carry-lookahead adder can be expressed as C1 = G0 + P0 Cin C2 = G1 + P1 C1= G1 + P1 G0 + P1 P0 Cin C3 = G2 + P2 C2= G2 + P2 G1+ P2 P1 G0 + P2 P1 P0 Cin C4 = G3 + P3 C3= G3 + P3 G2+ P3 P2 G1 + P3 P2 P1 G0 + P3 P2 P1 P0 Cin www.ijlera.com 2018 IJLERA All Right Reserved 33 Page
Thus we can observe that the carry C4 is generated at the very moment when C3 and C2 are generated and it does not have to wait for the generation of C2 and C3. This is the very reason for the reduced delay in carry look ahead adder compared to the ripple carry adder C. Kogge Stone adder Is based on the idea of parallel prefix computation.the G and P values defined in Carry look ahead adder are combined in kogge stone adder before being used. On combining two columns together the unit propagates a carry bit only if both right and left column propagate. But it generates a carry even when only one column generates and the other propagates. Gunit = G1+ P1.G0 Punit=P1.P0 Fig 4. Carry propagation and generation unit[4] Thus by performing recursive combinations we can compute final carry in an 8 bit adder in 3 steps. Fig.5.8 Bit kogge stone adder[4] The top square blocks with numbers represent the computed P and G bit of the eight columns of the 8 bit adder.two adjacent set of columns are combine in the diamond shaped blocks and thus a new combined P and G for the set is produced. At bottom the combined P and G for a particular column and every column to its right is represented by the arrows. Cn= Gn-combined + Pn-combined. Cin, Sn= Pn exor Cn-1 Kogge stone is the fastest possible layout as it scales logarithmically. 4. RESULTS AND COMPARISON A. Comparison of adders Conventional 4x4 vedic multiplier based on the three adders discussed above have be designed and implemented on Xilinx 14.7 www.ijlera.com 2018 IJLERA All Right Reserved 34 Page
Table 1. Comparison table of various adders TYPE OF ADDER(8 BIT) LUT S USED TOTAL NUMBER OF LUT S PRESENT AREA OCCUPIED DELAY(ns) RIPPLE CARRY ADDER 0 63400 0% 20.128 CARRY LOOK AHEAD ADDER 23 63400 0% 4.933 KOGGE STONE ADDER 12 63400 0% 4.135 III. Design Methodology A. 8x8 Modified Vedic Multiplier The 8x8 multiplier can be build either by implementing the partial product equations[5] or by using a 4x4 bit vedic multiplier which intern is build using a 2x2 bit vedic multiplier[6]. Here we have employed the latter technique. The design is further realized using proposed modified 4x4 vedic multiplier and modified kogge stone adders( as discussed below) in a way similar to how a 4x4 vedic multiplier has been designed. B. 4x4 Vedic Multiplier The design for the 4x4 bit vedic multiplier is build using 3 techniques and the delay of the 3 is compared the design which gives minimum delay is further employed in the 8x8 bit multiplier.the three designs are : 1. Conventional 4x4 Multiplier : In this conventional design the first two bits of the 2x2 bir vedic multiplier are directly used to provide the first two lower order bits of the 4x4 bit multiplier product.the other product bits obtained are shifted and added to obtain the higher order product bits of the 4x4 bit multiplier. Fig 6. Conventional 4x4 multiplier [6] 2. Proposed Symmetric 4x4 Multiplier: In this design 4x4 bit multiplier is build by only using 2x2 bit multipliers, shifters and adders. The products obtained from the 2x2 bit multipliers are shifted left or right and are subsequently added in two stages.the structure has a symmetry and gives a delay which is less in comparison to the conventional structure. www.ijlera.com 2018 IJLERA All Right Reserved 35 Page
Fig 7.Proposed symmetric 4x4 multiplier 3. Proposed Modified High speed 4X4 Multiplier : In this proposed design 4x4 bit multipliers are build using modified 2x2 bit multipliers and modified kogge stone adders. a. Modified 2X2 Vedic Multiplier: These multipliers are so designed that they provide the shifted version of the product hence the need for shifters is eliminated thus saving area and reducing the delay.thus the multipliers perform the function of multiplication as well as shifting. b. Modified Kogge Stone adders: These adders are also designed so that they have the built-in shift operation and thus apart from adding they also shift the required sum thus eliminating use of shifters. TYPE Fig 8. Proposed modified High speed 4x4 multiplier Table 2. Comparison table of various 4x4 Vedic multiplier architectures LUT S TOTAL AREA USED LUT S OCCUPIED PRESENT DELAY(ns) Conventional 4x4 structure 11 63400 0% 4.529 4x4 structure using shifters 12 63400 0% 4.262 Prposed 4x4 structure 17 63400 0% 2.690 www.ijlera.com 2018 IJLERA All Right Reserved 36 Page
IV. Results and Simulation Fig.9(a) Timing summary for 4x4 proposed Vedic multiplier Fig.9(b) Synthesis report of proposed 8x8 Vedic multiplier Fig.9(c) Timing summary of proposed 8x8 Vedic multiplier www.ijlera.com 2018 IJLERA All Right Reserved 37 Page
Fig.9(d) RTL schematic of proposed 8x8 multiplier Fig.9(e) Simulation of proposed 8x8 Vedic multipler V. Conclusion and Futurescope As Vedic multiplier is synthesized using different adders, it is observed that kogge stone adder gives the best response in terms of speed, i.e. time delay is minimum while using kogge stone adder. Further, a more symmetric architecture for a Vedic multiplier is implemented. Modified lower order multipliers and modified kogge stone adders have then been used to further reduce the delay and the area occupied. For future work 16x16 and other higher order multipliers can be designed using other high speed adders, the architecture can be worked on to further reduce the delay or the area occupied. www.ijlera.com 2018 IJLERA All Right Reserved 38 Page
Refrences [1]. Avinash Patil, Y. V. Chavan and Sushma Wadar : Performance analysis of multiplication operation based on vedic mathematics, International Conference on Control, Computing, Communication and Materials (ICCCCM),2016. [2]. Bussa Reshma Shalini, M.Mounica : Novel High Speed Vedic Mathematics Multiplier using Ripple Carry Adders,International Journal of Scientific Engineering and Technology Research,Vol.03,Issue.41 November-2014, Pages:8368-8372. [3]. Ankit Chouhan, Mr. Arvind Pratap Singh: Implementation of an Efficient Multiplier based on Vedic Mathematics Using High speed adder, Vol. 1 Issue 6, August 2014. [4]. S Nikhil and Mrs. P. Vijaya Lakshmi : Implementation of a High Speed Multiplier desired for High- Performance Applications Using Kogge Stone Adder [5]. Yogita Bansal,Charu Madhu : A novel high speed approach for 16 16 Vedic multiplication with compressor adders Computers And Electrical Engineering vol 49, january 2016. [6]. R. Raju, S.Veerakumar : Design and Implementation of Low Power and High Performance Vedic Multiplier, International Conference on Communication and Signal Processing, April 6-8, 2016, India. [7]. Akanksha Kant and Shobha Sharma : Applications of Vedic Multiplier Designs A Review [8]. C.S. Wallace, Suggestion for a Fast Multiplier, IEEE Trans. Electron. Computers, EC-13, pp.14-17, 1964. [9]. Ramalatha,M,Thanushkodi,K,DeenaDayalan,K,DharaniP : A novel time and energy efficien tcubing circuit using Vedic mathematics for finite field arithmetic,advances in recent technologies in communication and computing : 2009.p.873 5. [10]. Kuang S.R,Wang J.P,Chang K.C, and Hsu H.W, Energy-Efficient High-Throughput Montgomery Modular Multipliers for RSA Cryptosystems, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 21, no. 11, pp. 1999 2009, Nov. 2013. [11]. H. D. Tiwari, G. Gankhuyag, C. M. Kim, and Y. B. Cho, Multiplier design based on ancient Indian Vedic Mathematics, in SoC Design Conference, 2008. ISOCC 08. International, vol.2. IEEE, 2008, pp. II 65. www.ijlera.com 2018 IJLERA All Right Reserved 39 Page