King Mongkut s Institute of Technology Ladkrabang, Bangkok 10520, Thailand b Thai Microelectronics Center (TMEC), Chachoengsao 24000, Thailand

Similar documents
An improvement of electrical characteristics of P-N diode by X-ray irradiation method

Department of Electrical Engineering IIT Madras

Channel Engineering for Submicron N-Channel MOSFET Based on TCAD Simulation

Substrate Bias Effects on Drain Induced Barrier Lowering (DIBL) in Short Channel NMOS FETs

NAME: Last First Signature

QRTECH AB, Mejerigatan 1, Gothenburg, Sweden

EE/COE 152: Basic Electronics. Lecture 3. A.S Agbemenu.

Lecture 2 p-n junction Diode characteristics. By Asst. Prof Dr. Jassim K. Hmood

This document is downloaded from DR-NTU, Nanyang Technological University Library, Singapore.

CHAPTER 8 The PN Junction Diode

CHAPTER 8 The pn Junction Diode

Semiconductor Devices Lecture 5, pn-junction Diode

Semiconductor Physics and Devices

Digital Integrated Circuits A Design Perspective. The Devices. Digital Integrated Circuits 2nd Devices

Design Simulation and Analysis of NMOS Characteristics for Varying Oxide Thickness

Unless otherwise specified, assume room temperature (T = 300 K).

Development of Solid-State Detector for X-ray Computed Tomography

Bipolar Junction Transistors (BJTs) Overview

EC T34 ELECTRONIC DEVICES AND CIRCUITS

CHAPTER 8 The PN Junction Diode

High-Ohmic Resistors using Nanometer-Thin Pure-Boron Chemical-Vapour-Deposited Layers

n-channel LDMOS WITH STI FOR BREAKDOWN VOLTAGE ENHANCEMENT AND IMPROVED R ON

LAB V. LIGHT EMITTING DIODES

EE70 - Intro. Electronics

EDC Lecture Notes UNIT-1

Title detector with operating temperature.

Role of guard rings in improving the performance of silicon detectors

10/27/2009 Reading: Chapter 10 of Hambley Basic Device Physics Handout (optional)

Ch5 Diodes and Diodes Circuits

Simulation and test of 3D silicon radiation detectors

Review Energy Bands Carrier Density & Mobility Carrier Transport Generation and Recombination

improving further the mobility, and therefore the channel conductivity. The positive pattern definition proposed by Hirayama [6] was much improved in

The current density at a forward bias of 0.9 V is J( V) = 8:91 10 ;13 exp 0:06 = 9: :39=961:4 Acm ; 1: 10 ;8 exp 0:05 The current is dominated b

Depletion width measurement in an organic Schottky contact using a Metal-

Lesson 5. Electronics: Semiconductors Doping p-n Junction Diode Half Wave and Full Wave Rectification Introduction to Transistors-

semiconductor p-n junction Potential difference across the depletion region is called the built-in potential barrier, or built-in voltage:

ECE520 VLSI Design. Lecture 2: Basic MOS Physics. Payman Zarkesh-Ha

ES 330 Electronics II Homework # 1 (Fall 2016 SOLUTIONS)

The HGTD: A SOI Power Diode for Timing Detection Applications

ECE4902 B2015 HW Set 1

Digital Integrated Circuits EECS 312

An Analytical model of the Bulk-DTMOS transistor

Laboratory No. 01: Small & Large Signal Diode Circuits. Electrical Enginnering Departement. By: Dr. Awad Al-Zaben. Instructor: Eng.

PHYSICS OF SEMICONDUCTOR DEVICES

Silicon Sensor Developments for the CMS Tracker Upgrade

Intrinsic Semiconductor

Section 2.3 Bipolar junction transistors - BJTs

LAB V. LIGHT EMITTING DIODES

Key Questions. ECE 340 Lecture 39 : Introduction to the BJT-II 4/28/14. Class Outline: Fabrication of BJTs BJT Operation

Key Questions ECE 340 Lecture 28 : Photodiodes

Analog Electronic Circuits

Chapter #3: Diodes. from Microelectronic Circuits Text by Sedra and Smith Oxford Publishing

UNIT 3: FIELD EFFECT TRANSISTORS

University, Harbin, The 49th Research Institute of China Electronics Technology Group Corporation, Harbin,

Proposal of Novel Collector Structure for Thin-wafer IGBTs

High Voltage and MEMS Process Integration

Downloaded from

EE C245 / ME C218 INTRODUCTION TO MEMS DESIGN FALL 2011 PROBLEM SET #2. Due (at 7 p.m.): Tuesday, Sept. 27, 2011, in the EE C245 HW box in 240 Cory.

ELECTRICAL PROPERTIES OF POROUS SILICON PREPARED BY PHOTOCHEMICAL ETCHING ABSTRACT

Copyright -International Centre for Diffraction Data 2010 ISSN

Sub-Threshold Region Behavior of Long Channel MOSFET

Experiment 3. 3 MOSFET Drain Current Modeling. 3.1 Summary. 3.2 Theory. ELEC 3908 Experiment 3 Student#:

AN ANALYSIS OF D BAND SCHOTTKY DIODE FOR MILLIMETER WAVE APPLICATION

Students: Yifan Jiang (Research Assistant) Siyang Liu (Visiting Scholar)

Field-Effect Transistor (FET) is one of the two major transistors; FET derives its name from its working mechanism;

SUPPLEMENTARY INFORMATION

Lecture 3: Diodes. Amplitude Modulation. Diode Detection.

Quality Assurance for the ATLAS Pixel Sensor

Student Lecture by: Giangiacomo Groppi Joel Cassell Pierre Berthelot September 28 th 2004

ECSE-6300 IC Fabrication Laboratory Lecture 9 MOSFETs. Lecture Outline

Integrated diodes. The forward voltage drop only slightly depends on the forward current. ELEKTRONIKOS ĮTAISAI

Three Terminal Devices

Electronics The basics of semiconductor physics

Lecture 16 - Metal-Semiconductor Junction (cont.) October 9, 2002

EJERCICIOS DE COMPONENTES ELECTRÓNICOS. 1 er cuatrimestre

ECE-342 Test 1: Sep 27, :00-8:00, Closed Book. Name : SOLUTION

6.012 Microelectronic Devices and Circuits

Università degli Studi di Roma Tor Vergata Dipartimento di Ingegneria Elettronica. Analogue Electronics. Paolo Colantonio A.A.

A new Vertical JFET Technology for Harsh Radiation Applications

3D SOI elements for System-on-Chip applications

R. W. Erickson. Department of Electrical, Computer, and Energy Engineering University of Colorado, Boulder

Effect of Dislocations on Dark Current in LWIR HgCdTe Photodiodes

Characterization of SOI MOSFETs by means of charge-pumping

Higher School of Economics, Moscow, Russia. Zelenograd, Moscow, Russia

ECSE-6300 IC Fabrication Laboratory Lecture 7 MOSFETs. Lecture Outline

INTEGRATED CIRCUIT ENGINEERING

Lecture 18: Photodetectors

Electrical transport properties in self-assembled erbium. disilicide nanowires

EXPERIMENT 10: SCHOTTKY DIODE CHARACTERISTICS

Application Note No. 065

Supporting Information

Transistor was first invented by William.B.Shockley, Walter Brattain and John Bardeen of Bell Labratories. In 1961, first IC was introduced.

CHAPTER 9 CURRENT VOLTAGE CHARACTERISTICS

Low-frequency noises in GaAs MESFET s currents associated with substrate conductivity and channel-substrate junction

Semiconductor TCAD Tools

Experiment 3 - IC Resistors

Optimization of Threshold Voltage for 65nm PMOS Transistor using Silvaco TCAD Tools

Introduction to the Long Channel MOSFET. Dr. Lynn Fuller

A study into the applicability of p þ n þ (universal contact) to power semiconductor diodes for faster reverse recovery

Physics 160 Lecture 5. R. Johnson April 13, 2015

Transcription:

Materials Science Forum Online: 2011-07-27 ISSN: 1662-9752, Vol. 695, pp 569-572 doi:10.4028/www.scientific.net/msf.695.569 2011 Trans Tech Publications, Switzerland DEFECTS STUDY BY ACTIVATION ENERGY PROFILE FOR LOWERING LEAKAGE CURRENT IN P-N JUNCTION Itsara Srithanachai a, Surada Ueamanapong a, Poopol Rujanapich a, Narin Atiwongsangthong a, Surasak Niemcharoen a, Amporn Poyai b, and Wisut Titiroongruang a a Electronics Research Center and Department of Electronics Faculty of Engineering, King Mongkut s Institute of Technology Ladkrabang, Bangkok 10520, Thailand b Thai Microelectronics Center (TMEC), Chachoengsao 24000, Thailand E-mail: Srithanachai@gmail.com, Usurada@gmail.com, poopolr@yahoo.com, kanarin@kmitl.ac.th, knsurasa@kmitl.ac.th, amporn.poyai@nectec.or.th, ktwisut@kmitl.ac.th Keywords: Activation Energy, Silicon, P-N Junction, Leakage Current, Defect Abstract. Diode leakage current consists of diffusion (I d ) and generation current (I g ), which is strongly sensitive to the residual defect density. These defects can be studied by activation energy (E a ). Therefore, this paper presents a method for calculating activation energy of silicon p-n junctions from volume generation current. It combines temperature-dependent current voltage (I V) and capacitance voltage (C-V) measurements of diodes. The I g can be found from the volume leakage current by subtraction of the volume diffusion current, which is calculated while the depletion width is zero. The activation energy (E a ) is derived from slope of an Arrhenius plot of I g. To derive the correct slope the temperature dependence of the depletion width, which is obtained from the corrected volume capacitance has been applied. The E a profile below junction has been shown. The lower E a value has been found near the junction, which may relate to the junction implantation. Introduction Requirements for present-day high-quality silicon substrates are extremely tight with respect to control of grown-in or processing induced defects. Besides, it may still be a marked effect of the starting material on electrical characteristics of simple device structures, like a p-n junction [1]. The defects can be a source of the leakage current in p-n junction which is one of main parameter that affects device performance. This leakage current is related to electrically active defects in the silicon [2]. Therefore, one way to study defects is analyzing E a of the leakage current in p-n junction. Usually, it can be extracted from the generation current [3]. To yield information on energy level of generation centers in depletion region of a diode we study reverse current (I R ) as a function of temperature. E a is derived from slope of an Arrhenius plot of ln(i R ) versus 1/kT, whereby only exponential 1/T dependence is taken into account; where k and T are the Boltzmann constant and the absolute temperature, respectively [1]. Here, the method using current-voltage (I- V) and capacitance-voltage (C-V) characteristics and analyses of the leakage current E a will be shown. Experiment Sample preparation For this study, p + -n junction diodes were fabricated on the <111> orientation 134-140 Ω-cm 300 µm of n-type silicon substrate. The wafers were sent into photolithography and etch processes to open 4 mm 2 for active area and 10 µm for guard ring of 1 µm thickness photoresist window. Then wafers were implanted boron with dose of 1x10 16 cm -2 at energy of 120 kev and implanted phosphorous with the same condition on backside wafer for ohmic contact and followed by an 1050 o C, 60 min thermal anneal. After that wafers were sent into metallization process to create 1 µm thickness of aluminum layer at both sides. The second photolithography step and etch processes were conducted to create aluminum patterns then anneal at 400 o C for 30 min. Wafers were sawed and assembled on PCB before finished with wire bond process. Finally, the chip is ready to connect to test circuit outside. All rights reserved. No part of contents of this paper may be reproduced or transmitted in any form or by any means without the written permission of Trans Tech Publications, www.ttp.net. (ID: 130.203.136.75, Pennsylvania State University, University Park, USA-09/05/16,04:14:33)

570 Eco-Materials Processing and Design XII Measurement procedure HP4156B was used to measure electrical properties of diode. The current-voltage (I-V) characteristics were measured on wafer with bias step of 0.025 V from reverse (V R ) to forward (V F ) voltage, in the range of -10 to +1 V, whereby the bias was applied to the back n-type substrate and the current was measured at the top p-type. Temperature dependent measurements were done at 30, 40, 50, 60, 70, and 80 o C, respectively, allowing extraction of the E a of the reverse current. Capacitance-voltage (C-V) measurements were performed on the same diode at a frequency of 100 khz, as a function of temperature, to extract the volume depletion width (W). Results and Discussion The current-voltage of p-n junction diode presented in Figure 1, [4,5]. For the case of reverse bias, the saturation current or leakage current includes the contributions of the diffusion current (I d ) and the generation current (I g ), which generate in the depletion region. The leakage current is presenting in equation (1) and the generation current is described in equation (2). I 0 = I d + I g I 0 = I d + Aqn i W/τ g (1) (2) Where A is the area of p-n junction, n i is the intrinsic carrier concentration, W is the width of depletion region and τ g is generation lifetime. Fig 1. The current-voltage characteristics of the silicon p-n junction diode Fig 2. The capacitance-voltage characteristics of the silicon p-n junction diode The leakage current increases at higher reverse bias (larger depletion width higher reversed bias voltage), which can be surely explained by equation (2). The diffusion current is independent of applied bias because all of a fixed amount of the minority carriers generated by thermal energy within a diffusion length of the depletion region will essentially get swept across the junction due to the field, regardless of the applied bias and the strength of the electric field. Therefore, increasing of leakage current at higher reverse bias is mostly the result of generation current and also depends on the depletion width which can obtain from the capacitance that was shown in Figure 2. The relation between depletion width and capacitance can explain in equation (3), where ε si is permittivity of silicon. From equation (2), the increment of generation current is result of the increase in depletion width. W = A ε si / C In case of varied temperature, as shown in Figure 3, the leakage current increases as temperature increases due to diffusion current increases with temperature. Table 1 shows the summary of the diffusion current. To derive the diffusion current, it can be calculated from the relation of leakage (3)

Materials Science Forum Vol. 695 571 current and depletion width. Figure 4 shows how to calculate the diffusion current and in this example it is 0.65 na. From equation (2), the generation current was calculated after we derived the diffusion current for difference temperature. Table 1 The volume diffusion current at various temperature Temperature [ o C] 30 40 50 60 70 80 I d [na] 0.002 0.043 0.209 0.650 2.405 7.903 Fig 3. The current-voltage characteristics of the silicon p-n junction diode at various temperatures Fig 4. The leakage current versus the depletion width of the silicon p-n junction diode A general relation between a physical variable and its activation energy can be applied to the leakage current of a p n junction, according to I R (T) exp(-e a /kt) With I R is reverse current. The slope of an Arrhenius plot, I R (T) vs 1/kT yields the activation energy E a [6]. Figure 5 shows the effect of difference temperature corrections on the activation energy from Arrhenius plot of generation current versus the temperature of the difference bias. Figure 6 shows the approximation of E a is 0.69 ev. The lower E a value has been found near the junction, which may relate to the boron implantation. While the defects related to phosphorus implantation may dominate at deeper. This can be expected the higher leakage current near the junction. In order to reduce the leakage current, these kinds of defects have to be controlled. (4) Fig 5. Arrhenius plot of generation current versus the temperature of the difference bias Fig 6. The value of the activation energy versus bias voltage

572 Eco-Materials Processing and Design XII Summary This paper clearly shows the method to obtain the activation energy profile below the junction from the temperature dependence I-V and C-V characteristics. This is a useful method to study the behavior of electrically active defects. Lower activation energy has been found near the junction. Acknowledgment This work has been supported by Thailand Graduate Institute of Science and Technology (TGIST) under scholarship No. TG-44-22-53-014D. References [1] A. Poyai, E. Simoen, C. Claeys, A. Czerwinski, and E. Gaubas, Improved extraction of the activation energy of the leakage current in silicon p n junction diodes, Appl. Phys. Lett., Vol. 78(14), pp. 1997-1999, 2001. [2] W. Pengchan, T.Phetchakul, and A. Poyai, Implantation-induced Defects Analysis Base on Activation Energy Diagnostics, Integrated Circuits, ISIC, pp. 518 52,1 Issue 14-16 Dec 2009. [3] A. Poyai, C. Claeys and E. Simoen, Improved extraction of carrier concentration and depletion width from capacitance-voltage characteristics of silicon n+-p-well junction diodes Appl. Phys. Lett., Vol. 80(7), pp. 1192-1194, 2002. [4] S.M. Sze, Physics of Semiconductor Devices, John Wiley & Sons, New York, 1981. [5] Gerold W. Neudeck, The pn junction diode, 2nd Modular series on solid state devices, Eds Gerold W. Neudeck and Robert F. Pierret, Addison-Wesley Publishing Company, 1989. [6] A. Czerwinski, E. Simoen, A. Poyai, and C. Claeys, Activation energy analysis as a tool for extraction and investigation of p n junction leakage current components, J. Appl. Phys., Vol. 94(2), pp. 1218-1221, 200

Eco-Materials Processing and Design XII 10.4028/www.scientific.net/MSF.695 Defects Study by Activation Energy Profile for Lowering Leakage Current in P-N Junction 10.4028/www.scientific.net/MSF.695.569 DOI References [1] A. Poyai, E. Simoen, C. Claeys, A. Czerwinski, and E. Gaubas, Improved extraction of the activation energy of the leakage current in silicon p n junction diodes, Appl. Phys. Lett., Vol. 78(14), pp.1997-1999, (2001). 10.1063/1.1359487 [3] A. Poyai, C. Claeys and E. Simoen, Improved extraction of carrier concentration and depletion width from capacitance-voltage characteristics of silicon n+-p-well junction diodes, Appl. Phys. Lett., Vol. 80(7), pp.1192-1194, (2002). 10.1063/1.1435809