Power MOSFET - V, -. A, Single P-Channel, TSOP- Features Low R DS(on) in TSOP- Package. V Gate Rating This is a Pb-Free Device Applications Battery Switch and Load Management Applications in Portable Equipment High Side Load Switch Portable Devices like Games and Cell Phones V (BR)DSS R DS(on) MAX I D MAX - V 9 m @ -. V m @ -. V -. A -. A MAXIMUM RATINGS (T J = C unless otherwise stated) Parameter Symbol Value Unit Drain-to-Source Voltage V DSS - V Gate-to-Source Voltage V GS V Continuous Drain Current (Note ) Power Dissipation (Note ) Continuous Drain Current (Note ) Power Dissipation (Note ) Steady State T A = C I D -. A T A = 7 C -. t s T A = C -. Steady State T A = C P D. W t s. Steady State T A = C I D -. A T A = 7 C -. T A = C P D.7 W Pulsed Drain Current t p = s I DM - A Operating Junction and Storage Temperature T J, T STG Lead Temperature for Soldering Purposes (/ from case for s) - to C T L C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.. Surface-mounted on FR board using in sq pad size (Cu area =.7 in sq [ oz] including traces).. Surface-mounted on FR board using the minimum recommended pad size. (Cu area =.77 in sq). P-Channel TSOP- CASE G STYLE MARKING DIAGRAM SF = Device Code M = Date Code = Pb-Free Package (Note: Microdot may be in either location) PIN ASSIGNMENT Drain Drain Source Drain Drain Gate SF M ORDERING INFORMATION Device Package Shipping TG TSOP- (Pb-Free) / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD/D. Semiconductor Components Industries, LLC, 7 November, 7 - Rev. Publication Order Number: /D
THERMAL RESISTANCE MAXIMUM RATINGS Parameter Symbol Value Unit Junction-to-Ambient Steady State (Note ) R JA Junction-to-Ambient t s (Note ) R JA Junction-to-Ambient Minimum Pad (Note ) R JA 9. Surface-mounted on FR board using in sq pad size (Cu area =.7 in sq [ oz] including traces). Surface-mounted on FR board using the minimum recommended pad size (Cu area =.77 in sq). C/W Input Capacitance C ISS ELECTRICAL CHARACTERISTICS (T J = C unless otherwise specified) Parameter Symbol Test Condition Min Typ Max Unit OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage V (BR)DSS V GS = V, I D = - A - V Zero Gate Voltage Drain Current I DSS VGS = V, T J = C -. A V DS = - V T J = 7 C -. Gate-to-Source Leakage Current I GSS V DS = V, V GS = ± V. A ON CHARACTERISTICS (Note ) Gate Threshold Voltage V GS(TH) V GS = V DS, I D = - A -. -.9 V Drain-to-Source On Resistance R DS(on) V GS = -. V, I D = -. A 9 9 m V GS = -. V, I D = -. A 79 Forward Transconductance g FS V DS = - V, I D = -. A. S CHARGES, CAPACITANCES AND GATE RESISTANCE pf Output Capacitance C OSS VGS = V, f = MHz, VDS = - V 9 Reverse Transfer Capacitance C RSS 9 Total Gate Charge Q G(TOT). 9. nc Threshold Gate Charge Q G(TH) V GS = -. V, V DS = - V;. Gate-to-Source Charge Q GS I D = -. A. Gate-to-Drain Charge Q GD. SWITCHING CHARACTERISTICS, V GS =. V (Note ) Turn-On Delay Time t d(on). ns Rise Time t r V GS = -. V, V DS = - V,. Turn-Off Delay Time t d(off) I D = -. A, R G =. Fall Time t f DRAIN-SOURCE DIODE CHARACTERISTICS Forward Diode Voltage V SD V GS = V, I S = -. A Reverse Recovery Time t RR V GS = V, di SD /d t = A/ s, I S = -. A. Pulse Test: pulse width s, duty cycle %. Switching characteristics are independent of operating junction temperatures T J = C -. -. V ns
TYPICAL PERFORMANCE CURVES (T J = C unless otherwise noted) V GS = -. V -. V T J = C V DS = - V -I D, DRAIN CURRENT (AMPS) - V - V -. V - V -. V -V DS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) -I D, DRAIN CURRENT (AMPS). T J = C T J = C T J = - C.. -V GS, GATE-TO-SOURCE VOLTAGE (VOLTS) Figure. On-Region Characteristics Figure. Transfer Characteristics R DS(on), DRAIN-TO-SOURCE RESISTANCE ( ).. I D = - A T J = C.......... -V GS, GATE-TO-SOURCE VOLTAGE (VOLTS) Figure. On-Resistance vs. Gate-to-Source Voltage R DS(on), DRAIN-TO-SOURCE RESISTANCE ( )... T J = C V GS = -. V. -I D, DRAIN CURRENT (AMPS) V GS = -. V Figure. On-Resistance vs. Drain Current and Gate Voltage R DS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED).......9. I D = - A V GS = -. V.7 - - 7 T J, JUNCTION TEMPERATURE ( C) Figure. On-Resistance Variation with Temperature C, CAPACITANCE (pf) C iss C oss C rss -V DS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) Figure. Capacitance Variation V GS = V T J = C f = MHz
-V GS, GATE-TO-SOURCE VOLTAGE (VOLTS) 7 Q GS TYPICAL PERFORMANCE CURVES (T J = C unless otherwise noted) -V DS -V GS Q GD QT Q G, TOTAL GATE CHARGE (nc) V DS = - V I D = - A T J = C Figure 7. Gate-to-Source and Drain-to-Source Voltage vs. Total Charge -V DS, DRAIN-TO-SOURCE VOLTAGE (VOLTS), SOURCE CURRENT (AMPS) -IS.. V GS = V T J = C T J = C...... -V SD, SOURCE-TO-DRAIN VOLTAGE (VOLTS) Figure. Diode Forward Voltage vs. Current. -V GS(th) (V).9 I D = - A..7....... - - 7 T J, JUNCTION TEMPERATURE ( C) Figure 9. Threshold Voltage POWER (WATTS)... SINGLE PULSE TIME (s) Figure. Single Pulse Maximum Power Dissipation -I D, DRAIN CURRENT (A) s ms ms V GS = -. V SINGLE PULSE. T C = C R DS(on) LIMIT dc Thermal Limit Package Limit.. -V DS, DRAIN-TO-SOURCE VOLTAGE (V) Figure. Maximum Rated Forward Biased Safe Operating Area
R(t), EFFECTIVE TRANSIENT THERMAL RESPONSE NORMALIZED ( C/W). Duty Cycle =...... Single Pulse P (pk) Figure. FET Thermal Response t t DUTY CYCLE, D = t /t Test Type = sq in oz R JA = sq in oz..... PULSE TIME (s)
PACKAGE DIMENSIONS TSOP- CASE G- ISSUE S H E D E NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y.M, 9.. CONTROLLING DIMENSION: MILLIMETER.. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL.. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS.. (.) e A b A L c MILLIMETERS INCHES DIM MIN NOM MAX MIN NOM MAX A.9....9. A...... b...... c.....7. D.9..... E...7..9.7 e..9...7. L...... H E..7..99.. - - SOLDERING FOOTPRINT*..9 STYLE : PIN. DRAIN. DRAIN. GATE. SOURCE. DRAIN. DRAIN.9.7.9.7.9.7.7...9 SCALE : mm inches *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box, Denver, Colorado 7 USA Phone: -7-7 or -- Toll Free USA/Canada Fax: -7-7 or --7 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: --9 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 79 9 Japan Customer Focus Center Phone: --77- ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative /D