RT A, 21V 500kHz Synchronous Step-Down Converter. General Description. Features. Ordering Information RT8287. Applications. Pin Configurations

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3A, 2V 500kHz Synchronous Step-Down Converter General Description The is a synchronous step-down regulator with an internal power MOSFET. It achieves 3A of continuous output current over a wide input supply range with excellent load and line regulation. Current mode operation provides fast transient response and eases loop stabilization. Fault condition protection includes cycle-by-cycle current limiting and thermal shutdown. An adjustable soft-start reduces the stress on the input source at startup. The requires a minimal number of readily available external components, providing a compact solution. Ordering Information Note : Richtek products are : Package Type QW : WDFN-4L 4x3 (W-Type) Lead Plating System Z : ECO (Ecological Element with Halogen Free and Pb free) RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. Suitable for use in SnPb or Pb-free soldering processes. Marking Information A YM DNN A : Product Code YMDNN : Date Code Features 3A Output Current Adjustable Soft-Start 20mΩ/40mΩ Internal Power MOSFET Switch Internal Compensation Minimizes External Parts Count Fixed 500kHz Frequency Thermal Shutdown Protection Cycle-by-Cycle Over Current Protection Wide 4.5V to 2V Operating Input Range Adjustable Output from 0.0V to 5V Small 4-Lead WDFN Package RoHS Compliant and Halogen Free Applications Distributive Power Systems Battery Charger DSL Modems Pre-Regulator for Linear Regulators Pin Configurations BOOT EN (TOP VIEW) 4 2 3 4 5 3 2 0 6 9 7 5 WDFN-4L 4x3 A VCC SS FB Copyright 202 Richtek Technology Corporation. All rights reserved. DS27-03 June 202

Typical Application Circuit V IN ON/OFF C IN 22µF R3 00k C C 0.µF 9 VCC 7 EN A 4 BOOT FB 6 2, 3, 4, 5 SS 0 C SS 47nF C BOOT 0.µF R T 2, 3, 5 (Exposed Pad) L R R2 C OUT.2V/3A Table. Recommended Components Selection (V) R (kω) R2 (kω) R T (kω) L (μh) C OUT (μf) 5 75 4.46 0 4.7 22 x 2 3.3 75 24.32 0 3.6 22 x 2 2.5 75 35.2 0 3.6 22 x 2. 5 4.07 30 2 22 x 2.5 5 5.4 39 2 22 x 2.2 5 0.3 47 2 22 x 2.05 5 6.69 47.5 22 x 2 Function Pin Description Pin No. Pin Name Pin Function Supply Input. supplies the power to the IC, as well as the step-down converter switches. Drive with a 4.5V to 2V power source. Bypass to with a suitably large capacitor to eliminate noise on the input to the IC. 2, 3, 4, 5 Switch Node. is the switching node that supplies power to the output. Connect the output LC filter from to the output load. Note that a capacitor is required from to BOOT to power the high side switch. 6 BOOT High Side Gate Drive Boost Input. BOOT supplies the drive for the high side N-MOSFET switch. Connect a 00nF or greater capacitor from to BOOT to power the high side switch. 7 EN Chip Enable (Active High). For automatic start-up, connect the EN pin to with a 00kΩ resistor. FB Feedback Input. FB senses the output voltage to regulate said voltage. Drive FB with a resistive voltage divider from the output voltage. The feedback threshold is 0.0V. 9 Power Good Output. The output of this pin is open-drain. Power good threshold is 90% low to high and 70% high to low of regulation value. 0 SS Soft-Start Control Input. SS controls the soft-start period. Connect a capacitor from SS to to set the soft-start period. VCC Bias Supply. Decouple with 0.μF to 0.22μF capacitor. The capacitance should be no more than 0.22μF. 2, 3 5 (Exposed Pad) Ground. The exposed pad must be soldered to a large PCB and connected to for maximum power dissipation. 4 A Analog Ground. Connect this pin to the system ground in PCB layout. Copyright 202 Richtek Technology Corporation. All rights reserved. 2 DS27-03 June 202

Function Block Diagram EN VCC FB 5k 3V.2V µa.7v Shutdown Comparator Regulator - - Lockout Comparator - V C Reference V A Ramp Generator Oscillator 500kHz - Error Amplifier S R - PWM Comparator Current Sense Amplifier V A Q Driver - BOOT V C 30pF 400k 0µA SS pf Copyright 202 Richtek Technology Corporation. All rights reserved. DS27-03 June 202 3

Absolute Maximum Ratings (Note ) Supply Input Voltage, ---------------------------------------------------------------------------------- 0.3V to 26V Switch Voltage, ----------------------------------------------------------------------------------------- 0.3V to (V IN 0.3V) Boot Voltage, BOOT ----------------------------------------------------------------------------------------- ( 0.3V) to ( 6V) Other Pins------------------------------------------------------------------------------------------------------ 0.3V to 6V Power Dissipation, P D @ T A = 25 C WDFN-4L 4x3 ------------------------------------------------------------------------------------------------.667W Package Thermal Resistance (Note 2) WDFN-4L 4x3, θ JA ------------------------------------------------------------------------------------------ 60 C/W WDFN-4L 4x3, θ JC ------------------------------------------------------------------------------------------ 7 C/W Junction Temperature ---------------------------------------------------------------------------------------- 50 C Lead Temperature (Soldering, 0 sec.) ------------------------------------------------------------------ 260 C Storage Temperature Range ------------------------------------------------------------------------------- 65 C to 50 C ESD Susceptibility (Note 3) HBM (Human Body Model) --------------------------------------------------------------------------------- 2kV Recommended Operating Conditions (Note 4) Supply Input Voltage, ---------------------------------------------------------------------------------- 4.5V to 2V Junction Temperature Range ------------------------------------------------------------------------------- 40 C to 25 C Ambient Temperature Range ------------------------------------------------------------------------------- 40 C to 5 C Electrical Characteristics (V IN = 2V, TA = 25 C unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit Shutdown Current I SHDN V EN = 0 -- 0 μa Quiescent Current I Q V EN = 2V, V FB = V -- 0.7 -- ma Upper Switch On Resistance R DS(ON) -- 20 -- mω Lower Switch On Resistance R DS(ON)2 -- 40 -- mω Switch Leakage I LEAK V EN = 0V, V = 0V or 2V -- 0 0 μa Current Limit I LIMIT V BOOT V = 4.V 5.4 6.5 -- A Oscillator Frequency f V FB = 0.75V 425 500 575 khz Short Circuit Frequency V FB = 0V -- 50 -- khz Maximum Duty Cycle D MAX V FB = 0.V -- 90 -- % Minimum On Time t ON -- 00 -- ns Feedback Voltage V FB 4.5V V IN 2V 0.796 0.0 0.2 V Feedback Current I FB -- 0 50 na EN Threshold Logic-High V IH 2 -- 5.5 Voltage Logic-Low V IL -- -- 0.4 V Enable Current V EN = 2V -- -- V EN = 0V -- 0 -- μa Copyright 202 Richtek Technology Corporation. All rights reserved. 4 DS27-03 June 202

Parameter Symbol Test Conditions Min Typ Max Unit Power Good Rising Threshold -- 90 -- % Power Good Falling Threshold -- 70 -- % Power Good Delay -- 20 -- μs Power Good Sink Current Capability Sink 4mA -- -- 0.4 V Power Good Leakage Current -- 0 -- na Under Voltage Lockout Threshold Under Voltage Lockout Threshold Hysteresis V UVLO V IN Rising 3. 4 4.2 V ΔV UVLO -- 400 -- mv VCC Regulator -- 5 -- V VCC Load Regulation I CC = 5mA -- 5 -- % Soft-Start Period t SS C SS = 47nF -- 4.7 -- ms Thermal Shutdown T SD -- 50 -- C Thermal Shutdown Hysteresis ΔT SD -- 30 -- C Note. Stresses beyond those listed Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability.bsolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. θ JA is measured at T A = 25 C on a high effective thermal conductivity four-layer test board per JEDEC 5-7. θjc is measured at the exposed pad of the package. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Copyright 202 Richtek Technology Corporation. All rights reserved. DS27-03 June 202 5

Typical Operating Characteristics Efficiency vs. Output Current Reference Voltage vs. Input Voltage 00 0.30 90 = 2V 0.25 Efficiency (%) 0 70 60 50 40 30 20 = 2V Reference Voltage(V) 0.20 0.5 0.0 0.05 0.00 0 0 VOUT =.22V, IOUT = 0A to 3A 0.795 0.790 0 0.5.5 2 2.5 3 4 6 0 2 4 6 20 22 Output Current (A) Input Voltage (V) Reference Voltage vs. Temperature Output Voltage vs. Output Current 0.4.226 0.3.224 Reference Voltage (V) 0.2 0. 0.0 0.79 0.7 Output Voltage (V).222.220.2.26.24 0.77 0.76-50 -25 0 25 50 75 00 25 Temperature ( C).22.20 = 2V, VOUT =.22V, IOUT = 0A to 3A 0 0.5.5 2 2.5 3 Output Current (A) Switching Frequency vs. Input Voltage Switching Frequency vs. Temperature 550 550 Switching Frequency (khz) 525 500 475 450 425 400 375 350 VOUT =.22V, IOUT = 0.A Switching Frequency (khz) 525 500 475 450 425 400 375 350 = 2V, VOUT =.22V, IOUT = A 4 6 0 2 4 6 20 22 Input Voltage (V) -50-25 0 25 50 75 00 25 Temperature ( C) Copyright 202 Richtek Technology Corporation. All rights reserved. 6 DS27-03 June 202

Current Limit vs. Input Voltage Current Limit vs. Temperature 2 0 0 9 Current Limit (A) 6 4 Current Limit (A) 7 6 5 2 0 4 3 = 2V, VOUT =.22V 4 6 0 2 4 6 20 22 Input Voltage (V) -50-25 0 25 50 75 00 25 Temperature ( C) Load Transient Response Load Transient Response (200mV/Div) (200mV/Div) I OUT (2A/Div) I OUT (2A/Div) = 2V, VOUT =.22V, IOUT = 0A to 3A Time (00μs/Div) = 2V, VOUT =.22V, IOUT = A to 3A Time (00μs/Div) Output Voltage Ripple Output Voltage Ripple VOUT (50mV/Div) VOUT (50mV/Div) V (0V/Div) V (0V/Div) I L (2A/Div) = 2V, IOUT = A IL (2A/Div) = 2V, IOUT = 3A Time (μs/div) Time (μs/div) Copyright 202 Richtek Technology Corporation. All rights reserved. DS27-03 June 202 7

Power On from V IN Power Off from V IN V IN (0V/Div) (0V/Div) VOUT (V/Div) (V/Div) V (5V/Div) I L (5A/Div) = 2V, VOUT =.22V, IOUT = 3A V (5V/Div) I L (5A/Div) = 2V, VOUT =.22V, IOUT = 3A Time (5ms/Div) Time (50ms/Div) Power On from EN Power Off from EN V EN (5V/Div) V EN (5V/Div) (V/Div) (V/Div) V (5V/Div) V (5V/Div) I L (5A/Div) = 2V, VOUT =.22V, IOUT = 3A I L (5A/Div) = 2V, VOUT =.22V, IOUT = 3A Time (2.5ms/Div) Time (50μs/Div) Copyright 202 Richtek Technology Corporation. All rights reserved. DS27-03 June 202

Application Information The IC is a synchronous high voltage buck converter that can support the input voltage range from 4.5V to 2V and the output current can be up to 3A. Output Voltage Setting The output voltage is set by an external resistive divider according to the following equation : V OUT = V R FB R2 where V FB is the feedback reference voltage 0.0V (typ.). The resistive divider allows the FB pin to sense a fraction of the output voltage as shown in Figure. R FB R2 Figure. Output Voltage Setting External Bootstrap Diode Connect a 00nF low ESR ceramic capacitor between the BOOT pin and pin as shown in Figure 2. This capacitor provides the gate driver voltage for the high side MOSFET. It is recommended to add an external bootstrap diode between an external 5V and BOOT pin for efficiency improvement when input voltage is lower than 5.5V or duty ratio is higher than 65%.The bootstrap diode can be a low cost one such as IN44 or BAT54. The external 5V can be a 5V fixed input from system or a 5V output of the IC. Note that the external boot voltage must be lower than 5.5V. 5V BOOT 00nF Figure 2. External Bootstrap Diode Soft-Start The IC contains an external soft-start clamp that gradually raises the output voltage. The soft-start timing is programmed by the external capacitor between SS pin and. The chip provides an internal 0μA charge current for the external capacitor. If 47nF capacitor is used to set the soft-start, the period will be 4.7ms (typ.). Under Voltage Lockout Threshold The IC includes an input Under Voltage Lockout Protection (UVLO). If the input voltage exceeds the UVLO rising threshold voltage (4.2V), the converter resets and prepares the PWM for operation. If the input voltage falls below the UVLO falling threshold voltage (3.V) during normal operation, the device stops switching. The UVLO rising and falling threshold voltage includes a hysteresis to prevent noise caused reset. Chip Enable Operation The EN pin is the chip enable input. Pulling the EN pin low (<0.4V) will shut down the device. During shutdown mode, the IC quiescent current drops to lower than μa. Driving the EN pin high (>2V, < 5.5V) will turn on the device again. For external timing control (e.g.rc), the EN pin can also be externally pulled high by adding a R EN * resistor and C EN * capacitor from the pin, as can be seen from the Figure 5. An external MOSFET can be added to implement digital control on the EN pin when front age system voltage below 2.5V is available, as shown in Figure 3. In this case, a 00kΩ pull-up resistor, R EN, is connected between V IN and the EN pin. MOSFET Q will be under logic control to pull down the EN pin. To prevent enabling circuit when V IN is smaller than the target value, a resistive voltage divider can be placed between the input voltage and ground and connected to the EN pin to adjust IC lockout threshold, as shown in Figure 4. For example, if an V output voltage is regulated from a 2V input voltage, the resistor R EN2 can be selected to set input lockout threshold larger than V. Copyright 202 Richtek Technology Corporation. All rights reserved. DS27-03 June 202 9

V IN Chip Enable R EN 00k Q C IN R3 00k BOOT 6 7 2, 3, 4, 5 EN 9 FB C SS VCC SS 0 47nF R T C BOOT L R R2 C OUT C C A 4 2, 3, 5 (Exposed Pad) Figure 3. Enable Control Circuit for Logic Control with Low Voltage V IN R EN 00k C IN 7 EN BOOT 6 2, 3, 4, 5 C BOOT L R EN2 R3 00k 9 FB VCC SS 0 C SS 47nF R T R R2 C OUT C C A 4 2, 3, 5 (Exposed Pad) Figure 4. The Resistors can be Selected to Set IC Lockout Threshold Power Good Output The power good output is an open-drain output and requires a pull up resistor. When the output voltage is 70% below its set voltage, will be pulled low. It is held low until the output voltage returns to within the allowed tolerances once more. During soft-start, is actively held low and only allowed to transition high after soft-start is over and the output voltage has reached 90% of its set voltage. Under Output Voltage Protection-Hiccup Mode For the IC, Hiccup Mode of Under Voltage Protection (UVP) is provided. When the FB voltage drops below half of the feedback reference voltage, V FB, the UVP function will be triggered and the IC will shut down for a period of time and then recover automatically. The Hiccup Mode of UVP can reduce input current in short-circuit conditions. Copyright 202 Richtek Technology Corporation. All rights reserved. 0 Inductor Selection For a given input and output voltage, the inductor value and operating frequency determine the ripple current. The ripple current ΔI L increases with higher and decreases with higher inductance. V V Δ I = L OUT OUT f L Having a lower ripple current reduces not only the ESR losses in the output capacitors but also the output voltage ripple. Highest efficiency operation is achieved by reducing ripple current at low frequency, but it requires a large inductor to attain this goal. For the ripple current selection, the value of ΔI L = 0.24(I MAX ) will be a reasonable starting point. The largest ripple current occurs at the highest V IN. To guarantee that the ripple current stays below a specified maximum, the inductor value should be chosen according to the following equation : VOUT VOUT L = f I L(MAX) V Δ IN(MAX) DS27-03 June 202

The inductor's current rating (caused a 40 C temperature rising from 25 C ambient) should be greater than the maximum load current and its saturation current should be greater than the short circuit peak current limit. Please see Table 2 for the inductor selection reference and it is highly recommended to keep inductor value as close as possible to the recommended inductor values for each as shown in Table. Table 2. Suggested Inductors for Typical Application Circuit Component Supplier Series Dimensions (mm) TDK VLF0045 0 x 9.7 x 4.5 TDK SLF2565 2.5 x 2.5 x 6.5 TAIYO YUDEN NR040 x x 4 Input and Output Capacitors Selection The input capacitance, C IN, is needed to filter the trapezoidal current at the source of the high side MOSFET. To prevent large ripple current, a low ESR input capacitor sized for the maximum RMS current should be used. The RMS current is given by : VOUT I RMS = IOUT(MAX) VOUT This formula has a maximum at V IN = 2, where I RMS = I OUT / 2. This simple worst case condition is commonly used for design because even significant deviations do not offer much relief. Choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design. For the input capacitor, one 22μF low ESR ceramic capacitors are recommended. For the recommended capacitor, please refer to table 3 for more detail. Table 3. Suggested Capacitors for C IN and C OUT Location Component Supplier Part No. Capacitance (μf) Case Size C IN MURATA GRM32ER7C226M 22 20 C IN TDK C3225X5RC226M 22 20 C OUT MURATA GRM3CR60J476M 47 206 C OUT TDK C3225X5R0J476M 47 20 C OUT MURATA GRM32ER7C226M 22 20 C OUT TDK C3225X5RC226M 22 20 The selection of C OUT is determined by the required ESR to minimize voltage ripple. Moreover, the amount of bulk capacitance is also a key for C OUT selection to ensure that the control loop is stable. Loop stability can be checked by viewing the load transient response. The output ripple, Δ, is determined by : Δ Δ VOUT IL ESR fc OUT Higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. Their high ripple current, high voltage rating and low ESR make them ideal for switching regulator applications. However, care must be taken when these capacitors are used at input and output. When a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, V IN. At best, this ringing can couple to the output and be mistaken as loop instability. At worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at V IN large enough to damage the part. Thermal Shutdown Thermal shutdown is implemented to prevent the chip from operating at excessively high temperatures. When the junction temperature is higher than 50 C, the chip will shut down the switching operation. The chip will automatically resume switching, once the junction temperature cools down by approximately 30 C. Copyright 202 Richtek Technology Corporation. All rights reserved. DS27-03 June 202

EMI Consideration Since parasitic inductance and capacitance effects in PCB circuitry would cause a spike voltage on pin when high side MOSFET is turned-on/off, this spike voltage on may impact on EMI performance in the system. In order to enhance EMI performance, there are two methods to suppress the spike voltage. One way is by placing an R-C snubber (R S *, C S *) between and and locating them as close as possible to the pin, as shown in Figure 5. Another method is by adding a resistor in series with the bootstrap capacitor, C BOOT, but this method will decrease the driving capability to the high side MOSFET. It is strongly recommended to reserve the R-C snubber during PCB layout for EMI improvement. Moreover, reducing the trace area and keeping the main power in a small loop will be helpful on EMI performance. For detailed PCB layout guide, please refer to the section Layout Considerations. V IN R EN * C EN * C IN R3 00k 7 EN 9 VCC 6 BOOT 2, 3, 4, 5 FB SS 0 C SS 47nF C BOOT C S * R S * R T L R R2 C OUT * : Optional C C A 4 2, 3, 5 (Exposed Pad) Figure 5. Reference Circuit with Snubber and Enable Timing Control Thermal Considerations For continuous operation, do not exceed absolute maximum junction temperature. The maximum power dissipation depends on the thermal resistance of the IC package, PCB layout, rate of surrounding airflow, and difference between junction and ambient temperature. The maximum power dissipation can be calculated by the following formula : P D(MAX) = (T J(MAX) T A ) / θ JA where T J(MAX) is the maximum junction temperature, T A is the ambient temperature, and θ JA is the junction to ambient thermal resistance. For recommended operating condition specifications, the maximum junction temperature is 25 C. The junction to ambient thermal resistance, θ JA, is layout dependent. For WDFN-4L 4x3 package, the thermal resistance, θ JA, is 60 C/W on a standard JEDEC 5-7 four-layer thermal test board. The maximum power dissipation at T A = 25 C can be calculated by the following formula : P D(MAX) = (25 C 25 C) / (60 C/W) =.667W for WDFN-4L 4x3 package The maximum power dissipation depends on the operating ambient temperature for fixed T J(MAX) and thermal resistance, θ JA. The derating curve in Figure 6 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation. Maximum Power Dissipation (W).0 Four-Layer PCB.50.20 0.90 0.60 0.30 0.00 0 25 50 75 00 25 Ambient Temperature ( C) Figure 6. Derating Curve of Maximum Power Dissipation Copyright 202 Richtek Technology Corporation. All rights reserved. 2 DS27-03 June 202

Layout Considerations Follow the PCB layout guidelines for optimal performance of the IC. Keep the traces of the main current paths as short and wide as possible. Put the input capacitor as close as possible to the device pins ( and ). node is with high frequency voltage swing and should be kept at small area. Keep analog components away from the node to prevent stray capacitive noise pickup. Connect feedback network behind the output capacitors. Keep the loop area small. Place the feedback components near the IC. Connect all analog grounds to a common node and then connect the common node to the power ground behind the output capacitors. An example of PCB layout guide is shown in Figure 7 for reference. Place the input and output capacitors as close to the IC as possible. C IN should be connected to inductor by wide and short trace and keep sensitive components away from this trace. L C BOOT BOOT EN 4 2 3 4 5 3 2 0 6 9 7 5 A VCC SS FB C SS R T R2 R Place the feedback as close to the IC as possible. COUT Figure 7. PCB Layout Guide Copyright 202 Richtek Technology Corporation. All rights reserved. DS27-03 June 202 3

Outline Dimension 2 2 DETAIL A Pin # ID and Tie Bar Mark Options Note : The configuration of the Pin # identifier is optional, but must be located within the zone indicated. Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A 0.700 0.00 0.02 0.03 A 0.000 0.050 0.000 0.002 A3 0.75 0.250 0.007 0.00 b 0.0 0.300 0.007 0.02 D 3.900 4.00 0.54 0.6 D2 3.250 3.350 0.2 0.32 E 2.900 3.00 0.4 0.22 E2.650.750 0.065 0.069 e 0.500 0.020 L 0.350 0.450 0.04 0.0 W-Type 4L DFN 4x3 Package Richtek Technology Corporation 5F, No. 20, Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (63)552679 Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries. 4 DS27-03 June 202