163 39th Southeaster Symposium o System Theory Mercer Uiversity Maco, GA, 31207, March 4-6, 2007 MB3.3 Phase Delay Measuremet ad Calibratio i Built- Aalog Fuctioal Testig Jie Qi, Studet Member, EEE, Charles Stroud, Fellow, EEE, ad Foster Dai, Seior Member, EEE complete aalog tests such as frequecy respose, liearity, ad oise measuremets [1]. A ew mixed-sigal BST approach has bee proposed which icludes a direct digital sythesizer (DDS) based test patter geerator (TPG) ad multiplier/accumulator (MAC) based output respose aalyzer (ORA). Because the sigal is i digital form, it is easy to iclude differet modulatio capabilities i the DDS. Therefore, may aalog fuctioal tests, such as magitude ad phase respose i the frequecy domai, 3rd order itercept poit (P3) ad oise figure (NF) ca be performed i this architecture [1]. Some experimetal results for P3 ad frequecy respose (both phase ad gai). NTRODUCTON AND BACKGROUND M ixed-sigal Built- Self-Test (BST) is ow i more usig this BST architecture have bee preseted i [1] to demad tha ever. First, aalog fuctioality tests demostrate the feasibility ad accuracy of the BST approach. based o the traditioal methodology of maual testig costs this paper, we discuss the effect of phase delay o the much more moey ad time due to the ever-icreasig implemetatio ad accuracy of the MAC-based ORA. operatioal frequecy ad complexity of moder additio, through experimetatio with the BST circuitry, a mixed-sigal itegrated circuits (Cs). For example, radio simple compariso betwee the MAC-based ORA ad frequecy itegrated circuit (RFC) test cost ca be as as FFT-based BST scheme is also preseted. The paper is 50% of the total cost, depedig o the complexity of the orgaized as follows. Sectio 2 gives a overview of the fuctioality to be tested [1]. Secod, the operatioal BST approach. This is followed by a detailed discussio of frequecy ad complexity of moder mixed-sigal Cs make it the effect of phase delay o the MAC-based ORA i Sectio 3. difficult to perform test o these Cs. Fially, with a rapidly Some experimetal results related to the MAC-based ORA are icreasig level of itegratio, the umber of iput/output (10) preseted i Sectio 4 ad the paper cocludes i Sectio 5. pis does ot icrease accordigly such that observability of. OVERVEW OF BST ARCHTECTURE iteral compoets is lower compared with traditioal Cs [2]. Therefore, it becomes more attractive to automate the The mixed-sigal BST architecture, illustrated i Fig. 1, aalog testig process with low-cost, built-i test circuitry. is capable of accurate o-chip aalog fuctioal order to perform a suite of aalog fuctioality tests, measuremets [ 1]. order to miimize the area ad such as liearity, frequecy respose, ad oise figure (NF) performace pealty o the aalog circuitry, the majority of measuremet, i a BST eviromet, the frequecy spectrum the BST circuitry resides i the digital portio of the of the sigal comig from the device uder test (DUT) eeds mixed-sigal system. The digital portio of the BST circuitry to be measured ad aalyzed by a output respose aalyzer icludes a DDS-based TPG, a MAC-based ORA, ad a test (ORA) icluded i the BST circuitry [3]. A few techiques cotroller. The test scheme utilizes the existig have bee proposed to perform o-chip frequecy-domai digital-to-aalog coverters (DACs) ad aalog-to-digital testig of mixed-sigal circuits i [4]-[7]. However, most of coverters (ADCs) typically associated with most these approaches focus oly o oe or two simple parameter mixed-sigal architectures to provide accurate aalog tests such as cut-off frequecy of a filter ad caot perform fuctioality testig ad measuremets while miimizig the hardware added for BST. The oly test circuitry added to the aalog domai is loopback capabilities eeded to facilitate Mauscript received October 13, 2006. oe or more retur paths for the test sigals to the ORA. The Jie Qi is with Dept. of Electrical & Computer Egieerig, 200 Brou umber ad locatio of these loopback capabilities determies Hall, Aubur, AL 36849-5201 USA (e-mail: qijiel @aubur.edu). the accuracy ad resolutio of tests ad measuremets Charles Stroud is with Dept. of Electrical & Computer Egieerig, 200 Brou Hall, Aubur, AL 36849-5201 USA (phoe: 334-844-1806; fax: associated with a give aalog fuctio. Abstract-A Built- Self-Test (BST) approach has bee proposed for fuctioality measuremets of aalog circuitry i mixed-sigal systems. The BST circuitry cosists of a direct digital sythesizer (DDS) based test patter geerator (TPG) ad multiplier/accumulator (MAC) based output respose aalyzer (ORA). this paper we ivestigate ad discuss the effects of phase delay o aalog fuctioality measuremets i mixed-sigal systems whe usig MAC-based ORAs. We show that phase delay has a critical impact o measuremet results ad that the MAC-based ORA is a effective method for measurig phase delay. 334-844-1809; e-mail: strouce@aubur.edu). Foster Dai is with Dept. of Electrical & Computer Egieerig, 200 Brou Hall, Aubur, AL 36849-5201 USA (e-mail: daifa0l @aubur.edu). 1-4244-1051-7/07/$25.00 2007 EEE. 145
164 f_nco1 sifl(2 flfltck+9l) - v2_ v 2, 821 s1^^ 1 fi _X si(2zf2tck+ 02) ORA TPG Accm 03aE 3si(2zf3 TClk+03) f2( TCk): Mut2 Fig. 1. The DDS-based TPG cosists of three umerically cotrolled oscillators (NCOs) ad utilizes the existig DAC from the mixed-sigal system to complete the DDS. Fig. 2 shows a more detailed view of the umerically cotrolled oscillator (NCO) used i the TPG. The phase accumulator is used to geerate the phase word based o the frequecy word f ad the iitial phase word 9. The the NCO utilizes a look-up table (LUT) to covert the trucated phase word sequece to a digital sie wave sequece show i Fig. 2. The output sie wave frequecy is determied as f =f clk 2 where is the word width of the phase accumulator. The digital sie wave serves two purposes. Oe purpose is to produce a aalog stimulus to the DUT through the DAC. The other is to provide i-phase ad out-of-phase test toes for the MAC-based ORA. f Phase Accumulator ~L Fig. 2. NCO used i TPG. The ORA cosists of two sets of NxN-bit multiplier ad M-bit accumulator pairs with each MAC performig i-phase ad out-of-phase aalysis respectively. the desig of the ORA, N is the umber of bits from the DDS ad ADC ad M is chose such that K<2M 2N, where K is the legth of the BST sequece i clock cycles. A more detailed descriptio of how the MAC-based ORA works is give i the followig sectio.. OVERVEW OF PHASE DELAY While performig the frequecy respose, liearity ad NF measuremets, fl(tclk) ad f2(tclk) is set to cos(atclk) ad si(atclk) respectively. As a result, the DC1 ad DC2 accumulator values ca be described as Geeral model of BST architecture. (1) 146 DC1 = Z f(tlk) COS(WT(lk)' DC2 = E (Tck) si(fiotck ) From (2) ad (3), it ca be see that DC1 ad DC2 are the i-phase ad out-of-phase compoets of the sigalf(tclk) at frequecy c. The sigal f(tclk)'s Fourier Trasform F(w) ca also be expressed through DC1 ad DC2 accordig to the followig formula: F(o) = (2) (3) f(tlk))ejtlk =DC,(ow)+j.DC2(w) (4) From (4), the sigalfl(tclk)'s frequecy spectrum, F(w), withi the badwidth ca be measured through the DC1 ad DC2 by sweepig the frequecy c over the iterested badwidth. compariso with the FFT which computes F(w) over the etire bad at the same time, the MAC-based ORA i Figure 1 oly measures F(w) at oe frequecy poit at a time with the etire spectrum obtaied through successive measuremets. From the fuctio F(w), the amplitude A(0) ad the phase z5(co) of the spectrum ca be derived as follows: where F(v) = DC, (v) + j DC2(v) =A(-)e A4(co)=tg 1 DC2() DC,(o)) A()) = F(o))e-jA0(w) f (T(lk). ej A()] (5) = (f(tk) * cos(cotcl -AA()) These two parameters are used much more widely i aalog fuctioal measuremets. The amplitude respose A(0) is of iterest because may importat parameters, such as cut-off frequecy, i-bad ripple, badwidth, etc., are determied by it. The phase respose 45(co) represets the delay itroduced by electrical devices. t is also because of the phase delay that there is ormally a phase differece betwee the exteral path through the DUT ad the iteral (6) (7)
165 that it does't require ay extra circuitry to calculate the amplitude oce the phase delay is determied. However, there are also some disadvatages associated with it. First, a extra accumulatio sequece is required to obtai the amplitude respose, which will slow dow the processig speed ad legthe testig time. Secod, this approach caot be used for MF measuremet. Usually the oise i electric devices is modeled as a white Gaussia oise process with time-varyig phase, which makes it impossible to perform NF measuremet through (7). Compared with the first approach, the secod techique ca perform the phase ad amplitude measuremet almost simultaeously ad does ot have the costraits that the first approach has for the NF measuremet. However, extra hardware to realize the divisio ad siusoidal operatio show i (8) is required. A commo problem associated with the first two approaches is that their amplitude calculatio is based o the phase delay determied beforehad. So if there is ay error i the phase delay calculatio, the error will propagate to the subsequet amplitude calculatio. However, the third approach does't have this drawback because the amplitude ad phase are calculated idepedetly through (6) ad (10), but the cost is the extra hardware to implemet the square ad square root operatios. path from the TPG to the ORA (refer to Fig. 1). The phase delay is a importat issue to the MAC-based ORA because it will affect the accuracy ad implemetatio of the BST approach. Oce the phase retardatio z5(w) is determied based o (6), A(0) ca be measured through DC, accordig to (7) if the test toe geerated by NCO ca be phase-adjusted usig 4o(oc). However, with pre-determied 50(69), A(0) ca also be calculated as follows: A(w) cos (8) si AOu(c) Ai(w) For a o-chip test, we do't have to set up a full-legth arcta LUT to get the exact phase delay from DC, ad DC2. First the quadrat of J0(m) ca be determied from the sig bits of DC, ad DC2. Before we further the discussio, we defie a ew term, the absolute phase offset of z5(w) i the correspodig quadrat ad it ca be calculated through the formula as g-1 DC2(w)l g 1 DC1(o)l D(co) DC2(w) DC1(co)l DC2(co) (9) DC1(co)l DC2(co)l TABLE Pros ad cos of the three approaches The relatioship betwee A5(ca) ad Ai5(ca) is show i Table. Therefore, A5(ca) ca be idetified with A75(ca) whose value rage is [0, 45 ]. Upo the aalysis util ow, the arcta LUT ca be decreased by half. Furthermore, the arcta(dc2jdc) ca be represeted by the ratio of the DC2/DC1 whe DC2/DC1 is very small. So the legth of the arcta LUT ca be compressed further such that the hardware resources used by the phase calculatio ca be miimized. Approach costraits propagatio error TABLE DC1>0; DC2>0 DC1>O; DC2<0 A0(o))=3600-A0o(Co) DC1<0; DC2>0 Ai0(co)=1800-Ao0(6o) DC1<O;DC2<0 Ai0(co)=1800+A0o(wq) =2700+Ao/o(w) Ab(w)=900+A0o(w) A,(w) =2700- Aoo(c) Basically, there are three techiques to measure ad calibrate the phase delay. Oe is to adjust the phase of the outgoig test toe i the NCO such that the DUT output is i phase with the sigal to be mixed i the ORA ad the make the amplitude measuremet. The secod approach is to calculate the corrected amplitude accordig to (8). The last method is to obtai the amplitude directly from DC1 ad DC2 as follows: A(o) = 2DC+DC #3 Low Low t caot be used for NF Measuremet. Yes o o yes o The advatages ad disadvatages of these three approaches are summarized i the Table. The bold etries i the table are the desired properties for the ideal ORA. Through such a compariso, the third approach is see to be the most preferred strategy. The oly drawback of this approach is the extra hardware overhead. Because the amplitude is usually measured ad evaluated i the uit of db i real-life applicatios, the calculatio of (10) ca be trasformed to the logarithm domai as DC11<1 DC21 Ab(o)) 900 Ab0(o) A(60) #2 hardware overhead speed RELATONSHP BETWEEN AQ(C) AND A0(60) DC11>1 DC21 A (co) =A b0() #1 A (o) = 20 logl0 (A(w)) og (D C 2 + DC2)(11) log2 10 19 where A (c) is the measured amplitude i db uit. The hardware implemetatio of (11) ca be doe with a LUT or simple liear approximatio algorithm [8] depedig o the precisio requiremet. (10) V. EXPERMENTAL RESULTS All these three approaches have their ow advatages ad disadvatages. The most attractive merit of first approach is We have implemeted the BST architecture show i 147
166 Fig. 1 i hardware to perform the liearity, frequecy respose, ad NF measuremets. The digital portio of the BST circuitry was implemeted i a Xilix Sparta XC2S50 FPGA o a Xilix XSA50 prited circuit board (PCB). A 8-bit DAC with a low-pass filter ad a 8-bit ADC were implemeted o a separate PCB with a separate power supply. this sectio, we preset some experimetal results to show the critical impact of phase delay o the measuremet result obtaied through the ORA. A. Phase Delay troduced by BST Circuit The sesitivity ad accuracy of the measuremets that ca be obtaied with this BST approach ca be particularly illustrated from a desig error i the origial BST circuitry implemeted i [1]. We foud that there was a extra clock cycle delay i the path from the TPG, through MUX4 (see Fig. 1), to the ORA. Workig i this mode, the BST circuitry bypasses the DAC, DUT, ad ADC totally ad should itroduce o phase delay. However, Fig. 3 shows a phase delay measured by the origial BST cofiguratio i [1]. Whe the extra delay was removed, the phase respose show i Fig. 4 was obtaied. Fig. 4 also illustrates that liear phase delay error is itroduced by the ORA if the accumulatio does ot stop at a iteger multiple of the period of the sie wave used to make the phase measuremet. The reaso is that the accumulatio caot totally cacel the o-dc sigal show as the "humps" i the curves of both Fig. 3 ad Fig. 4. circuitry ad the exteral test equipmets ad this draw i Fig. 5. The other curve i the figure represets the phase delay caused by the DAC/ADC pair ad Amplifier measured by modified BST circuitry. Comparig these two curves, we ca see that they are close to each other, which also shows that the phase delay i the DAC/ADC cotributes to most of the phase measuremet error i [1]. 2.5 2 1,5 _5 L- 0 i -2 k/ 10 20 38 Fig. 4. Ffequecq (kho) Phase error with delay removed error is Phase Delay by the aalog BST circuitry - Phase Respose Error Shou i [18] 48-4.0-8 a Fig. 3. to e 28 Phase error due to delay itroduced i TPG While performig measuremets o the DUT, the test sigal must pass through the exteral path composed of the DAC with amplifier for low pass filter, the DUT ad the ADC. So actually, the measured phase respose is the total phase delay caused by all these four devices together. Therefore, the phase delay itroduced by the DAC/ADC pair ad amplifier also eeds to be well calibrated out. Fig. 5 illustrates the impact of this kid of phase delay o the accuracy of the BST circuitry. The reported phase respose measured by the BST circuitry i [1] shows a apparet error betwee the phase measuremet doe by origial BST -10 0 10 20 30 40 50 Fig. 5. Frequecy (khz) Phase delay caused by DAC/ADC circuitry B. mplemetatios of the MAC-based ORA The MAC-based ORA was modeled i Verilog with parameterized umber of iput bits (N, which correspods to the umber of multiplier bits) ad umber of output bits (M, which correspods the umber of accumulator bits) to support the requiremet for applicatios with varied bit-width. our implemetatio, the BST circuitry is sythesized ito a Xilix Sparta XC2S50 FPGA. Table ad V summarize the resources required to implemet the MACs as a fuctio of differet values for N ad M. As ca be see, whe M icreases, the logic required to realize the accumulator will icrease correspodigly. Table ad Table V show a liear relatioship betwee the resource usage ad M if N is fixed. fact, the accumulator 148
167 requires exactly oe slice for every two bits of the accumulator. However, the complexity of a multiplier icreases much faster tha a accumulator with icreasig size, which is also illustrated by Table ad Table V. The MAC-based ORA ca be also compared to the FFT-based BST approach proposed i [7] ad the FFT implemetatios i [9]. For a 256 poit FFT with a 32 poit approximate kerel, [7] used a XC2V8000, which itself is almost 250 times larger tha the XC2S 15 device, for implemetatio of that FFT-based BST approach. The maximum clock frequecy of that approach was reported to be betwee 1 ad 2 MHz while our approach will operate at 48.5 MHz. MAC-based ORA is much simpler ad cheaper, ad ca also achieve some flexibility that the FFT-based approach caot provide. For example, the maximum umber of the poits that a FFT processor ca compute is fixed, such that it is difficult to adjust the frequecy resolutio whe usig a FFT-based approach. stead, the frequecy resolutio ca be easily tued with the step size of the sweepig frequecy i our ORA. additio, we are typically oly iterested i several frequecy poits or i a arrow badwidth, which ca be doe easily usig our ORA scheme while FFT-based scheme has to compute a great amout of iformatio that may be useless because FFT processes the whole frequecy domai at oe time. The trade-off is i test time sice the FFT ca compute the etire frequecy spectrum cocurretly, while our MAC-based ORA measures oe frequecy compoet at a time. TABLE Number of slices vs. MAC cofiguratio M=28 M=32 M=36 M=40 M=44 N=8 N=12 N=16 74 76 78 80 82 129 131 133 135 137 204 206 208 210 V. CONCLUSONS order to avoid the drawbacks associated with the covetioal approaches to perform the mixed-sigal testig ad measuremet, a BST scheme has bee proposed usig a DDS-based TPG ad a MAC-based ORA [1]. Both the theoretical aalysis ad experimetal results from actual measuremets show that the phase delay is very importat to the implemetatio ad accuracy of the MAC-based ORA. compariso with the FFT-based approach, the MAC-based ORA ca be realized usig much more flexible ad simpler BST circuitry with less area pealty, which is what a ideal BST scheme is supposed to be. TABLE V Number of slices vs. MAC cofiguratio M=28 M=32 M=36 M=40 M=44 N=8 N=12 N=16 139 143 147 151 155 244 248 252 256 260 387 391 395 399 TABLE V RESOURCES USAGE OF 256-PONT FF17 MPLEMENTATONS ON VRTEX TYPE Pipelied Burst /O Miimum Resources # OF SLCES #0OF 18X18-BT MULTPLERS TRANSFORM FREQUENCY 2633 2743 1412 12 9 3 641 khz 313 khz 133 khz REFERENCES F. Dai, C. Stroud, ad D. Yag, "Automatic Liearity ad Frequecy Respose Tests with Built-i Patter Geerator ad Aalyzer," EEE Tras. o VLS Systems., vol. 14, o. 6, pp. 561-572, 2006. [2] M. Bushell, V. Agrawal, Essetials of Electroic Testig for Digital, Memory ad Mixed-Sigal VLS Circuits, Spriger, 2006. [3] J. Qi, C. Stroud ad F. Dai, "Phase Delay i MAC-based Aalog Fuctioal Testig i Mixed-Sigal Systems," Proc. EEE North Atlatic Test Workshop, pp. 44-50, 2006. [4] C.-Y. Chao, H.-J. Li, ad L. Milor, "Optimal Testig of VLS Aalog Circuits," EEE Tras. o Computer-Aided Desig, vol. 16, o. 1, pp. 58-76, 1997. [5] M. Toer ad G. Roberts, "A BST Techique for a Frequecy Respose ad termodulatio Distortio Test of a Sigma-Delta ADC," Proc. EEE VLS Test Symp., pp. 60-65, 1994. [6] B. Provost ad E. Sachez-Siecio, "O-chip Ramp Geerators for Mixed-Sigal BST ad ADC Self-Test," EEE J. Solid-State Circuits, vol. 38, pp. 263-273, 2003. [7] J. Emmert, J. Cheatham, B. Jagaatha, S. Umarai, "A FF1 Approximatio Techique Suitable for O-Chip Geeratio ad Aalysis of Siusoidal Sigals", Proc. EEE teratioal Symp. o Defect ad Fault Tolerace i VLS Systems, pp. 361-367, 2003. [8] M. Lu, Arithmetic ad Logic i Computer System, Joh Wiley ad Sos, 2004. [9], "Fast Fourier Trasform v3.2," Xilix, c., August 2005. [1] [9] presets a umber of FFT implemetatios for differet poit sizes o differet series FPGAs. We chose three types of 256-poit FFT implemetatios with 16-bit iput implemeted o a Xilix Virtex FPGA for compariso. The resources usage ad performace of these implemetatios are summarized i Table V. Cosider the fastest pipelied implemetatio i Table V as a example. With almost 7 times more slices ad twelve 18-bitxl8-bit multipliers (which, it should be oted, are ot used i our BST circuitry), the pipelied type FFT processor ca oly ru at 641kHz. Furthermore, it should be oted that if we were to use the existig 1 8x1 8 multipliers i Virtex for the multiplier i our MAC-based ORA, we would oly require oe multiplier ad the umber of slices eeded for the accumulator is equal to M/2. As a result the largest cofiguratio i Tables ad V would oly require oe multiplier ad 22 slices. From such a compariso, we ca coclude that the 149