COMPARATIVE STUDY ON MCPWM STRATEGIES FOR 15 LEVEL ASYMMETRIC INVERTER

COMPARATIVE STUDY ON MCPWM STRATEGIES FOR 15 LEVEL ASYMMETRIC INVERTER V.ARUN #1, B.SHANTHI #2, K.RAJA #3 #1 Department of EEE, Arunai Engineering College, Thiruvannamalai, Tamilnadu, India. #2 Centralised Instrumentation and Service Laboratory, Annamalai University, Chidambaram, Tamilnadu, India. #3 Department of EEE, Arunai Engineering College, Thiruvannamalai, Tamilnadu, India. Abstract This paper focuses on a new topology of multilevel inverter with a reversing-voltage technique. This topology requires fewer components compared to conventional inverters and requires fewer carrier signals and gate drives. Multilevel inverter is triggered using Unipolar Sine Pulse Width Modulating (USPWM) strategies using sine reference and trapezoidal reference with triangular carriers. It include Phase Disposition (PD) strategy, Alternate Phase Opposition Disposition (APOD) strategy, Carrier Overlapping (CO) strategy and Variable Frequency (VF) strategy. The performance measures like Total Harmonic Distortion (THD), V RMS (fundamental), crest factor, form factor and distortion factor are evaluated for various modulation indices. Simulation is performed using MATLAB-SIMULINK. Index Terms APOD, CO, PD, VF, PWM. I. INTRODUCTION Multilevel inverters have become an attractive choice as a partial solution to the improvement of the global conversion chain efficiency. Multilevel inverter is a switching converter where the appropriate control of an arrangement of switching devices allows combining diverse input voltages to synthesize a sinusoidal output voltage waveform.rathore et al[1] generalized optimal pulsewidth modulation of multilevel inverters for low-switching-frequency control of medium-voltage high-power industrial AC drives. Najafi et al [2] proposed design and implementation of a new multilevel inverter topology. Ahmadi et al [3] introduced a universal selective harmonic elimination method for high-power inverters. Gong et al[4] introduced a comparative study of multicell amplifiers for AC-power-source applications.zhang and Sun [5] analyzed an efficient control strategy for a five-level inverter comprising flying-capacitor asymmetric H-bridge.Khoucha et al [6] proposed a comparison of symmetrical and asymmetrical threephase H-bridge multilevel inverter for DTC induction motor drives. Zhao [7] proposed multilevel circuit topologies based on the switched-capacitor converter and diode-clamped converter. Boora et al [8] developed voltage-sharing converter to supply singlephase asymmetrical four-level diode-clamped inverter with high power factor loads. Malinowski et al[9] proposed a survey on cascaded multilevel inverters. Dixon et al[10] developed asymmetrical multilevel inverter for traction drives using only one DC supply. This paper presents a single phase binary DC source 15 level inverter topology for investigation with various USPWM switching strategies. Simulations were performed using MATLAB-SIMULINK. Harmonic analysis and evaluation of different performance measures for various modulation indices have been carried out and presented. II. PROPOSED ASYMMETRICAL MULTILEVEL INVERTER The proposed new asymmetric cascaded multilevel inverter is shown in Figure 1. inverter consists of 3 sub multilevel inverter and H bridge. Conversion cell consists of separate voltage sources(v1,v2,v3) connected in cascade and two active switching elements that can make the output voltage in positive polarity with several levels.h bridge consists of four active switching element that can make the output voltage in positive or in negative polarity depending on the switching condition. By 229

using Vdc,2Vdcand 4Vdc, it can synthesize 15 output levels;-7vdc,-6vdc,-5vdc, -4Vdc, -3Vdc, -2Vdc, - Vdc, 0, Vdc, 2Vdc, 3Vdc,4Vdc,5Vdc,6Vdc,7Vdc. Expected output voltage level is given by Vn=2 n+1-1, Where n=1,2,4. m a =A m /(2*A c ) A. Unipolar Phase disposition PWM strategy (UPDPWM) Fig. 2 and 3 shows the sinusoidal and trapezoidal pulse width modulation of an m-level inverter, (m-1) carriers with the same frequency f c and same amplitude A c are positioned such that the bands they occupy are contiguous. If the reference wave is more than a carrier signal, then the active devices corresponding to that carrier are switched on. Otherwise, the devices switch off. Fig 1: proposed multilevel inverter III. MULTI CARRIER BASED PWM METHODS In this proposed work a unipolar sine and trapezoidal reference with a triangular carrier is used to generate firing pulses for a 15 level inverter. For an m-level inverter using unipolar multi-carrier strategies, (m-1)/2 carriers with the same frequency f c and same peak-to-peak amplitude A c are used. The reference waveform has amplitude A m and frequency f m and it is placed at the zero reference. The reference wave is continuously compared with each of the carrier signals. If the reference wave is more than a carrier signal, then the active devices corresponding to that carrier are switched on. Otherwise, the device switches off. There are many alternative strategies are possible, some of them are tried in this paper and they are: a. Phase disposition PWM strategy (UPDPWM). b. Alternate phase opposition disposition PWM strategy(uapodpwm). c. Carrier overlapping PWM strategy (UCOPWM). d. Variable frequency PWM strategy (UVFPWM). The formulae to find the Amplitude of modulation indices are as follows: Fig 2: Carrier arrangements for UPDPWM strategy with sinusoidal reference (m a = 0.9 and m f = 40) Fig 3: Carrier arrangements for UPDPWM strategy with trapezoidal reference (m a = 0.9 and m f = 40) B. Unipolar Alternate phase opposition disposition PWM strategy (UAPODPWM) In UAPOD strategy the carriers of same amplitude are phase displaced from each other by 180 degrees alternately. The carrier arrangement of sinusoidal references and trapezoidal reference are illustrated in figures 4 and 5 respectively. For PDPWM, APODPWM and VFPWM: For COPWM: m a = 2A m /( m-1)a c ) 230

Fig 4: Carrier arrangements for UAPODPWM (m a = 0.9 and m f = 40) Fig. 5. Carrier arrangements for UAPODPWM (m a = 0.9 and m f = 40) Fig 7: Carrier arrangements for UCOPWM strategy with trapezoidal reference (m a = 0.9 and m f = 40) D. Unipolar Variable frequency PWM strategy (UVFPWM) The number of switching s for upper and lower devices of chosen MLI is much more than that of intermediate switches in PWM using constant frequency carriers. In order to equalize the number of switching s for all the switches, variable frequency PWM strategy is used as illustrated in Fig.8 and 9 in which the carrier frequency of the intermediate switches is properly increased to balance the number of switching s for all the switches. C. Unipolar Carrier overlapping PWM strategy (UCOPWM) In UCOPWM strategy, carriers with the same frequency fc and same peak-to-peak amplitude Ac are disposed such that the bands they occupy are overlap each other; the overlapping vertical distance between each carrier is Ac/2. The carrier arrangement of sinusoidal references and trapezoidal reference are illustrated in figures 6 and 7 respectively. Fig 8: Carrier arrangements for UVFPWM strategy with sinusoidal reference (m a = 0.9 and m f = 40) Fig 6: Carrier arrangements for UCOPWM strategy with sinusoidal reference (m a = 0.9 and m f = 40) Fig 9: Carrier arrangements for UVFPWM strategy with trapezoidal reference (m a = 0.9 and m f = 40) 231

IV. SIMULATION RESULT The single phase binary DC source 15 level inverter is modeled in SIMULINK using power system block set. Switching signals for binary multilevel inverter using USPWM strategies are simulated. Fig.10 (a) and (b) respectively shows the 15 level output voltage generated by UPDPWM strategies with sinusoidal reference and its FFT plot. Fig.11 (a) and (b) respectively shows the 15 level output voltage generated by UPDPWM strategies with trapezoidal reference and its FFT plot. Fig.12 (a) and (b) respectively shows the 15 level output voltage generated by UAPODPWM strategies with sinusoidal reference and its FFT plot. Fig.13 (a) and (b) respectively shows the 15 level output voltage generated by UAPODPWM strategies with trapezoidal reference and its FFT plot.fig.14 (a) and (b) respectively shows the 15 level output voltage generated by UCOPWM strategies with sinusoidal reference and its FFT plot. Fig.15 (a) and (b) respectively shows the 15 level output voltage generated by UCOPWM strategies with trapezoidal reference and its FFT plot. Fig.16 (a) and (b) respectively shows the 15 level output voltage generated by UVFPWM strategies with sinusoidal reference and its FFT plot. Fig.17 (a) and (b) respectively shows the 15 level output voltage generated by UCOPWM strategies with trapezoidal reference and its FFT plot. Simulations were performed for different values of m a ranging from 0.8 to 1 and the corresponding %THD are measured using the FFT block and their values are shown in Table I. Table II represents the V RMS of the inverter output voltage. Table III represents the crest factor of the output voltage. Table IV and V represents the form factor and distortion factor of the output voltage. For ma= 0.9, it is observed from the figures[10b 11b 12b 13b 14b 15b 16b 17b] the harmonic energy is dominant in:10b) 39 th order in UPDPWM and triangular carrier.11b) 5 th,7 th,37 th,39 th order in UPDPWM.12b) 39 th order in UAPODPWM strategy with sinusoidal reference and triangular carrier.13b) 5 th,7 th,19 th, order in UAPODPWM strategy with trapezoidal reference.14b) 38 th,39 th, order in UCOPWM strategy with sinusoidal reference and triangular carrier.15b) 5 th,37 th,39 th order in UCOPWM strategy with trapezoidal reference.16b) 19 th,31 st,33th,37 th,39 th order in UVFPWM and triangular carrier.17b) 5 th,39 th,order in UVFPWM. The following parameter values are used for simulation: V dc =21.5V, R (load) = 100 ohms, f c =2000 Hz and f m =50Hz. Fig 10(a): Output voltage generated by UPDPWM Fig 10 (b): FFT plot for output voltage of UPDPWM Fig 11 (a): Output voltage generated by UPDPWM Fig 11 (b): FFT plot for output voltage of UPDPWM 232

Fig 12 (a): Output voltage generated by UAPODPWM Fig 14 (a): Output voltage generated by UCOPWM Fig 12 (b): FFT plot for output voltage of UAPODPWM Fig 14 (b): FFT plot for output voltage of UCOPWM Fig 13 (a): Output voltage generated by UAPODPWM Fig 15 (a): Output voltage generated by UCOPWM Fig 13 (b): FFT plot for output voltage of UAPODPWM Fig 15(b): FFT plot for output voltage of UCOPWM 233

Fig 16 (a): Output voltage generated by UVFPWM Fig 17 (a): Output voltage generated by UVFPWM Fig 16 (b): FFT plot for output voltage of UVFPWM Fig 17 (b): FFT plot for output voltage of UVFPWM TABLE I. %THD FOR DIFFERENT MODULATION INDICES Sine Trapezoidal Sine Trapezoidal Sine Trapezoidal Sine Trapezoidal 1 8.62 9.17 8.10 8.62 11.15 11.12 7.67 8.17 0.95 8.56 9.46 8.40 9.40 12.43 12.66 8.38 9.10 0.9 8.29 9.17 8.97 7.98 13.87 12.07 8.66 8.17 TABLE II.V RMS FOR DIFFERENT MODULATION INDICES Sine Trapezoidal Sine Trapezoidal Sine Trapezoidal Sine Trapezoidal 1 106.1 111.3 106.4 115.9 106.6 112.8 106.5 111.3 0.95 100.7 105.1 101.1 106.2 104.6 108.9 101.6 105.8 0.9 95.47 111.3 95.76 111.8 99.44 110.5 95.4 111.3 TABLE III.CF FOR DIFFERENT MODULATION INDICES Sine Trapezoidal Sine Trapezoidal Sine Trapezoidal Sine Trapezoidal 1 1.41371 1.415094 1.41444 1.41415 1.41467 1.414007 1.41408 1.413297 0.95 1.41318 1.413892 1.41441 1.414506 1.41491 1.41506 1.41437 1.413989 0.9 1.41405 1.415094 1.41395 1.415027 1.41495 1.413575 1.41404 1.413297 234

TABLE IV.FORM FACTOR FOR DIFFERENT MODULATION INDICES Sine Trapezoidal Sine Trapezoidal Sine Trapezoidal Sine Trapezoidal 1 1.918E+9 2.01E+09 1.924E+9 2.27E+04 1.95609 1.98E+09 2.03E+09 2.14E+04 0.95 1.94E+09 1.02E+04 1.92E+09 2.16E+09 1.97E+09 1.39E+09 1.98E+09 2.04E+04 0.9 1.8E+09 2.00E+09 1.91E+09 2.05E+09 1.9E+09 1.99E+09 1.77E+09 2.14E+04 TABLE V. DISTORTION FACTOR FOR DIFFERENT MODULATION INDICES Sine Trapezoidal Sine Trapezoidal Sine Trapezoidal Sine Trapezoidal 1 0.0009727 0.0022945 9.3E-05 0.005598 0.001235 0.002454 0.00083 0.002167 0.95 0.0013283 0.0027660 9.4E-05 0.001691 0.001808 0.002783 0.000683 0.002057 0.9 0.0007261 0.0022945 9.0E-05 0.00177 0.003449 0.005275 0.000667 0.002167 V. CONCLUSION In this paper, USPWM techniques for binary DC source 15 level inverter have been presented. Binary DC source multilevel inverter gives higher output voltage with reduced switch count and low harmonics. Performance factors like % THD,V RMS,CF,FF and DF have been evaluated presented and analyzed. It is found that the UVFPWM provides relatively lower %THD, UCOPWM strategy with trapezoidal reference is found to perform relatively higher fundamental RMS output voltage. CF is almost same for all the strategies. FF is almost same for all the strategies. DF relatively low in UPDPWM. REFERENCES [1] A. K. Rathore, J. Holtz, and T. Boller, Generalized Optimal Pulsewidth Modulation of Multilevel Inverters for Low- Switching-Frequency Control of Medium- Voltage High-Power Industrial AC Drives, IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, vol. 60, no. 10, pp. 4215 4224, 2013. [2] E. Najafi, A. Halim, and M. Yatim, Design and Implementation of a New Multilevel Inverter Topology, IEEE Transactions on Industrical Electronics, vol. 59, no. 11, pp. 4148 4154, 2012. [3] D. Ahmadi, K. Zou, C. Li, and J. Wang, A Universal Selective Harmonic Elimination Method for High-Power Inverters, IEEE TRANSACTIONS ON POWER ELECTRONICS, vol. 26, no. 10, pp. 2743 2752, 2011. [4] G. Gong, D. Hassler, and J. W. Kolar, A Comparative Study of Multicell Amplifiers for AC-Power-Source Applications, IEEE TRANSACTIONS ON POWER ELECTRONICS, vol. 26, no. 11, pp. 149 164, 2011. [5] Y. Zhang and L. Sun, An Efficient Control Strategy for a Five-Level Inverter Comprising Flying-Capacitor Asymmetric H- Bridge, IEEE TRANSACTIONS ON 235

INDUSTRIAL ELECTRONICS, vol. 58, no. 9, pp. 4000 4009, 2011. [6] F. Khoucha, M. S. Lagoun, A. Kheloui, and M. E. H. Benbouzid, A Comparison of Symmetrical and Asymmetrical Three-Phase H-Bridge Multilevel Inverter for DTC InductionMotor Drives, IEEE TRANSACTIONS ON ENERGY CONVERSION, vol. 26, no. 1, pp. 64 72, 2011. [7] F. J.Zhao,Y.Han,X.He,C.Tan,J.Cheng,and R.Zhao, Multilevel Circuit Topologies Based on the Switched-Capacitor Converter and Diode-Clamped Converter, IEEE TRANSACTIONS ON POWER ELECTRONICS,vol.26,no.8,pp.2127-2136, 2011. [8] A. A. Boora, A. Nami, F. Zare, A. Ghosh, and F. Blaabjerg, Voltage-Sharing Converter to Supply Single-Phase Asymmetrical Four-Level Diode-Clamped InverterWith High Power Factor Loads, IEEE TRANSACTIONS ON POWER ELECTRONICS,, vol. 25, no. 10, pp. 2507 2520, 2010. [9] M. Malinowski, K. Gopakumar, J. Rodriguez, and M. A. Pérez, A Survey on Cascaded Multilevel Inverters, IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS,, vol. 57, no. 7, pp. 2197 2206, 2010. [10] J. Dixon, J. Pereda, C. Castillo, and S. Bosch, Asymmetrical Multilevel Inverter for Traction Drives Using Only One DC Supply, IEEE TRANSACTIONS ON VEHICULAR TECHNOLOGY, vol. 59, no. 8, pp. 3736 374 3, 2010. K.Raja was born in 1987 at Panruti. He has obtained B.E in Electrical and Electronics Engineering from G.K.M College of Engineering and Technology, Chennai, India in 2009,and pursuing M.E degree in Power Electronics and Drives from Arunai Engineering College, Tiruvannamalai,India. He has been working in the teaching field for about 2 years. His areas of interest include Power Electronics, Electrical Machines, Multilevel Inverters and Converter. Contact number-+91-9843666296.email:rajakannan87@gmail.com. V.Arun was born in 1986 in Salem. He has obtained B.Tech (Electrical and Electronics) and M.E (Power Systems) degrees in 2007 and 2009 respectively from SRM University, Chennai, India and Sona College of Technology, Salem, India. He has been working in the teaching field for about 4 years. His areas of interest include power electronics, digial electronics and power systems. He has 7 publications in international journals. He has presented 15 technical papers in various national / international conferences. Currently, he is working as Assistant Professor in the Department of EEE, Arunai Engineering College, Tiruvannamalai. He is a life member of Indian Society for Technical Education. Contact number- +91-9500218228. E-mail:varunpse@yahoo.com. B.Shanthi was born in 1970 in Chidambaram. She has obtained B.E (Electronics and Instrumentation) and M.Tech (Instrument Technology) from Annamalai University and Indian Institute of Science, Bangalore in 1991 and 1998 respectively. She obtained her Ph.D in Power Electronics from Annamalai University in 2009.She is presently a Professor in Central Instrumentation Service Laboratory of Annamalai University where she has put in a total service of 20 years since 1992.Her research papers (7) have been presented in various / IEEE international /national conferences. She has 3 publications in national journal and 12 in international journals. Her areas of interest are: modeling, simulation and intelligent control for inverters. Contact number- +91-9443185211. Email: shancisl@gmail.com. 236