EM Insights Series Episode #1: QFN Package Agilent EEsof EDA September 2008
Application Overview Typical situation IC design is not finished until it is packaged. It is now very important for IC designers to understand the package s electrical performance from the early stage of design process as the operating frequency of ICs always goes up. What is the upper frequency limit that the package can operate? Is it possible to use a lower cost package type to lower the final product cost? What about the performance of package isolation? As an example, LO to RF leakage performance of an up- or down-converter IC depends not only on the IC s isolation performance but also on the package. Potential users and targeted market IC design engineers, package engineers RFIC, MMIC, RF SIP, and package manufacturers EM product used Electromagnetic Design System Generation 2 (EMDS G2) Page 2
Design Challenges Design challenges QFN (Quad Flat No-Lead) is very popular low cost package for RFIC, MMIC, and RF SiP applications. Most IC vendors use this package for their products. 3x3[mm],16-pin QFN package performs pretty good up to 15GHz, showing less than -18 db return loss with a typical package mounting scheme. However new designs require a higher operating frequency up to 20 GHz with the same package by optimizing the transition design on the circuit board. A 3D EM simulation is required however, designer doesn t want to learn new 3D EM tools Import/export files between different tools delays design cycle time Problem solved The 3mm x 3mm,16pin RF QFN package performance is improved by optimizing the impedance of input/output feed line and the transitional structure very quickly with the integrated 3D EM design flow using EMDS G2. Value delivered Designers can quickly design the best possible transition design within ADS without leaving ADS environment. Page 3
Page 4 Typical QFN packages
3x3 [mm] 16 Pin QFN Package Top metal 0.1 mm thick Top View Plastic encasement 0.2 mm thick Bottom View Bottom metal 0.1 mm thick Page 5
Substrate Stack-up Definition (EMDS G2) Substrate layers Dielectric brick: diel, diel2 Metallization (vias): pcvia1, 2, and 3 Layout layers Page 6
EMDS G2 QFN Package Simulation With Microstrip Transmission Line on PC Board PCB vias from QFN to ground Microstrip Line on ThinFilm substrate Chip Bottom view Top view Board microstrip feed Board Double bonding wires Good Up to 15 GHz! Page 7
Solution to Improve Package Performance 1. Increase the width of input/output transmission lines to make 50 ohm impedance Very simple to do in EMDS G2! 2. Use two lead frames instead of single to minimize the transitional impedance profile and split the double bonding to the two lead frames Wider line width Two lead frames and split bond wires Page 8
Improved Package Performance Results db(s11) db(s21) Red & blue: improved design Cyan & dark green: original design Page 9
EM Insights Series Episode #1: QFN Package Without leaving the ADS environment, you can quickly design the best possible transition using EMDS G2. Interested in learning more about this application? Request an evaluation copy of EMDS G2 http://www.agilent.com/find/eesof-emds-for-ads-evaluation Request a demo of EMDS G2 http://www.agilent.com/find/eesof-contact Page 10
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