DUAL THRESHOLD VOLTAGE FOR HIGH PERFORMANCE DOMINO LOGIC Azfar Satari Abdullah Bachelor of Engineering with Honours (Electronics and Telecommunication Engineering) 2009
UNIVERSITI MALAYSIA SARAWAK R13a BORANG PENGESAHAN STATUS TESIS Judul: DUAL THRESHOLD VOLTAGE FOR HIGH PERFORMANCE DOMINO LOGIC SESI PENGAJIAN: 2008/2009 Saya AZFAR SATARI BIN ABDULLAH (HURUF BESAR) mengaku membenarkan tesis * ini disimpan di Pusat Khidmat Maklumat Akademik, Universiti Malaysia Sarawak dengan syarat-syarat kegunaan seperti berikut: 1. Tesis adalah hakmilik Universiti Malaysia Sarawak. 2. Pusat Khidmat Maklumat Akademik, Universiti Malaysia Sarawak dibenarkan membuat salinan untuk tujuan pengajian sahaja. 3. Membuat pendigitan untuk membangunkan Pangkalan Data Kandungan Tempatan. 4. Pusat Khidmat Maklumat Akademik, Universiti Malaysia Sarawak dibenarkan membuat salinan tesis ini sebagai bahan pertukaran antara institusi pengajian tinggi. 5. ** Sila tandakan ( ) di kotak yang berkenaan SULIT TERHAD (Mengandungi maklumat yang berdarjah keselamatan atau kepentingan Malaysia seperti yang termaktub di dalam AKTA RAHSIA RASMI 1972). (Mengandungi maklumat TERHAD yang telah ditentukan oleh organisasi/ badan di mana penyelidikan dijalankan). TIDAK TERHAD Disahkan oleh (TANDATANGAN PENULIS) (TANDATANGAN PENYELIA) Alamat tetap: NO.1500,LRG E5, TAMAN SATRIA JAYA, BDC, STAMPIN, 93350, KUCHING, SARAWAK PN. SITI KUDNIE SAHARI Nama Penyelia Tarikh: 19 MAY 2008 Tarikh: CATATAN * Tesis dimaksudkan sebagai tesis bagi Ijazah Doktor Falsafah, Sarjana dan Sarjana Muda. ** Jika tesis ini SULIT atau TERHAD, sila lampirkan surat daripada pihak berkuasa/organisasi berkenaan dengan menyatakan sekali sebab dan tempoh tesis ini perlu dikelaskan sebagai SULIT dan TERHAD.
This Final Year Project attached here: Title : Dual Threshold Voltage for High Performance Domino Logic Student Name : Azfar Satari Bin Abdullah Matric No : 13770 has been read and approved by: Puan Siti Kudnie Sahari Date (Supervisor)
DUAL THRESHOLD VOLTAGE FOR HIGH PERFOMANCE DOMINO LOGIC AZFAR SATARI ABDULLAH This project is submitted in partial fulfilment of The requirements for the degree of Bachelor of Engineering with Honours (Electronics and Telecommunications Engineering) Faculty of Engineering UNIVERSITI MALAYSIA SARAWAK 2008/2009
***Dedicated to my lovely family***
ACKNOWLEDGEMENT I would like to take this opportunity to give my sincerest appreciation to my supervisor; Puan Siti Kudnie Bt Sahari who has gives her supports, advices, comments and suggestions all throughout the process of completion of this project. Thankfulness would like to give to my friends and family who give full supports to me either morally or financially. They always give encouragement to me when I faced problem throughout this project development. Finally, I express my gratefulness to in the individuals who involved direct or indirectly during the progress of this project. iii
ABSTRAK Dalam rekaan VLSI, ada satu litar rekaan yang dapat memenuhi keperluan untuk penukaran data berkelajuan tinggi dan kehilangan tenaga yang rendah. Litar itu dipanggil logik domino. Akan tetapi, jikalau voltan ambangan di dalam transistor dan bekalan voltan direndahkan, kebocoran arus sub ambangan mudah berlaku. Oleh itu, dua voltan ampangan logik domino telah diperkenalkan untuk menangani masalah tersebut. Nilai voltan ambangan rendah pada transistor dapat mengekalkan kecekapan logik domino manakala nilai voltan ambangan tinggi pada transistor untuk mengurangkan kebocoran sub ampangan arus. Dua rekaan diperkenalkan untuk menambahkan kecekapan dua voltan ambangan logik domino. Usulan rekaan yang pertama ialah DVth LSDWDK with SLEEP dan yang kedua ialah DVth LSDWDK with SLEEP+C 3 BBG. Sleep transistor dan C 3 BBG digunakan untuk mengurangkan kebocoran arus sub ambangan. Low swing digunakan untuk mengurangkan pertentangan arus di antara keeper dan pull down network. DVth LSDWDK with SLEEP mempunyai kelajuan setinggi 11.07% jika dibandingkan dengan dua voltan ampangan logik domino yang standart. Usulan rekaan yang kedua lebih menumpukan kepada penjimatan penggunaan tenaga di mana 46.39% lebih jimat dari penjimatan tenaga dua voltan ampangan logik domino yang standart. iv
ABSTRACT In VLSI designs, there is a design that could fulfill high speed transition and low power consumption. The design is called domino logic. However, to scale down the domino logic, threshold voltage and supply voltage need to be reduced. Scale down threshold voltage and supply voltage has caused the sub threshold leakage current increase exponentially. Thus, dual threshold voltage domino logic has been introduced to overcome these problems. Low threshold voltage transistors are used to maintain the performance and high voltage threshold transistors are used to reduce leakage current. In this project, a new design to improve the dual threshold voltage performance has been introduced. There are two proposed designs in this project. First proposed design is dual threshold voltage low swing domino logic with weakly driven keeper with sleep (DVth LSDWDK with SLEEP). Second proposed design is dual threshold voltage low swing domino logic with weakly driven keeper with sleep and C 3 BBG (DVth LSDWDK with SLEEP+ C 3 BBG). OR topology is used in evaluation tree. Sleep transistor and C 3 BBG are added in design to reduce the leakage current while low swing is used to reduce the contention current. DVth LSDWDK with SLEEP (first proposed design) has increased speed up to 19.64% and power saving up to 25.42% over standard dual threshold voltage domino logic. However, in term of power dissipation, DVth LSDWDK with SLEEP and C 3 BBG has increased power saving up to 46.39% over dual threshold voltage domino logic. v
TABLE OF CONTENTS CONTENTS PAGE ACKNOWLEDGEMENT ABSTRAK ABSTRACT TABLE OF CONTENTS LIST OF TABLES LIST OF FIGURES NOMENCLATURE iii iv v vi xiii xv xxii CHAPTER 1 INTRODUCTION 1.1 Project Overview 1 1.2 Project Scope 1 1.3 Project Objective 2 1.4 Project Outline 3 CHAPTER 2 LITERATURE REVIEW 5 2.1 Dynamic CMOS 5 2.1.1 Operation of Dynamic CMOS 5 2.1.2 Dynamic CMOS Properties 6 2.1.3 Issues and Solution 7 vi
2.1.3.1 Charge Leakage 7 2.1.3.2 Charge Sharing 9 2.1.3.3 Capacitive Coupling 10 2.1.3.4 Clock Feed Through 10 2.1.5.3 Power Delay Product (PDP) 13 2.2 Noise Margin 13 2.3 Noise Constraint 14 2.4 Inverter CMOS Design 15 2.5 Domino Logic 17 2.6 Dual Threshold Domino Logic 19 2.6.1 Evaluation Phase 21 2.6.2 Precharge Phase 21 2.6.3 Standby Phase 22 2.7 Keeper Sizing in Dual Threshold Voltage Domino Logic 23 2.8 Domino Logic with Variable Threshold Voltage Keeper (DVTVK) 24 2.8.1 Variable Threshold Voltage 25 2.8.2 Dynamic Body Bias Generator and Cross Coupling Capacitance Body Bias Generator (DBBG and C 3 BBG) 26 2.8.2.1 Dynamic Body Bias Generator (DBBG) 26 2.8.2.2 Cross Coupling vii
Capacitance Body Bias 27 Generator (C 3 BBG) 2.9 Low Swing Dual Threshold Voltage Domino 28 Logic CHAPTER 3 METHODOLOGY 3.1 Project Overview 30 3.2 Parameter Analysis 30 3.2.1 Reference Inverter 31 3.3.1.1 Transistor Sizing Analysis 32 3.3.1.2 Supply Voltage Analysis 33 3.2.1.3 Threshold Voltage 34 Analysis 3.3 Types of Domino Logic for Comparison Purpose 35 3.3.1 OR Standard Domino Logic with 36 Keeper (OR SDK) 3.3.2 OR Dual Threshold Voltage Domino Logic (OR DVthDL) 38 3.3.3 OR Dual Threshold Voltage Domino Logic with SLEEP (OR DVthDL with SLEEP) 40 3.4 Comparison Between OR Domino Logic Variable Threshold Voltage Keeper with C 3 BBG and DBBG (OR DVTVK- C 3 BBG and viii
OR DVTVK-DBBG) 42 3.5 Proposed Designs 44 3.5.1 First Proposed Design 44 3.5.1.1 OR Dual Threshold Voltage Low Swing Domino Logic Weakly Driven Keeper with Sleep Switch (OR DVth LSDWDK with SLEEP) 44 3.5.2 Second Proposed Design 46 3.5.2.1 OR Dual Threshold Voltage LSDWDK with C 3 BBG and Sleep Switch (OR DVth LSDWDK with SLEEP+ C 3 BBG) 46 3.6 Comparison of Propagation Delay, Power Dissipation and Power Delay Product Between The Proposed Designs, OR SDK, OR DVthDL and OR DVthDL with SLEEP. 48 CHAPTER 4 RESULTS, ANALYSIS AND DISCUSSIONS 50 4.1 Introduction 50 4.2 Reference Inverter 50 4.2.1 Results and Discussion of Transistor 51 Sizing Analysis ix
4.2.2 Results and Discussion of Supply 52 Voltage Analysis 4.2.3 Results and Discussion of Threshold 54 Voltage Analysis 4.3 Types of Domino Logic for Comparison Purpose 56 4.3.1 Results and Discussion of OR Standard Domino Logic with Keeper (OR SDK) 56 4.3.2 Results and Discussion of OR Dual Threshold Voltage Domino Logic with Keeper (OR DVthDL) 59 4.3.3 Results and Discussion of OR Dual Threshold Voltage Domino Logic with Keeper (OR DVthDL) 62 4.4 Comparison Between OR DVTVK- C 3 BBG and OR DVTVK-DBBG 65 4.5 Results and Discussion For Proposed Designs 68 4.5.1 OR Dual Threshold Voltage Low Swing Domino Logic Weakly Driven Keeper with Sleep Switch (OR DVth LSDWDK with SLEEP) 68 4.5.2 OR Dual Threshold Voltage LSDWDK x
with C 3 BBG and Sleep Switch (OR DVth LSDWDK with SLEEP+ C 3 BBG) 71 4.6 Comparing the Propagation Delay, Power Dissipation and Power Delay Product Between the Proposed Designs, OR SDK and OR DVthDL 75 4.6.1 OR DVth LSDWDK with SLEEP compare with OR SDK and OR DVthDL 76 4.6.1.1 Comparing The Propagation Delay 76 4.6.1.2 Comparing The Power Dissipation 78 4.6.1.3 Comparing The Power Delay Product 80 4.6.2 OR DVth LSDWDK with SLEEP+ C 3 BBG Compare with OR SDK and OR DVthDL 81 4.6.2.1 Comparing The Propagation Delay 81 4.6.2.2 Comparing The Power Dissipation 83 4.6.2.3 Comparing The Power Delay Product 84 4.6.3 The Proposed Design Compare with OR xi
DVthDL and OR DVthDL with SLEEP 86 4.6.3.1 Comparing The Propagation Delay 86 4.6.3.2 Comparing The Power Dissipation 88 4.6.3.3 Comparing The Power Delay Product 90 CHAPTER 5 CONCLUSIONS AND RECOMMENDATIONS 93 5.1 Conclusion 93 5.2 Recommendation 95 REFERENCES 97 APPENDIX A 99 APPENDIX B 106 xii
LIST OF TABLES Table Page 3.1 Settings for Transistor Sizing Analysis 33 3.2 Supply voltage setting 34 3.3 Threshold voltage setting 35 3.4 Settings for OR SDK 37 3.5 Settings for OR DVthDL for all cases 39 3.6 Settings for OR DVthDL with SLEEP 41 3.7 Settings for first proposed design by varying the KEEPER ratio 45 3.8 Settings for second proposed design by varying KEEPER ratio 51 4.1 Reference inverter for result of τ p and P 51&53 4.2 Results for τ p and P for reference inverter when scaling the V DD 54 4.3 (a) PSPICE simulation for reference inverter when scaling the threshold voltage 54 4.4 (b) PSPICE simulation for reference inverter when scaling the threshold voltage 54 4.5 Results of P, τ p and PDP for OR SDK when scaling the keeper ratio 56 xiii
4.6 Results of P, τ p and PDP for OR DVthDL for LH and LL cases when scaling keeper ratio 59 4.7 Results of P, τ p and PDP for OR DVthDL for LH and LL cases when scaling keeper ratio 60 4.8 Results of P, τ p and PDP for OR DVthDL with SLEEP when scaling keeper ratio for HH and HL case 62 4.9 Results of P, τ p and PDP for OR DVthDL with SLEEP when scaling keeper ratio for LH and LL case 63 4.10 Results of P, τ p and PDP for OR DVTVK-C 3 BBG and OR DVTVK-DBBG when scaling keeper ratio 66 4.11 Results of P, τ p and PDP for OR DVth LSDWDK with SLEEP with when scaling keeper ratio for HH and HL case 68 4.12 Results of P, τ p and PDP for OR DVth LSDWDK with SLEEP with when scaling keeper ratio for LH and LL case 69 4.13 Results of P, τ p and PDP for OR DVth LSDWDK with SLEEP and C 3 BBG when scaling keeper ratio for HH and HL case 72 4.14 Results of P, τ p and PDP for OR DVth LSDWDK with SLEEP and C 3 BBG when scaling keeper ratio for LH and LL case 73 5.1 Summaries of performance for first proposed design and second proposed design compared with OR SDK, OR DVthDL and OR DVthDL with SLEEP 95 xiv
LIST OF FIGURES Figure Page 2.1 Dynamic CMOS logic gate 5 2.2 Charge leakage 7 2.3 Keeper transistor in dynamic CMOS 8 2.4 Charge sharing 9 2.5 Charge redistribution 9 2.6 Capacitive coupling 10 2.7 Switching waveform for idealized inverter 12 2.8 A piecewise linear approximation of the VTC simplifies the derivation of V IL and V IH 14 2.9 Noise source of domino logic 15 2.10 Inverter 15 2.11 Standard dual threshold voltage domino logic gate 19 2.12 Dual threshold voltage domino logic gate 20 2.13 Dual threshold voltage domino logic for HH, LL, HL and LH types 23 2.14 A k-input domino OR gate with a variable threshold voltage keeper 24 2.15 The waveform during the operation 25 2.16 Body bias generator circuit 26 2.17 Cross-coupled capacitive body bias generator 28 xv
2.18 Dual Threshold Low Swing Domino Weakly Driven 28 Keeper (LSDWDK) 3.1 Flow chart for parameter analysis 31 3.2 The conversion of OR Gate Dynamic Circuit Into Reference Inverter 32 3.3 Flow chart of domino logic analysis 36 3.4 Standard Domino Logic schematic circuit 37 3.5 Schematic circuit of OR dual voltage threshold domino logic for HH case 39 3.6 Schematic Circuit of Dual Vth Domino Logic with SLEEP for LH case 41 3.7 OR domino logic with body bias generator, DBBG 42 3.8 OR DVTVK-C 3 BBG 43 3.9 Flow chart of DVTVK selection 43 3.10 Dual threshold voltage LSDWDK with sleep switch 45 3.11 Second Proposed Schematic Diagram 47 3.12 Domino logic design and analysis process flow 49 4.1 Propagation delay versus supply voltage for reference inverter 53 4.2 Propagation Delay versus Supply Voltage for reference inverter 53 4.3 Propagation delay versus threshold voltage for reference inverter 55 4.4 Power Dissipation versus threshold voltage for xvi
reference inverter 55 4.5 Propagation Delay versus KPR for OR SDK 57 4.6 Power Dissipation versus KPR for OR SDK 57 4.7 PDP versus KPR for OR SDK 57 4.8 Propagation Delay versus KPR for OR DVthDL 60 4.9 Power Dissipation versus KPR for OR DVthDL 60 4.10 PDP versus KPR for OR DVthDL 61 4.11 Power Dissipation versus KPR for OR DVthDL with SLEEP 63 4.12 Propagation Delay versus KPR for OR DVthDL with SLEEP 63 4.13 PDP versus KPR for OR DVthDL with SLEEP 64 4.14 Propagation Delay versus KPR (C 3 BBG and DBBG) 66 4.15 Power Dissipation versus KPR (C 3 BBG and DBBG) 66 4.16 PDP versus KPR (C 3 BBG and DBBG) 67 4.17 Propagation Delay versus KPR for OR DVth LSDWDK with SLEEP 69 4.18 Power Dissipation versus KPR for OR DVth LSDWDK with SLEEP 69 4.19 PDP versus KPR for OR DVth LSDWDK with SLEEP 70 4.20 Propagation Delay versus KPR for OR DVth LSDWDK with SLEEP + C 3 BBG 73 4.21 Power Dissipation versus KPR for OR DVth LSDWDK with SLEEP + C 3 BBG 73 xvii
4.22 PDP versus KPR for OR DVth LSDWDK with SLEEP + C 3 BBG 74 4.23 Propagation Delay versus KPR for HH case 76 4.24 Propagation Delay versus KPR for HL case 76 4.25 Propagation Delay versus KPR for LH case 76 4.26 Propagation Delay versus KPR for LL case 76 4.27 Power Dissipation versus KPR for HH case 78 4.28 Power Dissipation versus KPR for HL case 78 4.29 Power Dissipation versus KPR for LH case 78 4.30 Power Dissipation versus KPR for LL case 78 4.31 PDP versus KPR for HH case 80 4.32 PDP versus KPR for HL case 80 4.33 PDP versus KPR for LH case 80 4.34 PDP versus KPR for LL case 80 4.35 Propagation Delay versus KPR for HH case 81 4.36 Propagation Delay versus KPR for HL case 81 4.37 Propagation Delay versus KPR for LH case 82 4.38 Propagation Delay versus KPR for LL case 82 4.39 Power Dissipation versus KPR for HH case 83 4.40 Power Dissipation versus KPR for HL case 83 4.41 Power Dissipation versus KPR for LH case 83 4.42 Power Dissipation versus KPR for LL case 83 4.43 PDP versus KPR for HH case 84 4.44 PDP versus KPR for HL case 84 4.45 PDP versus KPR for LH case 85 xviii
4.46 PDP versus KPR for LL case 85 4.47 Propagation Delay versus KPR for HH case 86 4.48 Propagation Delay versus KPR for HL case 86 4.49 Propagation Delay versus KPR for LH case 86 4.50 Propagation Delay versus KPR for LL case 86 4.51 Power Dissipation versus KPR for HH case 88 4.52 Power Dissipation versus KPR for HL case 88 4.53 Power Dissipation versus KPR for LH case 88 4.54 Power Dissipation versus KPR for LL case 88 4.55 PDP versus KPR for HH case 90 4.56 PDP versus KPR for HL case 90 4.57 PDP versus KPR for LH case 90 4.58 PDP versus KPR for LL case 90 A1 Schematic circuit of OR dual voltage threshold domino logic for HL case 99 A2 Schematic circuit of OR dual voltage threshold domino logic for LH case 99 A3 Schematic circuit of OR dual voltage threshold domino logic for LL case 100 A4 Schematic circuit of OR dual voltage threshold domino logic with SLEEP for HH case 100 A5 Schematic circuit of OR dual voltage threshold domino logic with SLEEP for HL case 101 A6 Schematic circuit of OR dual voltage threshold domino xix
logic with SLEEP for LL case 101 A7 Schematic circuit of OR dual voltage threshold low swing domino logic with weakly driven keeper with SLEEP (OR DVth LSDWDK with SLEEP) for HH case 102 A8 Schematic circuit of OR dual voltage threshold low swing domino logic with weakly driven keeper with SLEEP (OR DVth LSDWDK with SLEEP) for HL 102 case A9 Schematic circuit of OR dual voltage threshold low swing domino logic with weakly driven keeper with SLEEP (OR DVth LSDWDK with SLEEP) for LH 103 case A10 Schematic circuit of OR dual voltage threshold low swing domino logic with weakly driven keeper with SLEEP (OR DVth LSDWDK with SLEEP) for LL case 103 A11 Schematic circuit of OR dual voltage threshold low swing domino logic with weakly driven keeper with SLEEP and C3BBG (OR DVth LSDWDK with SLEEP) for HH case 104 A12 Schematic circuit of OR dual voltage threshold low swing domino logic with weakly driven keeper with SLEEP and C3BBG (OR DVth LSDWDK with SLEEP) for HL case 104 A13 Schematic circuit of OR dual voltage threshold low xx
swing domino logic with weakly driven keeper with SLEEP and C3BBG (OR DVth LSDWDK with SLEEP) for LH case 105 A14 Schematic circuit of OR dual voltage threshold low swing domino logic with weakly driven keeper with SLEEP and C3BBG (OR DVth LSDWDK with SLEEP) for LH case 106 xxi