Data Sheet FEATURES Fixed (ADP3) and adjustable output (ADP33) options Bias voltage range ():.5 V to 5.5 V LDO input voltage range (VIN/VIN, VIN3):.8 V to 5.5 V Three ma low dropout voltage regulators (LDOs) 6-lead, 3 mm 3 mm LFCSP Initial accuracy: ±% Stable with μf ceramic output capacitors No noise bypass capacitor required 3 independent logic controlled enables Overcurrent and thermal protection Key specifications High PSRR 76 db PSRR up to khz 7 db PSRR at khz 6 db PSRR at khz 4 db PSRR at MHz Low output noise 9 μv rms typical output noise at VOUT =. V 55 μv rms typical output noise at VOUT =.8 V Excellent transient response Low dropout voltage: mv at ma load 85 μa typical ground current at no load, all LDOs enabled μs fast turn-on circuit Guaranteed ma output current per regulator 4 C to 5 C junction temperature APPLICATIONS Mobile phones Digital cameras and audio devices Portable and battery-powered equipment Portable medical devices Post dc-to-dc regulation GENERAL DESCRIPTION The ADP3/ADP33 ma triple output LDOs combine high PSRR, low noise, low quiescent current, and low dropout voltage to extend the battery life of portable devices and are ideally suited for wireless applications with demanding performance and board space requirements. The ADP3/ADP33 PSRR is greater than 6 db for frequencies as high as khz while operating with a low headroom voltage. The ADP3/ADP33 offer much lower noise performance than competing LDOs without the need for a noise bypass capacitor. Triple, ma, Low Noise, High PSRR Voltage Regulator ADP3/ADP33.5V TO 5.5V.8V TO 5.5V.8V TO 5.5V.5V TO 5.5V.8V TO 5.5V.8V TO 5.5V TYPICAL APPLICATION CIRCUITS µf VIN/VIN µf ON EN OFF VIN3 VIN/VIN VIN3 ON EN OFF µf ON EN3 OFF ADP3 LDO EN LD LDO EN LD LDO 3 EN LD3 GND Figure. Typical Application Circuit for ADP3 µf µf ON EN OFF ON EN OFF µf ON EN3 OFF ADP33 LDO EN LD LDO EN LD LDO 3 EN LD3 GND VOUT µf VOUT µf VOUT3 µf FB FB FB3 Figure. Typical Application Circuit for ADP33 988- VOUT µf VOUT µf VOUT3 µf The ADP3/ADP33 are available in a miniature 6-lead, 3 mm 3 mm LFCSP package and are stable with tiny μf ±3% ceramic output capacitors providing the smallest possible board area for a wide variety of portable power needs. The ADP3 is available in output voltage combinations ranging from.8 V to 3.3 V and offers overcurrent and thermal protection to prevent damage in adverse conditions. The APDP33 adjustable triple LDO can be configured for any output voltage between.5 V and 5 V with two resistors for each output. 988-53 Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 96, Norwood, MA 6-96, U.S.A. Tel: 78.39.47 www.analog.com Fax: 78.46.33 Analog Devices, Inc. All rights reserved.
ADP3/ADP33 TABLE OF CONTENTS Features... Applications... Typical Application Circuits... General Description... Revision History... Specifications... 3 Input and Output Capacitor, Recommended Specifications.. 4 Absolute Maximum Ratings... 5 Thermal Resistance... 5 ESD Caution... 5 Pin Configurations and Function Descriptions... 6 Typical Performance Characteristics... 8 REVISION HISTORY 9/ Rev. to Rev. A Added Figure, Renumbered Sequentially... Changes to Theory of Operation Section... 5 Added Figure 45, Renumbered Sequentially... 5 Changes to Ordering Guide... Data Sheet Theory of Operation... 5 Applications Information... 6 Capacitor Selection... 6 Undervoltage Lockout... 7 Enable Feature... 7 Current-Limit and Thermal Overload Protection... 8 Thermal Considerations... 8 Printed Circuit Board Layout Considerations... Outline Dimensions... Ordering Guide... 9/ Revision : Initial Version Rev. A Page of 4
Data Sheet ADP3/ADP33 SPECIFICATIONS VIN/VIN = VIN3 = (VOUT.5 V) or.8 V (whichever is greater), =.5 V, EN, EN, EN3 =, IOUT = IOUT = IOUT3 = ma, CIN = COUT = COUT = COUT3 = μf, and TA = 5 C, unless otherwise noted. Table. Parameter Symbol Conditions Min Typ Max Unit VOLTAGE RANGE Input Bias Voltage Range TJ = 4 C to 5 C.5 5.5 V Input LDO Voltage Range VIN/VIN/VIN3 TJ = 4 C to 5 C.8 5.5 V CURRENT Ground Current with All IGND IOUT = μa 85 μa Regulators On IOUT = μa, TJ = 4 C to 5 C 6 μa IOUT = ma μa IOUT = ma, TJ = 4 C to 5 C μa IOUT = ma 5 μa IOUT = ma, TJ = 4 C to 5 C 38 μa Bias Voltage Input Current IBIAS 66 μa TJ = 4 C to 5 C 4 μa Shutdown Current IGND-SD EN = EN = EN3 = GND. μa EN = EN = EN3 = GND, TJ = 4 C to 5 C.5 μa FEEDBACK INPUT CURRENT FBIN. μa VOLTAGE ACCURACY Output Voltage Accuracy VOUT % (ADP3) μa < IOUT < ma, VIN = (VOUT.5 V) to 5.5 V, % TJ = 4 C to 5 C Feedback Voltage Accuracy VFB.495.5.55 V (ADP33) μa < IOUT < ma, VIN = (VOUT.5 V) to 5.5 V,.49.5 V TJ = 4 C to 5 C LINE REGULATION VOUT/ VIN VIN = (VOUT.5 V) to 5.5 V. %/ V VIN = (VOUT.5 V) to 5.5 V, TJ = 4 C to 5 C.3.3 %/ V LOAD REGULATION VOUT/ IOUT IOUT = ma to ma. %/ma IOUT = ma to ma, TJ = 4 C to 5 C.5 %/ma DROPOUT VOLTAGE 3 VDROPOUT VOUT = 3.3 V mv IOUT = ma 6 mv IOUT = ma, TJ = 4 C to 5 C 9 mv IOUT = ma mv IOUT = ma, TJ = 4 C to 5 C 7 mv START-UP TIME 4 TSTART-UP VOUT = 3.3 V, all VOUT initially off, enable any LDO 4 μs VOUT =.8 V μs VOUT = 3.3 V, one VOUT initially on, enable second or 6 μs third LDO VOUT =.8 V μs CURRENT LIMIT THRESHOLD 5 ILIMIT 5 36 6 ma THERMAL SHUTDOWN Thermal Shutdown Threshold TSSD TJ rising 55 C Thermal Shutdown Hysteresis TSSD-HYS 5 C Rev. A Page 3 of 4
ADP3/ADP33 Data Sheet Parameter Symbol Conditions Min Typ Max Unit EN INPUT EN Input Logic High VIH.5 V 5.5 V. V EN Input Logic Low VIL.5 V 5.5 V.4 V EN Input Leakage Current VI-LEAKAGE EN = EN = EN3 = VIN or GND. μa EN = EN = EN3 = VIN or GND, μa TJ = 4 C to 5 C UNDERVOLTAGE LOCKOUT UVLO Input Bias Voltage () UVLORISE.45 V Rising Input Bias Voltage () UVLOFALL. V Falling Hysteresis UVLOHYS 8 mv OUTPUT NOISE OUTNOISE Hz to khz, VIN = 5 V, VOUT = 3.3 V 63 μv rms Hz to khz, VIN = 5 V, VOUT =.8 V 55 μv rms Hz to khz, VIN = 3.6 V, VOUT =.5 V 5 μv rms Hz to khz, VIN = 3.6 V, VOUT =. V 9 μv rms POWER SUPPLY REJECTION RATIO PSRR VIN =.8 V, VOUT =.8 V, IOUT = ma Hz 7 db khz 7 db khz 7 db khz 6 db MHz 4 db VIN = 3.8 V, VOUT =.8 V, IOUT = ma Hz 68 db khz 6 db khz 68 db khz 6 db MHz 4 db Accuracy when VOUTx is connected directly to FBx. When the VOUTx voltage is set by external feedback resistors, the absolute accuracy in adjust mode depends on the tolerances of the resistors used. Based on an end-point calculation using ma and ma loads. 3 The dropout voltage specification applies only to output voltages greater than.8 V. Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. 4 Start-up time is defined as the time between the rising edge of ENx to VOUTx being at 9% of its nominal value. 5 Current-limit threshold is defined as the current at which the output voltage drops to 9% of the specified typical value. For example, the current limit for a 3. V output voltage is defined as the current that causes the output voltage to drop to 9% of 3. V, that is,.7 V. INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS Table. Parameter Symbol Conditions Min Typ Max Unit MINIMUM INPUT AND OUTPUT CAPACITANCE CMIN TA = 4 C to 5 C.7 μf CAPACITOR ESR RESR TA = 4 C to 5 C. Ω The minimum input and output capacitance should be greater than.7 μf over the full range of operating conditions. The full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended; Y5V and Z5U capacitors are not recommended for use with LDOs. Rev. A Page 4 of 4
Data Sheet ABSOLUTE MAXIMUM RATINGS Table 3. Parameter VIN/VIN, VIN3, to GND VOUT, VOUT, FB, FB to GND VOUT3, FB3 to GND EN, EN, EN3 to GND Storage Temperature Range Operating Junction Temperature Range Soldering Conditions Rating.3 V to 6.5 V.3 V to VIN/VIN.3 V to VIN3.3 V to 6.5 V 65 C to 5 C 4 C to 5 C JEDEC J-STD- Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL DATA Absolute maximum ratings apply individually only, not in combination. The ADP3/ADP33 triple LDO can be damaged when the junction temperature limits are exceeded. Monitoring ambient temperature does not guarantee that the junction temperature (TJ) is within the specified temperature limits. In applications with high power dissipation and poor thermal resistance, the maximum ambient temperature may have to be derated. In applications with moderate power dissipation and low PCB thermal resistance, the maximum ambient temperature can exceed the maximum limit as long as the junction temperature is within specification limits. The junction temperature (TJ) of the device is dependent on the ambient temperature (TA), the power dissipation of the device (PD), and the junction-to-ambient thermal resistance of the package (θja). Maximum junction temperature (TJ) is calculated from the ambient temperature (TA) and power dissipation (PD) using the following formula: TJ = TA (PD θja) ADP3/ADP33 Junction-to-ambient thermal resistance (θja) of the package is based on modeling and calculation using a 4-layer board. The junction-to-ambient thermal resistance is highly dependent on the application and board layout. In applications where high maximum power dissipation exists, close attention to thermal board design is required. The value of θja may vary, depending on PCB material, layout, and environmental conditions. The specified values of θja are based on a 4-layer, 4 inch 3 inch circuit board. See JEDEC JESD 5-9 for detailed information on the board construction. For additional information, see the AN-67 Application Note, MicroCSP Wafer Level Chip Scale Package. ΨJB is the junction to board thermal characterization parameter with units of C/W. ΨJB of the package is based on modeling and calculation using a 4-layer board. The JESD5-, Guidelines for Reporting and Using Package Thermal Information, states that thermal characterization parameters are not the same as thermal resistances. ΨJB measures the component power flowing through multiple thermal paths rather than a single path as in thermal resistance, θjb. Therefore, ΨJB thermal paths include convection from the top of the package as well as radiation from the package, factors that make ΨJB more useful in real-world applications. Maximum junction temperature (TJ) is calculated from the board temperature (TB) and power dissipation (PD) using the following formula: TJ = TB (PD ΨJB) See JEDEC JESD5-8 and JESD5- for more detailed information about ΨJB. THERMAL RESISTANCE θja and ΨJB are specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 4. Package Type θja ΨJB Unit 6-Lead, 3 mm 3 mm LFCSP 49.5 5. C/W ESD CAUTION Rev. A Page 5 of 4
ADP3/ADP33 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 3 NC VOUT VOUT NC VOUT3 5 6 7 8 6 EN 5 EN3 4 NC EN GND VIN/VIN 3 ADP3 NC VIN3 NC 4 9 NC TOP VIEW (Not to Scale) NOTES. NC = NO CONNECT.. CONNECT EXPOSED PAD TO GROUND PLANE. Figure 3. ADP3 Pin Configuration Table 5. ADP3 Pin Function Descriptions Pin No. Mnemonic Description EN Enable Input for Regulator. Drive EN high to turn on Regulator ; drive it low to turn off Regulator. For automatic startup, connect EN to. Input Voltage Bias Supply. Bypass to GND with a μf or greater capacitor. 3 VIN/VIN Regulator Input Supply for Output Voltage and Output Voltage. Bypass VIN/VIN to GND with a μf or greater capacitor. 4 NC Not connected internally. 5 VOUT Regulated Output Voltage. Connect a μf or greater output capacitor between VOUT and GND. 6 VOUT Regulated Output Voltage. Connect a μf or greater output capacitor between VOUT and GND. 7 NC Not connected internally. 8 VOUT3 Regulated Output Voltage 3. Connect a μf or greater output capacitor between VOUT3 and GND. 9 NC Not connected internally. VIN3 Regulator Input Supply for Output Voltage 3. Bypass VIN3 to GND with a μf or greater capacitor. NC Not connected internally. GND Ground Pin. 3 NC Not connected internally. 4 NC Not connected internally. 5 EN3 Enable Input for Regulator 3. Drive EN3 high to turn on Regulator 3; drive it low to turn off Regulator 3. For automatic startup, connect EN3 to. 6 EN Enable Input for Regulator. Drive EN3 high to turn on Regulator ; drive it low to turn off Regulator. For automatic startup, connect EN to. EP Exposed pad for enhanced thermal performance. Connect to copper ground plane. 988- Rev. A Page 6 of 4
Data Sheet ADP3/ADP33 3 NC VOUT VOUT FB VOUT3 5 6 7 8 6 EN 5 EN3 4 NC EN GND VIN/VIN 3 ADP33 NC VIN3 FB 4 9 FB3 TOP VIEW (Not to Scale) NOTES. NC = NO CONNECT.. CONNECT EXPOSED PAD TO GROUND PLANE. Figure 4. ADP33 Pin Configuration Table 6. ADP33 Pin Function Descriptions Pin No. Mnemonic Description EN Enable Input for Regulator. Drive EN high to turn on Regulator ; drive it low to turn off Regulator. For automatic startup, connect EN to. Input Voltage Bias Supply. Bypass to GND with a μf or greater capacitor. 3 VIN/VIN Regulator Input Supply for Output Voltage and Output Voltage. Bypass VIN/VIN to GND with a μf or greater capacitor. 4 FB Connect the midpoint of the voltage divider from VOUT to GND to set VOUT. 5 VOUT Regulated Output Voltage. Connect a μf or greater output capacitor between VOUT and GND. 6 VOUT Regulated Output Voltage. Connect a μf or greater output capacitor between VOUT and GND. 7 FB Connect the midpoint of the voltage divider from VOUT to GND to set VOUT. 8 VOUT3 Regulated Output Voltage 3. Connect a μf or greater output capacitor between VOUT3 and GND. 9 FB3 Connect the midpoint of the voltage divider from VOUT3 to GND to set VOUT3. VIN3 Regulator Input Supply for Output Voltage 3. Bypass VIN3 to GND with a μf or greater capacitor. NC Not connected internally. GND Ground Pin. 3 NC Not connected internally. 4 NC Not connected internally. 5 EN3 Enable Input for Regulator 3. Drive EN3 high to turn on Regulator 3; drive it low to turn off Regulator 3. For automatic startup, connect EN3 to. 6 EN Enable Input for Regulator. Drive EN3 high to turn on Regulator ; drive it low to turn off Regulator. For automatic startup, connect EN to. EP Exposed pad for enhanced thermal performance. Connect to copper ground plane. 988-54 Rev. A Page 7 of 4
ADP3/ADP33 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS VIN/VIN = VIN3 = = 4 V, VOUT = 3.3 V, VOUT =.8 V, VOUT3 =.5 V, IOUT = ma, CIN = COUT = COUT = COUT3 = μf, VENX is the enable voltage, TA = 5 C, unless otherwise noted. 3.33 3.3 LOAD = ma LOAD = ma LOAD = ma LOAD = ma.8.85.8 LOAD = ma LOAD = ma LOAD = ma LOAD = ma 3.3.85 V OUT (V) 3.3 V OUT (V).8 3.9.795.79 3.8.785 3.7 4 5 5 85 5 T J ( C) 988-3.78 4 5 5 85 5 T J ( C) 988-6 Figure 5. Output Voltage vs. Junction Temperature Figure 8. Output Voltage vs. Junction Temperature 3.3.8 3.35.85 V OUT (V) 3.3 V OUT (V).8 3.35.85 3.3 I LOAD (ma) 988-4.8 I LOAD (ma) 988-7 Figure 6. Output Voltage vs. Load Current Figure 9. Output Voltage vs. Load Current 3.3 3.35 LOAD = ma LOAD = ma LOAD = ma LOAD = ma.8.85 LOAD = ma LOAD = ma LOAD = ma LOAD = ma V OUT (V) 3.3 V OUT (V).8 3.35.85 3.3 3.6 3.8 4. 4. 4.4 4.6 4.8 5. 5. 5.4 V IN (V) 988-5.8..5.9 3.3 3.7 4. 4.5 4.9 5.3 V IN (V) 988-8 Figure 7. Output Voltage vs. Input Voltage Figure. Output Voltage vs. Input Voltage Rev. A Page 8 of 4
Data Sheet ADP3/ADP33 V OUT (V).5.55.5.55.5.495.49.485.48.5 LOAD = ma LOAD = ma LOAD = ma LOAD = ma 4 5 5 85 5 T J ( C) Figure. Output Voltage vs. Junction Temperature 988-9 GROUND CURRENT (µa) 4 8 6 4 4 5 5 85 5 T J ( C) LOAD = ma LOAD = ma LOAD = ma LOAD = ma Figure 4. Ground Current vs. Junction Temperature, Single Output Loaded 988-.58 V OUT (V).56.54.5 GROUND CURRENT (µa) 8 6 4.5 V OUT (V).5.58.56.54.5 I LOAD (ma) Figure. Output Voltage vs. Load Current LOAD = ma LOAD = ma LOAD = ma LOAD = ma.5.8..6 3. 3.4 3.8 4. 4.6 5. 5.4 V IN (V) Figure 3. Output Voltage vs. Input Voltage 988-988- GROUND CURRENT (µa) I LOAD (ma) Figure 5. Ground Current vs. Load Current, Single Output Loaded 8 6 4 LOAD = ma LOAD = ma LOAD = ma LOAD = ma.8..6 3. 3.4 3.8 4. 4.6 5. 5.4 V IN (V) Figure 6. Ground Current vs. Input Voltage, Single Output Loaded 988-4 988-3 Rev. A Page 9 of 4
ADP3/ADP33 Data Sheet 35 3 GROUND CURRENT (µa) 5 5 5 4 5 5 85 5 T J ( C) LOAD = ma LOAD = ma LOAD = ma LOAD = ma 988-5 BIAS CURRENT (µa) 8 6 4 4 5 5 85 5 T J ( C) LOAD = ma LOAD = ma LOAD = ma LOAD = ma 988-8 Figure 7. Ground Current vs. Junction Temperature, All Outputs Loaded Equally Figure. Bias Current vs. Junction Temperature, Single Output Loaded 3 9 5 8 GROUND CURRENT (µa) 5 BIAS CURRENT (µa) 7 6 5 4 3 5 TOTAL LOAD CURRENT (ma) Figure 8. Ground Current vs. Load Current, All Outputs Loaded Equally 3 988-6 I LOAD (ma) Figure. Bias Current vs. Load Current, Single Output Loaded 76 988-9 GROUND CURRENT (µa) 5 5 LOAD = ma 5 LOAD = ma LOAD = ma LOAD = ma.7..5.9 3.3 3.7 4. 4.5 4.9 5.3 V IN (V) Figure 9. Ground Current vs. Input Voltage, All Outputs Loaded Equally 988-7 BIAS CURRENT (µa) 74 7 7 68 66 LOAD = ma LOAD = ma LOAD = ma LOAD = ma 64.5.9 3.3 3.7 4. 4.5 4.9 5.3 V IN (V) Figure. Bias Current vs. Input Voltage, Single Output Loaded 988- Rev. A Page of 4
Data Sheet ADP3/ADP33 SHUTDOWN CURRENT (µa).9.8.7.6.5.4.3.. 3.6 3.8 4. 4.4 4.8 5.5 5 5 5 5 75 5 TEMPERATURE ( C) 988- GROUND CURRENT (µa) 35 3 5 5 LOAD = ma 5 LOAD = ma LOAD = ma LOAD = ma 3. 3.5 3. 3.5 3.3 3.35 3.4 3.45 3.5 V IN (V) 988-4 Figure 3. Shutdown Current vs. Temperature at Various Input Voltages 9 8 Figure 6. Ground Current vs. Input Voltage (in Dropout), VOUT = 3.3 V 3 5 DROPOUT (mv) 7 6 5 4 3 LOAD (ma) Figure 4. Dropout Voltage vs. Load Current and Output Voltage, VOUT = 3.3 V 988- DROPOUT (mv) 5 5 LOAD (ma) Figure 7. Dropout Voltage vs. Load Current and Output Voltage, VOUT =.8 V 988-5 3.35 3.3 3.5 LOAD = ma LOAD = ma LOAD = ma LOAD = ma.85.8.75 3..7 V OUT (V) 3.5 V OUT (V).65 3..6 3.5 3..95 3. 3.5 3. 3.5 3.3 3.35 3.4 3.45 3.5 V IN (V) 988-3.55 LOAD = ma LOAD = ma.5 LOAD = ma LOAD = ma.45.7.8.9.. V IN (V) 988-6 Figure 5. Output Voltage vs. Input Voltage (in Dropout), VOUT = 3.3 V Figure 8. Output Voltage vs. Input Voltage (in Dropout), VOUT =.8 V Rev. A Page of 4
ADP3/ADP33 Data Sheet GROUND CURRENT (µa) 6 4 8 6 4 LOAD = ma LOAD = ma LOAD = ma LOAD = ma.7.8.9.. V IN (V) Figure 9. Ground Current vs. Input Voltage (in Dropout), VOUT =.8 V 988-7 PSRR (db) 3 4 5 6 7 8 9 V RIPPLE = 5mV V IN =.5V V OUT =.5V C OUT = µf k k k M M FREQUENCY (Hz) ma ma ma ma Figure 3. Power Supply Rejection Ratio vs. Frequency,.5 V 988-3 3 ma ma ma ma V RIPPLE = 5mV V IN =.8V V OUT =.8V C OUT = µf 3.8V/mA.8V/mA.8V/mA.V/mA.V/mA.V/mA V RIPPLE = 5mV V HEADROOM.8V PSRR. XTALK PSRR (db) 4 5 6 PSRR (db) 4 5 6 7 7 8 8 9 9 k k k M M FREQUENCY (Hz) Figure 3. Power Supply Rejection Ratio vs. Frequency,.8 V 988-8 k k k M M FREQUENCY (Hz) Figure 33. Power Supply Rejection Ratio vs. Frequency, Channel-to-Channel Crosstalk 988-3 PSRR (db) 3 4 5 6 7 8 9 ma ma ma ma V RIPPLE = 5mV V IN = 4.3V V OUT = 3.3V C OUT = µf NOISE SPECTRAL DENSITY (nv/ Hz). 3.3V.8V.5V k k k M M FREQUENCY (Hz) Figure 3. Power Supply Rejection Ratio vs. Frequency, 3.3 V 988-9. k k k FREQUENCY (Hz) Figure 34. Output Noise Spectral Density vs. Frequency, VIN = 5 V, ILOAD = ma 988-3 Rev. A Page of 4
Data Sheet ADP3/ADP33 7 6 3.3V.8V.5V I LOAD 5 NOISE (µv rms) 4 3 V OUT... LOAD CURRENT (ma) Figure 35. Output Noise vs. Load Current and Output Voltage, VIN = 5 V 988-33 CH ma Ω B W CH 5mV B W M4µs A CH 84mA T.4% Figure 38. Load Transient Response, ILOAD = ma to ma, COUT = μf, CH = ILOAD, CH = VOUT 988-36 I LOAD I LOAD3 V OUT V OUT3 V OUT 3 4 V OUT3 CH ma CH 5mV B Ω B W W M4µs A CH 44mA CH3 mv B W CH4 mv B W T 9.8% Figure 36. Load Transient Response, ILOAD = ma to ma, ILOAD = ILOAD3 = ma, CH = ILOAD, CH = VOUT, CH3 = VOUT, CH4 = VOUT3 988-34 CH ma Ω B W CH 5mV B W M4µs A CH 4mA T.% Figure 39. Load Transient Response, ILOAD3 = ma to ma, COUT3 = μf, CH = ILOAD3, CH = VOUT3 988-37 I LOAD V IN V OUT V OUT 3 V OUT 4 V OUT3 CH ma Ω B W CH 5mV B W M4µs A CH 4mA T.% Figure 37. Load Transient Response, ILOAD = ma to ma, COUT = μf, CH = ILOAD, CH = VOUT 988-35 CH V B W CH mv B W Mµs A CH 4.6V CH3 mv B W CH4 mv B W T 5% Figure 4. Line Transient Response, VIN = 4 V to 5 V, ILOAD = ILOAD = ILOAD3 = ma, CH = VIN, CH = VOUT, CH3 = VOUT, CH4 = VOUT3 988-38 Rev. A Page 3 of 4
ADP3/ADP33 Data Sheet V IN V ENx VOUT V OUT V OUT 3 V OUT V OUT3 4 V OUT3 CH V B W CH mv B W Mµs A CH 4.58V CH3 mv B W CH4 mv B W T % Figure 4. Line Transient Response, VIN = 4 V to 5 V, ILOAD = ILOAD = ILOAD3 = ma, CH = VIN, CH = VOUT, CH3 = VOUT, CH4 = VOUT3 988-39 CH V B CH 5mV B W W Mµs A CH 54mV CH3 5mV B W CH4 5mV B W T.% Figure 4. Turn-On Response, ILOAD = ILOAD = ILOAD3 = ma, CH = VENx (the Enable Voltage), CH = VOUT, CH3 = VOUT, CH4 = VOUT3 988-4 Rev. A Page 4 of 4
Data Sheet THEORY OF OPERATION The ADP3/ADP33 triple LDO are low quiescent current, low dropout linear regulators that operate from.8 V to 5.5 V on VIN/VIN and VIN3 and provide up to ma of current from each output. Drawing a low 5 μa quiescent current (typical) at full load makes the ADP3/ADP33 ideal for battery-operated portable equipment. Shutdown current consumption is typically na. Optimized for use with small μf ceramic capacitors, the ADP3/ADP33 provide excellent transient performance. Internally, the ADP3 consists of a reference, three error amplifiers, three feedback voltage dividers, and three PMOS pass transistors. Output current is delivered via the PMOS pass device, which is controlled by the error amplifier. The error amplifier compares the reference voltage with the feedback voltage from the output and amplifies the difference. If the feedback voltage is lower than the reference voltage, the gate of the PMOS device is pulled lower, allowing more current to flow and increasing the output voltage. If the feedback voltage is higher than the reference voltage, the gate of the PMOS device is pulled higher, allowing less current to flow and decreasing the output voltage. VIN/VIN VOUT ADP3/ADP33 The output voltage can be set using the following formulas: VOUT =.5 V( R/R) (FBIN)(R) VOUT =.5 V( R3/R4) (FBIN)(R3) VOUT3 =.5 V( R5/R6) (FBIN)(R5) The value of R, R3, R5 should be less than kω to minimize errors in the output voltage caused by the FBx pin input current. For example, when R and R each equal kω, the output voltage is. V. The output voltage error introduced by the FBx pin input current is mv or.%, assuming a typical FBx pin input current of na at 5 C. The ADP3 is available in multiple output voltage options ranging from.8 V to 3.3 V. The ADP3/ADP33 use the EN/EN and EN3 pins to enable and disable the VOUT/VOUT/VOUT3 pins under normal operating conditions. When the EN/EN and EN3 pins are high, VOUT/VOUT/VOUT3 turn on; when the EN/EN and EN3 pins are low, VOUT/VOUT/VOUT3 turn off. For automatic startup, the EN/EN and EN3 pins can be tied to. EN EN EN3 VIN3 GND INTERNAL BIAS VOLTAGES/CURRENTS, UVLO AND THERMAL PROTECT SHUTDOWN VOUT SHUTDOWN VOUT SHUTDOWN VOUT3 OVERCURRENT OVERCURRENT OVERCURRENT.5V REF.5V REF.5V REF Figure 43. ADP3 Internal Block Diagram VOUT VOUT3 The ADP33 differs from the ADP3 except in that the output voltage dividers are internally disconnected and the feedback inputs of the error amplifiers are brought out for each output. VIN/VIN 988-4 VOUT.5V TO 5.5V.8V TO 5.5V.8V TO 5.5V µf VIN/VIN µf ON EN OFF ON EN OFF VIN3 µf ON EN3 OFF ADP33 LDO EN LD LDO EN LD LDO 3 EN LD3 GND FB FB FB3 Figure 45. ADP33 Application Circuit Diagram R R R3 R4 R5 R6 VOUT µf VOUT µf VOUT3 µf 988-45 INTERNAL BIAS VOLTAGES/CURRENTS, UVLO AND THERMAL PROTECT OVERCURRENT.5V REF FB EN SHUTDOWN VOUT VOUT EN EN3 SHUTDOWN VOUT SHUTDOWN VOUT3 OVERCURRENT.5V REF FB VIN3 VOUT3 GND OVERCURRENT.5V REF Figure 44. ADP33 Internal Block Diagram FB3 988-55 Rev. A Page 5 of 4
ADP3/ADP33 APPLICATIONS INFORMATION CAPACITOR SELECTION Output Capacitor The ADP3/ADP33 are designed for operation with small, space-saving ceramic capacitors, but the parts function with most commonly used capacitors as long as care is taken with the effective series resistance (ESR) value. The ESR of the output capacitor affects the stability of the LDO control loop. A minimum of.7 μf capacitance with an ESR of Ω or less is recommended to ensure the stability of the ADP3/ADP33. Transient response to changes in load current is also affected by output capacitance. Using a larger value of output capacitance improves the transient response of the ADP3/ADP33 to large changes in the load current. Figure 46 shows the transient response for an output capacitance value of μf. 3 4 CH ma Ω CH3 mv B W B W CH 5mV CH4 mv I LOAD V OUT V OUT V OUT3 B W B W M4µs A CH 44mA T 9.8% Figure 46. Output Transient Response, ILOAD = ma to ma, ILOAD = ma, ILOAD3 = ma, CH = ILOAD, CH = VOUT, CH3 = VOUT, CH4 = VOUT3 988-4 Data Sheet Input Bypass Capacitor Connecting a μf capacitor from VIN/VIN, VIN3, and to GND reduces the circuit sensitivity to the PCB layout, especially when long input traces or high source impedance is encountered. If an output capacitance greater than μf is required, the input capacitor should be increased to match it. Input and Output Capacitor Properties Any good quality ceramic capacitor can be used with the ADP3/ ADP33, as long as the capacitor meets the minimum capacitance and maximum ESR requirements. Ceramic capacitors are manufactured with a variety of dielectrics, each with a different behavior over temperature and applied voltage. Capacitors must have an adequate dielectric to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. X5R or X7R dielectrics with a voltage rating of 6.3 V or V are recommended. Y5V and Z5U dielectrics are not recommended due to their poor temperature and dc bias characteristics. Figure 47 depicts the capacitance vs. voltage bias characteristic of a 4 μf, V, X5R capacitor. The voltage stability of a capacitor is strongly influenced by the capacitor size and voltage rating. In general, a capacitor in a larger package or with a higher voltage rating exhibits better stability. The temperature variation of the X5R dielectric is about ±5% over the 4 C to 85 C temperature range and is not a function of the package or voltage rating. CAPACITANCE (µf)...8.6.4. 4 6 8 VOLTAGE (V) Figure 47. Capacitance vs. Voltage Bias Characteristic 988-43 Rev. A Page 6 of 4
Data Sheet Use Equation to determine the worst-case capacitance, accounting for capacitor variation over temperature, component tolerance, and voltage. CEFF = CBIAS ( TEMPCO) ( TOL) () where: CBIAS is the effective capacitance at the operating voltage. TEMPCO is the worst-case capacitor temperature coefficient. TOL is the worst-case component tolerance. In this example, TEMPCO over 4 C to 85 C is assumed to be 5% for an X5R dielectric. TOL is assumed to be %, and CBIAS is.94 μf at.8 V (from the graph in Figure 47). Substituting these values into Equation yields CEFF =.94 μf (.5) (.) =.79 μf Therefore, the capacitor chosen in this example meets the minimum capacitance requirement of the LDO over temperature and tolerance at the chosen output voltage. To guarantee the performance of the ADP3/ADP33 triple LDO, it is imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capacitors be evaluated for each application. UNDERVOLTAGE LOCKOUT The ADP3/ADP33 have an internal undervoltage lockout circuit that disables all inputs and the output when the input voltage bias,, is less than approximately. V. This ensures that the inputs of the ADP3/ADP33 and the output behave in a predictable manner during power-up. ENABLE FEATURE The ADP3/ADP33 use the ENx pins to enable and disable the VOUTx pins under normal operating conditions. Figure 48 shows that, when a rising voltage on ENx crosses the active threshold, VOUTx turns on. When a falling voltage on ENx crosses the inactive threshold, VOUTx turns off..4 ADP3/ADP33 As shown in Figure 48, the ENx pin has built-in hysteresis. This prevents on/off oscillations that can occur due to noise on the ENx pin as it passes through the threshold points. The active/inactive thresholds of the ENx pin are derived from the voltage. Therefore, these thresholds vary with changing input voltage. Figure 49 shows typical ENx active/ inactive thresholds when the input voltage varies from.5 V to 5.5 V (note that VENx is the enable voltage). ENABLE THRESHOLDS..95.9.85.8.75.7.65.6.55 V ENx RISE V ENx FALL.5.5 3. 3.5 4. 4.5 5. 5.5 INPUT VOLTAGE (V) Figure 49. Typical ENx Pins Thresholds vs. Input Voltage The ADP3/ADP33 use an internal soft start to limit the inrush current when the output is enabled. The start-up time for the.8 V option is approximately μs from the time the ENx active threshold is crossed to when the output reaches 9% of its final value. The start-up time is somewhat dependent on the output voltage setting and increases slightly as the output voltage increases. V ENx V OUT V OUT 988-45. V OUT @ 4.5V IN V OUT3. V OUT (V).8.6.4. CH V B CH 5mV B W W Mµs A CH 54mV CH3 5mV B W CH4 5mV B W T.% Figure 5. Typical Start-Up Time,ILOAD = ILOAD = ILOAD3 = ma, CH = VENx (the Enable Voltage), CH = VOUT, CH3 = VOUT, CH4 = VOUT3 988-46.4.5.6.7.8.9... ENABLE VOLTAGE (V) Figure 48. Typical ENx Pin Operation 988-44 Rev. A Page 7 of 4
ADP3/ADP33 CURRENT-LIMIT AND THERMAL OVERLOAD PROTECTION The ADP3/ADP33 are protected against damage due to excessive power dissipation by current and thermal overload protection circuits. The ADP3/ADP33 are designed to current limit when the output load reaches 3 ma (typical). When the output load exceeds 3 ma, the output voltage is reduced to maintain a constant current limit. Thermal overload protection is built in, which limits the junction temperature to a maximum of 55 C (typical). Under extreme conditions (that is, high ambient temperature and power dissipation) when the junction temperature starts to rise above 55 C, the output is turned off, reducing the output current to zero. When the junction temperature drops below 4 C, the output is turned on again and the output current is restored to its nominal value. Consider the case where a hard short from VOUTx to GND occurs. At first, the ADP3/ADP33 limits current so that only 3 ma is conducted into the short. If self-heating of the junction is great enough to cause its temperature to rise above 55 C, thermal shutdown activates, turning off the output and reducing the output current to zero. As the junction temperature cools and drops below 4 C, the output turns on and conducts 3 ma into the short, again causing the junction temperature to rise above 55 C. This thermal oscillation between 4 C and 55 C causes a current oscillation between ma and 3 ma that continues as long as the short remains at the output. Current and thermal limit protections are intended to protect the device against accidental overload conditions. For reliable operation, device power dissipation must be externally limited so that junction temperatures do not exceed 5 C. THERMAL CONSIDERATIONS In most applications, the ADP3/ADP33 do not dissipate a lot of heat due to high efficiency. However, in applications with a high ambient temperature and high supply voltage to output voltage differential, the heat dissipated in the package is large enough that it can cause the junction temperature of the die to exceed the maximum junction temperature of 5 C. When the junction temperature exceeds 55 C, the converter enters thermal shutdown. It recovers only after the junction temperature decreases below 4 C to prevent any permanent damage. Therefore, thermal analysis for the chosen application is very important to guarantee reliable performance over all conditions. The junction temperature of the die is the sum of the ambient temperature of the environment and the temperature rise of the package due to the power dissipation, as shown in Equation. Data Sheet To guarantee reliable operation, the junction temperature of the ADP3/ADP33 must not exceed 5 C. To ensure that the junction temperature stays below this maximum value, the user must be aware of the parameters that contribute to junction temperature changes. These parameters include ambient temperature, power dissipation in the power device, and thermal resistances between the junction and ambient air (θja). The θja number is dependent on the package assembly compounds used and the amount of copper to which the GND pins of the package are soldered on the PCB. Table 7 shows typical θja values for the ADP3/ADP33 for various PCB copper sizes. Table 7. Typical θja Values Copper Size (mm ) ADP3/ADP33 Triple LDO ( C/W) JEDEC 49.5 83.7 5 68.5 64.7 Device soldered to JEDEC standard board. The junction temperature of the ADP3/ADP33 can be calculated from the following equation: TJ = TA (PD θja) () where: TA is the ambient temperature. PD is the power dissipation in the die, given by PD = Σ[(VIN VOUT) ILOAD] Σ(VIN IGND) (3) where: ILOAD is the load current. IGND is the ground current. VIN and VOUT are input and output voltages, respectively. Power dissipation due to ground current is quite small and can be ignored. Therefore, the junction temperature equation simplifies to TJ = TA {Σ[(VIN VOUT) ILOAD] θja} (4) As shown in Equation 4, for a given ambient temperature, input-to-output voltage differential, and continuous load current, there exists a minimum copper size requirement for the PCB to ensure that the junction temperature does not rise above 5 C. Figure 5 to Figure 54 show junction temperature calculations for different ambient temperatures, total power dissipation, and areas of PCB copper. In cases where the board temperature is known, the thermal characterization parameter, ΨJB, can be used to estimate the junction temperature rise. TJ is calculated from TB and PD using the formula TJ = TB (PD ΨJB) (5) The typical ΨJB value for the 6-lead, 3 mm 3 mm LFCSP is 5. C/W. Rev. A Page 8 of 4
Data Sheet ADP3/ADP33 4 4 JUNCTION TEMPERATURE, T J ( C) 8 6 4 mm 5mm mm 5mm JEDEC T J MAX..4.6.8.. TOTAL POWER DISSIPATION (W) Figure 5. Junction Temperature vs. Total Power Dissipation, TA = 5 C 988-47 JUNCTION TEMPERATURE, T J ( C) 8 6 4 mm 5mm mm 5mm JEDEC T J MAX..4.6.8.. TOTAL POWER DISSIPATION (W) Figure 53. Junction Temperature vs. Total Power Dissipation, TA = 85 C 988-49 4 4 JUNCTION TEMPERATURE, T J ( C) 8 6 4 mm 5mm mm 5mm JEDEC T J MAX..4.6.8.. TOTAL POWER DISSIPATION (W) 988-48 JUNCTION TEMPERATURE, T J ( C) 8 6 4 T B = 5 C T B = 5 C T B = 85 C T J MAX..4.6.8...4.6.8 TOTAL POWER DISSIPATION (W) 988-5 Figure 5. Junction Temperature vs. Total Power Dissipation, TA = 5 C Figure 54. Junction Temperature vs. Total Power Dissipation and Board Temperature Rev. A Page 9 of 4
ADP3/ADP33 Data Sheet PRINTED CIRCUIT BOARD LAYOUT CONSIDERATIONS Heat dissipation from the package can be improved by increasing the amount of copper attached to the pins of the ADP3/ADP33. However, as can be seen from Table 7, a point of diminishing returns is eventually reached, beyond which an increase in the copper size does not yield significant heat dissipation benefits. Place the input capacitor as close as possible to the VINx and GND pins. Place the output capacitors as close as possible to the VOUTx and GND pins. Use 4 or 63 size capacitors and resistors to achieve the smallest possible footprint solution on boards where area is limited. 988-5 Figure 55. Example of PCB Layout, Top Side 988-5 Figure 56. Example of PCB Layout, Bottom Side Rev. A Page of 4
Data Sheet ADP3/ADP33 OUTLINE DIMENSIONS PIN INDICATOR 3. 3. SQ.9.5 BSC.3.5. 3 6 PIN INDICATOR EXPOSED PAD.65.5 SQ.45.8.75.7 SEATING PLANE TOP VIEW.5.4.3.5 MAX. NOM COPLANARITY.8. REF 9 4 8 5 BOTTOM VIEW. MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-9. Figure 57. 6-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 3 mm 3 mm Body, Very, Very Thin Quad (CP-6-7) Dimensions shown in millimeters ORDERING GUIDE Temperature Output Voltage (V) Model Range VOUT VOUT VOUT3 Package Description 969-A Package Option ADP3ACPZ-5-R7 4 C to 5 C 3.3 V.8 V.8 V 6-Lead LFCSP_WQ CP-6-7 LGU ADP3ACPZ-35-R7 4 C to 5 C 3.3 V.5 V.8 V 6-Lead LFCSP_WQ CP-6-7 LGT ADP3ACPZ-45-R7 4 C to 5 C 3.3 V.5 V. V 6-Lead LFCSP_WQ CP-6-7 LJC ADP3ACPZ-55-R7 4 C to 5 C 3.3 V.8 V.5 V 6-Lead LFCSP_WQ CP-6-7 LGS ADP3ACPZ-65-R7 4 C to 5 C 3.3 V.8 V.V 6-Lead LFCSP_WQ CP-6-7 LLX ADP3ACPZ-75-R7 4 C to 5 C.8 V.8 V. V 6-Lead LFCSP_WQ CP-6-7 LGR ADP3ACPZ-89-R7 4 C to 5 C.5 V.8 V. V 6-Lead LFCSP_WQ CP-6-7 LJD ADP33ACPZ-R7 4 C to 5 C Adjustable Adjustable Adjustable 6-Lead LFCSP_WQ CP-6-7 LGQ ADP3CP-EVALZ Evaluation board ADP33CP-EVALZ Evaluation board ADP3CPZ-REDYKIT Evaluation board kit Branding Z = RoHS Compliant Part. For additional voltage options, contact a local sales or distribution representative. Rev. A Page of 4
ADP3/ADP33 Data Sheet NOTES Rev. A Page of 4
Data Sheet ADP3/ADP33 NOTES Rev. A Page 3 of 4
ADP3/ADP33 Data Sheet NOTES Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D988--9/(A) Rev. A Page 4 of 4