CS and CE amplifiers with loads:

CS and CE amplifiers with loads: The Common-Source Circuit The most basic IC MOS amplifier is shown in fig.(1). The source of MOS transistor is grounded, also the drain resistor RD replaced by a constant-current source I. The current source load can be implemented using a PMOS transistor and is therefore called an active load, and the CS amplifier of Fig. 1(a) is said to be active-loaded. Before we consider the small-signal operation of the active-loaded CS amplifier, it is important to know that Q1 is biased to have ID = I. But the DC voltages at the drain and at the gate are developed by a circuit which is a part of a larger circuit in which negative feedback is utilized to fix the values of VDS and VGS. We shall assume that these circuits are in such a way that they bias the MOSFET in operate in the saturation region. Fig.1 (a) Active-loaded common-source amplifier, (b) Small-signal analysis of the amplifier in (a), performed both directly on the circuit diagram and using the small signal model explicitly. Since we analyse the circuit to obtain input impedance, voltage gain, current gain & output impedance in the view of small-signal, the biasing arrangement in the circuit is not shown. Small-signal analysis of the current-source-loaded CS amplifier is straightforward and is illustrated in Fig. 1(b). Here, along with the equivalent circuit model, we show the transistor with its r0 extracted and displayed separately and with the analysis performed directly on the circuit. From Fig. 1(b) we see that for this CS amplifier, Rin =, AVO = -gmro (since vi = vgs and vo = - gm rovgs) and R0 =r0. We note that Avo is the maximum voltage gain available from a common-source amplifier, namely the intrinsic gain of the MOSFET, A0 = gmro Common-Source Amplifier implemented using CMOS: A CMOS circuit implementation of the common-source amplifier is shown in Fig. 2(a) This circuit is based on that shown in Fig. 1(a) with the load current-source I implemented using

transistor Q2. This is the output transistor of the current mirror formed by Q2 and Q3 and fed with the bias current IREF. We shall assume that Q2 and Q3 are matched; therefore the Fig.active-loadQ2 ; (c) graphical construction to determine the transfer characteristic: and (d) transfer characteristic. i-v characteristic of the load device will be as shown in Fig. 2(b). This is simply the id-vsd characteristic curve of the p-channel transistor Q2 for a constant source-gate voltage VSG. The value of VSG is set by passing the reference bias current IREF through Q3. Observe that, Q2 behaves as a current source when it operates in saturation, which in turn is obtained when v = vsd exceeds (VSG - Vtp ), which is the magnitude of the overdrive voltage at which Q2 and Q3 are operating. Q2 exhibits a finite incremental resistance ro2, when it is in saturation and is given by, Where VA2 is the Early voltage of Q2. In other words, the current-source load is not ideal but has a finite output resistance equal to the transistor r0. The circuit s transfer characteristic, vo versus vi, needs to be observed before analyzing the circuit to calculate voltage gain. This can be obtained using the graphical construction shown in Fig. 2 (c). Here we have sketched the id-vds characteristics of the amplifying transistor Q1 and superimposed the load curve on them. The latter is simply the i-v curve in Fig. 2(b) "flipped around" and shifted VDD volts along the horizontal axis. Now, since vgs1=vi, each of the id-vds curves corresponds to a particular value of vi. The intersection of each particular curve with the load curve gives the corresponding value of VDS1, which is equal to v0. Thus, in this way, we can obtain the v0-vi characteristic, point by point. The resulting transfer characteristic is sketched in Fig. 2(d). As indicated, it has four distinct segments, labeled I, II, III, and IV, each of which is obtained for one of the four combinations of the modes of operation of Q1 and Q2, which are also indicated in the diagram. Note also that we have labeled two important break points on the transfer characteristic (A and B) in correspondence with the intersection points (A and B) in Fig.

2 (c). For amplifier operation segment III is the one of interest. Observe that in region III the transfer curve is almost linear and is very steep, indicating large voltage gain. In region III both the amplifying transistor Q1 and the load transistor Q2 are operating in saturation. The end points of region III are A and B: At A, defined by v0 = VDD - V0V2, Q2 enters the triode region, and at B, defined by v0 = vi Vtn, Q1 enters the triode region. When the amplifier is biased at a point in region III, the small-signal voltage gain can be determined by replacing Q1 with its small-signal model and Q2 with its output resistances ro2. The output resistance of Q2 constitutes the load resistance of Q1. The voltage gain Av can be found from Eq. below indicating that, as expected, Av will be lower in magnitude than the intrinsic gain of Q1, gm1ro1. For the case ro2 = rol, Av will be gm1rol/2. The CMOS common-source amplifier can be designed to provide voltage gains ranging from 15 to 100. It offers a very high input resistance; however, its output resistance is also high. Two final comments need to be made before leaving the common-source amplifier: 1. The circuit is not affected by the body effect since the source terminals of both Q1 and Q2 are at signal ground. 2. The circuit is usually part of a larger amplifier circuit and negative feedback is utilized to ensure that the circuit in fact operates in region III of the amplifier transfer characteristic. EXAMPLE Consider the CMOS common-source amplifier in Fig. 2 (a) for the case VDD = 3 V, Vtn = Vtp = 0.6 V, μnc0x = 200 μa / V2, and μpc0x = 65 μa / V2. For all transistors, L = 0.4 μm and W=4 μm. Also, VAn = 20 V, VAp = 10 V, and IREF = 100 μa. Find the small signal voltage gain. Also, find the coordinates of the extremities of the amplifier region of the transfer characteristic that is, points A and B in the transfer characteristic. Solution

The width of the amplifier region is therefore Δvi = VIB -VIA = 0.05 V and the corresponding output range is ΔV0=VOB - VOA = -2.14 V Thus the "large-signal" voltage gain is which is very close to the small-signal value of -42, indicating that segment III of the transfer characteristic is quite linear.

FIGURE 3(a) Active-loaded common-emitter amplifier, (b) Small-signal analysis of the amplifier in (a), performed both directly on the circuit and using the hybrid-π model explicitly. The active-loaded common-emitter amplifier, in Fig. 3(a), is similar to the active-loaded common-source circuit studied above. Here also, the bias-stabilizing circuit is not shown. Smallsignal analysis is similar to that for the MOS case and is shown in Fig. 3(b). The results are Ri = rπ Avo = -gmro Ro = ro which except for the rather low input resistance rπ are similar to the MOSFET case. Recall, however, from the comparison, that the intrinsic gain gmr0 of the BJT is much higher than that for the MOSFET. This advantage, however, is counterbalanced by the practically infinite input resistance of the common-source amplifier.