Wireless charger controller Features Single channel differential gate drivers QFN 40 1x differential-ended input operational amplifiers 1x single-ended input operational amplifiers 1x comparators with hysteresis and deglitch Serial Bus control Coil voltage sense for protection Bridge current sense for protection Over voltage and over current protection Description The CV90312T is a wireless battery charger controller working at a single power supply. The power management block provides regulated supply for both internal circuit. Through the serial bus, CV90312T communicates with the external MCU to obtain information to drive the battery charger. On-chip boot-strapped power transistor drivers will drive external power transistors directly. Built-in sensing circuit will shut the transistors off when over current condition or over voltage condition is detected. CV90312T can operate at a broad temperature range from 0 C to +70 C. 7/5/2013 Rev 1.0 1/19
1 Device block diagram LDO5V 2.5V VCM VCM_BUF PWRPI2C SDA BSTREFR SCL GATEHIR RBIAS ROSC CLK80K SERIAL INTERFACE AND LOGIC FREQUENCY AND PHASE SHIFT DEADZONE CONTROL AND DRIVER LOGIC VODR GATELOR BSTREFL GATEHIL VODL GATELOL ISENSE 335mV VSENSE 2.5V VFILTER demodulation + 2.5V + VDEMODSO VDEMODDIP VDEMODDIN VDEMODDO VDEMODSIN 7/5/2013 Rev 1.0 2/19
2 Pin description 2.1 Pin out chip. A 40 pin package is required to accommodate all the necessary I/O and power supplies of the 7/5/2013 Rev 1.0 3/19
2.2 Pin list Pin No. Name Description 13, 17, 19, 24, 33 Vcc power supply, 5V 14, 18, 25, 34, 35 GND Ground pin 1 pingin Inverting input of ping amplifier 2 pingip Non-inverting input of ping amplifier 3 vfiltero Demodulation filter output 4 Vdemodso demodulation single-ended opamp output 5 Vdemodsin demodulation single-ended opamp input 6 Vdemoddo demodulation differential-ended opamp output 7 Vdemoddin demodulation differential-ended opamp negative input 8 Vdemoddip demodulation differential-ended opamp positive input 9 idemodsin demodulation single-ended opamp input 10 idemoddo demodulation differential-ended opamp output 11 idemoddin demodulation differential-ended opamp negative input 12 idemoddip demodulation differential-ended opamp positive input 15 Vsense Over-voltage sense input 16 Isense Over-current sense input 20 Bstrefr right side bootstrap power supply 21 Gatehir right high-side gate drive 22 Vodr right side output 23 Gatelor right low-side gate drive 26 Gatelol Left low-side gate drive 27 Vodl Left side output 28 Gatehil Left high-side gate drive 29 Bstrefl Left side bootstrap power supply 30 Rbias Biasing resistor; Default=270kohm 31 Rosc Control resistor for oscillator frequency; Default=270kohm 32 Vcm_buf Buffered common voltage output 36 Vcc-iic Serial Bus power supply, 5V 37 SDA Serial Bus data input 38 SCL Serial Bus clock input 39 Clk80k Clock for digital debouncing circuit 40 ping Ping op-amp output 7/5/2013 Rev 1.0 4/19
3 Electrical specifications 3.1 Absolute maximum ratings Table 3. Absolute maximum ratings Symbol Parameter Value Unit VDD DC supply voltage 6.5 V T op Operating temperature 0 to 70 C T j Junction temperature 30 to 150 C T stg Storage temperature 65 to 150 C HBM ESD Susceptibility 2000 V CDM ESD Susceptibility 500 V 3.2 Thermal data Table 4. Thermal data Symbol Parameter Min Typ Max Unit θja Junction to ambient thermal resistance, still air; soldered to PCB of FR-4 30 C/W material. Heat sinking pad size on the 4 layer PCB is 3.8mm x 3.8mm with 9 thermal vias on 1.2mm pitch. 3.3 Electrical specifications Unless otherwise stated, the results in Table 5 below are given for the conditions: VLDO5V = 5 V, over the operating temperature of 0 C to +70 C. Table 5. Electrical specifications Symbol Parameter Condition Min Typ Max Unit POWER SUPPLY V Ldo5v Supply voltage for pin V Ldo5v 4.5 5 5.5 V I Ldo5v Total quiescent current No load TBD ma I Shutdown Shut down current Reg 01 =FF TBD µa 2.5V REGULATOR V vcm 2.5V regulator output No load 0.45V Ldo5v 0.5V Ldo5v 0.55V Ldo5v V Io vcm Output current 2kohm between V Ldo5v and V vcm 1 ma SERIAL INTERFACE (SDA, SCL I/O Characteristics; Pull-up resistors on SDA and SCL is 4.7kohm) V Pwrpi2c Serial Interface bus power supply 4.5 5 5.5 V V IH High input level 0.7V Pwrpi2c V V IL Low input level 0.3V Pwrpi2c V 7/5/2013 Rev 1.0 5/19
Symbol Parameter Condition Min Typ Max Unit V OL Low output level Sink current=3ma 0.4 V f clk Clock frequency at SCL 300 KHz I pwrpi2c DEMODULATOR V CM Supply current of serial interface block Common mode input voltage range 10KΩ Pull up at SDA, 200KHz clock 1.5 V Ldo5v - 1.5 600 µa V OS Input offset voltage 25 mv R i Input impedance 10 MΩ V Oswing Output voltage swing of op-amps Io Output current of op-amps Gain=10; R load =1.5kΩ with reference to V cm PSRR GBW Power supply rejection ratio of Operational Amplifier Gain Bandwidth Product of Operational Amplifier Gain=10; No load 0.25 V Ldo5v - 0.25-1.5 1.5 ma V Ldo5v =1V; No load 50 61 db V V 5 MHz Gain Open loop gain No load 60 66 db V comp V Comphi Comparator input voltage range Comparator high input voltage 0 V Ldo5v V Reg 0B =00 0.505V Ldo5v V V Complo Comparator low input voltage Reg 0B =00 0.495V Ldo5v V T Pulse CHARGER Minimum comparator output pulse width f g Gate driver frequency Rosc=270KΩ, Reg Freq =000 Reg Freq =1FF Reg Freq =27F 208 T jitterh T jitterl Period jitter of high-side gate driver Period jitter of low-side gate driver Reg Freq =000, with full bridge network without load Reg Freq =000, with full bridge network without load I ohmax Peak source current of gate driver V Ldo5v -V gatel =1.5V; V btref -V gateh =1.5V I olmax Peak sink current of gate driver V gatel =1.5V; V gateh -V vod =1.5V t deadzone Dead zone timing Reg 0A =00 Reg 0A =01 Reg 0A =10 Reg 0A =11 D% deltahi Duty cycle mismatch between left to right high-side gate driver Reg Freq =000, with full bridge network without load 10 clk TBD TBD 72 228 96 khz 5 ns 5 ns 200 150 100 50 A A ns 0.8 % D% deltalo Duty cycle mismatch between left Reg Freq =000, with full 0.8 % 7/5/2013 Rev 1.0 6/19
to right low-side gate driver bridge network without load Phase 080 Phase shift Reg Phase =080, Reg P =1 50 Deg Phase 1FF Phase shift Reg Phase =1FF, Reg P =1 198 Deg Phase 27F Phase shift Reg Phase =27F, Reg P =1 180 Deg Symbol Parameter Condition Min Typ Max Unit Minimum ON time PROTECTION Duty cycle mode, Gate driver must turn on more than 3.6deg, or 50nsec, whichever larger Reg phase >=010, Reg P =0 3.6 Deg V I Input voltage range 0 V Ldo5v V V Isense V Isense voltage to trigger shut down of bridge 0.07V Ldo5v V V Vsense V Vsense shut down voltage 0.52 Ldo5v V 7/5/2013 Rev 1.0 7/19
4 Serial Interface and Register table The CV90312T is controlled through a serial interface that consists of a serial data line (SDA) and a serial clock (SCL). The clock line is uni-directional. The data line is bi-directional (open drain). The CV90312T and the MCU can communicate at a clock rate up to 300kHz. Serial interface timing diagram Data on the SDA line must be stable during HIGH period of SCL. Each transmission sequence is framed by a START condition and a STOP condition. START and STOP condition of serial interface Each data word, device address and data, transmitted over the bus is 8 bits long and is always followed by an acknowledge pulse. The CV90312T device address is 0111100 The START signal, the transition of SDA from HIGH to LOW while SCL is HIGH, is generated, alerting all devices on bus that a device address is being written to the bus. The 7-bit device address, 0111100, is written to the bus, the most significant bit (MSB) first, followed by the R/W bit. R/W bit=0 indicates the master is writing to the slave device, R/W bit=1 indicates the master wants to read date from the slave device. Device address B7 B6 B5 B4 B3 B2 B1 B0 (R/W) 0 1 1 1 1 0 0 0 The data is latched in on the rising edge of the clock. Each address bit must be stable while SCL is HIGH. After 7/5/2013 Rev 1.0 8/19
the last address bit is transmitted, the master device releases SDA, during which time, an acknowledge clock pulse is generated by the slave device. If the CV90312T receives the correct address, the device pulls the SDA line low, generating an acknowledge bit (ACK). Once the master device registers the ACK bit, the 8-bit register data word is sent. Each data bit should be stable while SCL is HIGH. After the 8-bit register data word is sent, the CV90312T sends another ACK bit. Following the acknowledgement of the register data word, the master issues a STOP bit, allowing SDA to go high. Initial Data Conditions Register Name Address D7 D6 D5 D4 D3 D2 D1 D0 Shutdown control 01 1 1 1 1 1 1 1 1 Phase control for Channel 0 (LSB) 02 0 0 0 0 0 0 0 0 Phase control for Channel 0 (MSB) 03 x x x x x x 0 0 UN-USED 04 x x x x x x x x UN-USED 05 x x x x x x x x Frequency control for Channel 0 (LSB) 06 0 0 0 0 0 0 0 0 Frequency control for Channel 0 (MSB) 07 x x x x x x 0 0 UN-USED 08 x x x x x x x x UN-USED 09 x x x x x x x x Dead-zone timing control for gate drivers 0A x x x x x x 0 0 Comparator Threshold control 0B x x x x x x 0 0 Chip enable 0C x x x x x x x 0 Enable Vsense and Isense input pins 0F x x x x x x 0 0 Dead-zone timing Control Register 0A Register Address Value (D1D0) Dead-zone window 0A 00 200ns 01 150ns 10 100ns 11 50ns Comparator Threshold Control Register 0B Register Value Threshold Voltage 7/5/2013 Rev 1.0 9/19
Address (D1D0) 0B 00 2.5V±20mV 01 2.5V±25mV 10 2.5V±30mV 11 2.5V±35mV Chip Enable Control Register 0C Register Address Value (D0) Description 0C 0 Disable Channel 1 Enable Channel Enable Protection signals Control Register 0F Register Address Value (D1) Description 0F 0 Enable Isense and Vsense input pins 1 Disable Isense and Vsense input pins 5 Functional Description The CV90312T is a wireless battery charging controller that controls transmitter functions, such as analog pings, variable frequency and phase output power control, analog demodulation, over-voltage, over-current and thermal protection. SYSTEM POWER UP/ SHUTDOWN The CV90312T can be powered up by writing C0 to register 01 follows by writing 01 to register 0C. The chip then operates in default condition. To change functions, please see Section 4 for details. The CV90312T can be shut down by writing FF to register 01. SERIAL INTERFACE See Section 4 7/5/2013 Rev 1.0 10/19
GATE DRIVER OUTPUTS The CV90312T provides 4 gate drivers. 2 floating high-side gate drivers, gatehil0 and gatehir0 and 2 ground referenced low-side gate drivers, gatelol0 and gatelor0. Each gate driver is capable of sourcing and sinking 0.5A peak current. The low-side gate drivers are powered by LDO5V. The high-side gate drivers are powered from a bootstrap capacitor connecting between bstrefr0/bstrefl0 and vodr0/vodl0, respectively. An external Schottky diode connecting between LDO5V and bstrefr0/bstrefl0 provides the high-side gate driver power. So when high-side gate driver is ON, the bstrefr0/bstrefl0 pin will see a voltage 5V higher than VCC. A recommended value of the bootstrap capacitor is 220nF or greater. The gate driver can be enabled by writing 0 to D2 locations of register 01 and 1 to register 0C 2 operating modes of gate driver are provided. They are phase-mode and duty-cycle mode. The selection of mode is depends on the value in D6 location of register 01. In phase mode, the gate driver duty cycle is kept constant at around 50%. The gate driver waveforms are shown in diagram below. The gate driver outputs gatehil, gatelol, gatehir & gatelor mainly depend on the setting of registers Reg P & Reg Phase. Reg P = 1, Reg Phase = 000 (Phase-mode) gatehil t deadzone gatelol gatehir 50% gatelor 7/5/2013 Rev 1.0 11/19
Reg P = 1, Reg Phase = 100 (Phase-mode) gatehil gatelol gatehir Phase gatelor Reg P = 0, Reg Phase = 100 (Duty-cycle mode) gatehil gatelol gatehir gatelor The range of Reg phase is from 0000-027F with lowest maximum phase shift = 180deg. In duty cycle mode, a minimum ON time for gate driver is required for proper operation. The gate driver must turn ON more than 3.6deg (Reg phase >010) or 50ns, whichever is larger. The operating frequency of the gate drivers are controlled by the internal oscillator. An external reference resistor connected between ROSC pin and ground defines the reference current for frequency generation. A typical value of 270kohm is used. To facilitate the battery charging scheme, the operating frequency of the gate drivers can be programmed by writing values in registers 06 to 09, please refer to Section 4 for details. The range of Reg freq is from 0000-027F. The highest minimum operating frequency is 96kHz and the lowest maximum operating frequency is 208kHz. 7/5/2013 Rev 1.0 12/19
PROTECTION The CV90312T features over-voltage and over-current protection. It monitors the bridge current and transmitter coil voltage continuously and shutdown the chip if the threshold is exceeded. Each channel has its own protection circuits. The over-current is sensed by ISENSE pin. If the pin voltage exceeds 335mV or 6.7% of LDO5V voltage, the channel will be shutdown and a 1 will write to the data location D0 register 01. This condition can be read by serial interface. VCC isense pwrnprotect The over-voltage is sensed by VSENSE pin. If the pin voltage exceeds 2.5V or 50% of LDO5V voltage, the channel will be shutdown and a 1 will write to the corresponding data location D0 in register 01. This condition can be read by serial interface. When a channel is shutdown due to over-voltage or over-current condition, the right and left low-side gate driver of the channel will pull to ground and the right and left high-side gate driver of the channel will pull to vodr0/vodl0 To read the protection condition, user can use command 79 and read data D0 from SDA line. When the data in location D0 is HIGH, the channel is in protection mode. 7 9 X D6 D5 D4 D3 D2 D1 D0 The VSENSE and ISENSE pins can be disabled when bit 0 (D0) of register 0F is written an 1. 7/5/2013 Rev 1.0 13/19
6 Application Circuit 7/5/2013 Rev 1.0 14/19
7 Package Information Mechanical Drawings of the QFN40 package 7/5/2013 Rev 1.0 15/19
8 Reflow solder Profile Profile Feature Preheat/Soak Temperature Min (T smin ) Temperature Max (T smax ) Time (t s ) from (T smin to T smax ) Ramp-up rate (T L to T P ) Liquidous temperature (T L ) Time (t L ) maintained above T L Peak package body temperature (T P ) Ramp down rate (T P to T L ) Time 25 to peak temperature Maximum Time (t P ) between T P and T P - 5 Maximum solder reflow cycles on one single device Pb-Free Assembly 150 200 60-120 seconds 3 /second max. 217 60-150 seconds 260, maximum 6 /second max. 8 minutes max. 30 seconds 3 7/5/2013 Rev 1.0 16/19
Tape and Reel drawings Mechanical drawing of the tape (3,000 units per tape) Chip Orientation on the tape Dot indicates pin 1 of the packaged unit 7/5/2013 Rev 1.0 17/19
Mechanical drawing of the reel How the reel is placed in the box: 7/5/2013 Rev 1.0 18/19
Update History Revision No. Description Remark Date CV90312T_V1r0 1. Preliminary version Preliminary version1.0 7 th Sept., 2013 CV90312T_V1r01 1. Updated pin assignment 2. Application circuit Preliminary version 1.01 8 th April, 2014 7/5/2013 Rev 1.0 19/19