Paper PWM Control Method for NPC Inverters with Very Small DC-Link Capacitors Member Roberto Rojas (The University of Tokushima) Member Tokuo Ohnishi (The University of Tokushima) Member Takayuki Suzuki (The University of Tokushima) Abstract: This paper examines the neutral voltage variations on a neutral point clamped (NPC) inverter circuit and proposes a new PWM technique which allows a great reduction in the capacitor values. Conventional and advanced control methods of the neutral point potential are analyzed demonstrating that the use of medium size vectors generates voltage fluctuations which can only be reduced by increasing the capacitor values. In this paper a new PWM control method is introduced. Different from former techniques, the use of the medium size vectors is avoided, increasing the neutral voltage controllable region to the whole range of operation under any load conditions making it possible to operate the NPC inverter with very small DC-link capacitors. The suitable voltage vector is carefully selected to reduce the output waveform distortion. The proposed PWM technique is experimentally verified on a low-power prototype and is compared with advanced control methods. The simulation and experimental results have shown that the proposed technique allows a great reduction in the capacitor values. Key Words: NPC inverter, Neutral point voltage control, Capacitor reduction, Voltage vector, Neutral point voltage analysis 1. Introduction Greater attention has been focused on the need to improve the performance and increase the power ratings of an inverter. Research in this field has been very progressive during the past decade and new inverter topologies have been developed. Neutral point clamped (NPC) inverters has been widely investigated in recent years because they improve the output waveform quality and allow equal voltage shearing of series-connected devices in each phase(1)-(4). The NPC inverters, however, have an inherent problem of neutral point potential variation. A deviation of the neutral voltage not only distorts the output waveforms but also causes unbalanced voltage stress to the switching devices. Several PWM techniques which emphasize in the DC-link capacitor voltage balancing problem have been introduced so far(1)-(4). The neutral point potential control methods presented so far can be classified in two groups that we will call conventional and advanced control methods. Conventional methods use uniform intervals for the small positive and small negative vectors(1), (2). Advanced methods use different intervals in order to compensate variations produced by medium size vectors (3), (4). Advanced methods increase the controllable region, however, large values in the capacitors are still needed especially for low power factor loads. In this paper a new PWM control method is introduced. With the new method the DC-link capacitor values can be reduced and still control the neutral point variations within a small range. Different from former presented PWM techniques, the use of the medium size vectors is avoided because they produce uncontrollable variations when small capacitors are usedtsl. Due to the reduction of the available vectors, the shape of the line-to-line output voltage is somewhat different at high references; but for medium and low references the waveforms are similar to those commonly used. To describe the inverter output voltage and to analyze the neutral point potential control, the concept of complex-space vectors is applied. In the following sections, the controllability of the conventional and advanced control methods are described and the new technique is introduced. 2. Space Vector Representation Fig. 1 shows the circuit configuration of the NPC inverter. Each arm of the inverter consists of four switching devices and produces three switching states according to Table 1. The combination of the switching states of the three arms generates the 27 NPC inverter voltage vectors. The space vector representation of the line-to-line voltage vectors is shown in Fig. 2. They are classified according to their amplitude. Thus, a-group corresponds to the large vectors; b group refers to the medium size vectors; c-group and d-group categorize the small vectors. The last group (z) is composed of zero vectors. For neutral balance conditions, vectors of c and d groups 1506 T. IEE Japan, Vol. 115-D, No. 12, '95
NPC Inverters with Very Small DC-Link Capacitors Table 2. Transformed NPC vectors. Fig. 1. Neutral-Point-Clamped inverter. generate the same output waveform. The inverter output voltages can be conveniently analyzed in a two-axis rotating coordinate system by using the following transformation equation. Where euv, evw, ewv, represent the line to line voltages and the term (ep, eq) represent the instantaneous voltage vector in the P, Q coordinates. Sinusoidal PWM waveforms can be obtained if the medium value of ep is controlled to be equal to the reference Table 1. Arm switching states. (Ep,=RMS value of the line to line output voltage) and the medium value of e4 is controlled to be zero. The ep and eq components of the transformed NPC vectors are listed in Table 2. 3. Neutral Voltage Variations Variations in the neutral point potential take place only when a vector of group b, c or d is applied to the output. Fig. 3 shows the load connections for vectors e5, d5 and b5. Considering the same DC-link capacitors CI=C2=C, the neutral voltage variations are calculated by Fig. 2. Space vector representation. Fig. 3. Load connection for c5, d5;, and b5; vectors.
(2) Therefore, the neutral current (i0) is the only responsible for the neutral unbalance. Vectors c5, d5 and b5 give a neutral current io equal to -iw, iw, and iu respectively (see Fig. 3). 3.1 Analysis of Conventional and Advanced Neutral Voltage Control Methods Fig. 4 shows the method frequently used to create a PWM pattern for NPC inverters. Every 60-degrees interval is divided in 4 triangular areas and the waveforms are generated by switching among the three vectors related with the area that includes the reference. For area 1 the vectors used are a5, b5, c5 and d5. The vectors' dwell time required to generate sinusoidal waveforms was determined in (4) as: (3) (4) vectors. But, since a3c+a3d should be equal to a3 in order to generate sinusoidal output waveforms, it is possible to control the neutral current only within the range (8) Outside this interval neutral voltage variations are expected. The variations depend not only on the load current amplitude but also on the power factor and the inverter voltage reference operation. On the other hand, if vectors of b-group are not used, it is always possible to control the neutral current using uniform intervals for c and d group vectors (a3c=a3d). The former analysis, valid only for area 1, can be easily extended to other areas. Fig. 5 shows the controllable region of the neutral point potential for the conventional, advanced and non-b (the one that does not use b-group vectors) control methods. The dashed line corresponds to an RMS line-to-line output voltage (Epr) equal to 0.61Ed; value commonly called "modulation index 1" in phase voltage control methods. Advanced methods increase the controllable region, but it is highly dependent on the load power factor (0.8 lagging in Fig. 5), and decreases for poor load power factors. Fig. 6 shows the average waveform of the neutral current for the three methods. The load power factor is 0.8 lagging and Epr = 0.61 (5) (6) Conventional neutral point potential control methods use uniform intervals for c and d group vectors (a3c=a3d). The average value of the neutral current then becomes (7) Since this current is different from zero, neutral voltage variations will certainly arise. In this case, the variations can be reduced only by increasing the capacitor values. Advanced control methods use different intervals for c and d groups (a3cxa3d) to compensate variations produced by b-group Fig. 4. Control method commonly used for NPC inverters. Fig. 6. Neutral current (pf=0.8 lagging Epr = 0.61 Ed): (a) conventional; (b) advanced; (c) non-b methods. 1508 T. lee Japan, Vol. 115-D, No. 12, '95
NPC Inverters with Very Small DC-Link Capacitors Fig. 7. Proposed vector selection. Table 3. Vectors used in each area. Ed. Advanced methods reduce the neutral current, but it still may produce undesirable neutral point potential variations. 4. Proposed PWM Method Although any non-b control method can reduce the neutral variations it is important to select appropriately the vectors to obtain high quality output waveforms. Among several possibilities we have selected the one shown infig. 7, because it offers a very good output waveform shape. Each 60-degrees interval of the space plane is divided in 5 areas. In every area the PWM pattern is generated by switching among three vectors, as listed in Table 3. The shape of the PWM line-to-line output voltage will be restrained to the shaded areas of Fig. 8 (a), (b) and (c) for high, medium and low references respectively. The area of greater step-changes (equal to Ed) diminishes when the input reference decreases. For reference values smaller than 0.35 Ed the maximum step-change is equal to Ed/2. Equations 9 and 10 describe the control operation for area 1 and similar equations can be written for other areas. Fig. 8. Line-to-line voltage shape for (a) high, (b) medium and (c) low references operation. (13) (14) 5. Alternatives' Evaluation and DC-link Capacitor Design Considerations A detailed analysis of the PWM patterns generated by conventional, advanced and the proposed technique is out of the scope of the present work, however, it is clear from Fig. 8 (a) that the commonly used NPC waveforms are of better quality. Therefore, if large capacitors are available, advanced control methods are the best choice. However, since large capacitors are expensive and bulky, small values are usually desirable and therefore the proposed (9) (10) From them the control region in terms of the ep variable can be determined as shown in Fig. 9. The equations of curves I IV are given by equations 11-14 respectively. (11) (12) Fig. 9. Control region of areas I 5.
Fig. 11. Control system. Table 4. Instantaneous vector selection. Fig. 10. normalized neutral variations (x) versus the load power factor (pf): (a) Epr= Ed/_??_2; (b) Epr=0.61Ed technique e could be very useful. to decide which technique The following analysis may help us is suitable for a specific application. The capacitor voltages are determined from equations 2-7. There are many variables involved, but the complex equations can be solved with the aid of numerical methods. Fig. 10 plots the normalized neutral variations versus the load power factor (pf) for conventional, advanced and non-b methods at a maximum reference (Epr= Ed/,/2) in Fig. 10 (a) and medium reference (Epr=0.6lEd) in Fig. 10 (b). The normalized variations are defined by Where I represents the RMS value of the load current, f is the output frequency (w=2 tf) and Aed refers to the deviation of the neutral potential up or down (+/-) the desired point (Ed/2). Knowing the load characteristics it is possible to determine the minimum capacitor value to restrain the variations in to a certain limit. The next is an example for the capacitor design: Assuming that +/ 3% (Aed = ± 0.03 Ed) is an acceptable variation, the minimum required capacitance for a 200-V, 3.6-A, 60-Hz, pf=0.8 load (used later in the simulations) can be calculated from Fig. 10 (a) Theoretically, for ideal switching devices, it is possible to remove the DC-link capacitors in the case of the non-b method. In practice, the minimum value is limited by the available switching frequency. In the example, if capacitors of several hundred micro-farads are not a problem it is preferable to use either conventional or advanced methods, but, if we want to use a smaller capacitance, the proposed technique is a good alternative. 6. Control System The control system is relatively simple; it is illustrated in Fig. 11. The line-to-line voltages are sensed and transformed to the P-Q rotating reference coordinates. Both components are controlled independently by hysteresis comparators. The instantaneous vector is chosen using the selection indicated in Table 4; where Epr correspond to the voltage reference and hp and hq are the hysteresis width of the ep and eq controllers respectively. 1510 T. IEE Japan, Vol. 115-D, No. 12, '95
NPC Inverters with Very Small DC-Link Capacitors Table 5. Operation of the neutral voltage controller An additional hysteresis comparator controller is used to balance the DC capacitor voltages. The operation of this controller is summarized in Table 5; where hn refers to its hysteresis width. The direction of the source current (is) determines whether is generative or regenerative operation. The information of the working area is given by the block "Area Detection". It uses multiplier type A/D converters to generate the curves given by equations 11-14 and then compares them with the reference. All the information is processed in an EPROM table that generates the command signals to the inverter elements. The design of the controllers' hysteresis width and the integrator time constant is a trade-off between the wave-form generation accuracy and the available switching frequency. 7. Simulations Results For the simulations, the DC source voltage was set to Ed=284-V, the output frequency was of f=60-hz, and the DC-link capacitors of C=C1=C2 (see Fig. 1). The voltage reference was kept in to its maximum controllable value (Ed/_??_2). For comparison purpose, the advanced method described in (4) has been chosen; any other advanced method, such as that of (3), will behave in a similar way. Figures 12 (a), (b) and (c) show the simulation waveforms for the advanced control method with R-L load. In Fig. 12(a), the power factor of the load was 0.8 lagging (R=25-f2, L=50-mH), and used the capacitor values calculated in Section 5, namely 215-RE As can he seen, the capacitor voltages edl and ed2 remain approximately equal to Ed/2 and the voltage vector components ep and eq are controlled within the hysteresis limits, which gives an almost sinusoidal line current. However, when the capacitors are reduced to 8-pF as in Fig. 12(b), the neutral voltage experiment wide variations which are not only dangerous for the switching devices but also produce a serious distortion in the output voltage and current. The influence of the load power factor is demonstrated in Fig. 12(c), where it was improved to pf=0.95 keeping constant the fundamental current amplitude (R=30-f2, L=25-mH). Clearly, compared with Fig. 12(b) the variations are much smaller, but they are still far from being considered acceptable. Fig. 13 shows the simulations using the proposed method. Al though the conditions were the same as those of Fig. 12(b), in Fig. 13 the neutral voltage is successfully controlled and the load current is nearly sinusoidal, proving the effectiveness of the proposed method. The waveforms with a 200-V, 0.75-kW induction motor load Fig. 12. Simulations for advanced method at Epr=200-V: (a) C=215uF, pf=0.8; (b) C=8uF, pf=0.8; (c) C=8-p.&, pf=0.95. Fig. 13. Simulations for proposed method at Epr=200-V; C=8 1A-F; pf=0.8 (R=25-S2, L=50-mH )
Fig. 14. Induction motor drive simulation: C=8-tF; Ed=284-V; working with constant volt/hertz operation at 40-Hz are plotted in Fig. 14. In spite of the very small capacitor used (C=8-uF), high quality voltage and current waveforms are appreciated, demonstrating the good performance of the proposed technique under induction motor load. 8. Experimental Results A low power prototype using the NPC inverter of Fig. 1 was constructed and tested in the laboratory. The conditions for the experiment were the same as those of the computer simulations of Fig. 12(c); namely Ed=284-V, f=60-hz, C1=C2=8-uF, Ep1=200-V, R=30-Q, and L=25-mH. Fig. 15 shows the capacitor voltage edl and the line-to-line output voltage e v for (a) the proposed control method and (b) advanced method. The figures demonstrate that the real performance is in good agreement with the simulated performance. The induction motor drive operation is illustrated in Fig. 16. The conditions were the same as those of Fig. 14. Again the results are similar to the simulations proving the feasibility of the proposed control technique. 9. Conclusions The neutral-point-potential control region of conventional and advanced PWM methods for NPC inverter were analyzed. Advanced methods improve the controllability but it is still restrained to a limited region which is greatly depended on the load power factor and the operating point. In this view, a new PWM technique which is capable of controlling the neutral variations under any load conditions over the whole range of operation was proposed. The new technique allows a great reduction in the capacitor values, limited only by the switching frequency of the inverter elements. Computer simulations and experimental setup demonstrated that the new technique allows successful operation under conditions that conventional and advanced control methods present unacceptable neutral voltage variations. The new technique is particularly attractive when very poor power factor operation is required and or when high speed switching devices are Fig. 16. Induction motor drive operation: C=8-µF; Ed=284-V; Epr=133-V; f=40-hz. available. (Manuscript received February 20, 1995, revised August 4, 1995) References (1) T. Kawabata, M. Koyama, S. Tamai, T. Fuji, R. Uchida, "A New PWM Method of a Three-Level Inverter Considering Minimum Pulse Width and Neutral Voltage Balance Control", Trans. ME JAPAN Ind. Appl., vol. 113-D, No. 7, pp. 865-873, 1993 1512 T. IEE Japan, Vol. 115-D, No. 12, '95
NPC Inverters with Very Small DC-Link Capacitors (2) J. K. Steinke, "Switching Frequency Optimal PWM Control of a Three-Level Inverter", IEEE Trans. Power Electronics, vol. 7, No 3, pp. 487-496, 1992 (3) S. Ogasawara, T. Sawada, H. Akagi, "Analysis of the Neutral Point Potential Variation of Neutral-Point-Clamped Voltage Source PWM Inverters", Trans. IEE JAPAN Ind. Appl., vol. 113-D, No. 1, pp. 41-48, 1993 (4) R. Rojas, T. Ohnishi, T. Suzuki, "An Improved Voltage Vector Control Method for Neutral-Point-Clamped Inverters", Proc. PESC'94, pp. 951-957, 1994 (5) R. Rojas, T. Ohnishi, T. Suzuki, "Simple Structure and Control Method of a Neutral Point Clamped PWM Inverter", Proc. PCC Yokohama, pp. 26-31, 1993 Roberto Rojas (Member) He was bom in Quito, Ecuador on May The University of Tokushima. electronics 1, 1960. He received the Eng. degree in electrical engineering from the Escuela Politecnica Nacional University, Quito, Ecuador, in 1984 and the M.S. degree from The University of Tokushima, Tokushima, Japan in 1993. He is currently working toward the Ph.D. degree at His main research interest is in power Tokuo Ohnishi (Member) He was bom in Tokushima, Japan, on September 30, 1947. He received the B.S. and M.S. degree in electrical engineering from The University of Tokushima, Tokushima, Japan in 1970, 1972 respectively and the Ph.D. degree in electrical engineering from The University of Tokyo, Tokyo, Japan, in 1987. Since 1972 he has been with the Department of Electrical Engineering, The University of Tokushima where he is presently Professor. His main research interests are in power electronics. Dr. Ohnishi is a member of SICE and IEEE. Takayuki Suzuki (Member) He was bom in Seoul, Korea, on March 14, 1939. He received the B.S. and M.S. degrees in electrical engineering from The University of Tokushima and the Ph.D. from Kyoto University, Japan, in 1962, 1966 and 1975, respectively. Since 1966 he has been with the Department of Electrical and Electronic Engineering, The University of Tokushima, Japan, where he is presently Professor. His fields of research and lecture are control system and electrical machines. Dr Suzuki is a member of SICE and IEICE of Japan.