Data Sheet FEATURES Input voltage range:.5 V to 5.5 V Dual independent ma low dropout voltage regulators Miniature 6-ball,. mm.5 mm WLCSP and 6-ball bumped bare die Initial accuracy: ±% Stable with µf ceramic output capacitors No noise bypass capacitor required Two independent logic controlled enables Overcurrent and thermal protection Active output pull-down (ADP) Key specifications High PSRR 76 db PSRR up to khz 7 db PSRR at khz 6 db PSRR at khz 4 db PSRR at MHz Low output noise 7 µv rms typical output noise at VOUT =. V 5 µv rms typical output noise at VOUT =.8 V Excellent transient response Low dropout voltage: 5 mv @ ma load 6 µa typical ground current at no load, both LDOs enabled µs fast turn-on circuit Guaranteed ma output current per regulator 4 C to +5 C junction temperature APPLICATIONS Mobile phones Digital cameras and audio devices Portable and battery-powered equipment Portable medical devices Post dc-to-dc regulation GENERAL DESCRIPTION The ma dual output ADP/ADP combine high PSRR, low noise, low quiescent current, and low dropout voltage in a voltage regulator ideally suited for wireless applications with demanding performance and board space requirements. The low quiescent current, low dropout voltage, and wide input voltage range of the ADP/ADP extend the battery life of portable devices. The ADP/ADP maintain power supply rejection greater than 6 db for frequencies as high as khz while operating with a low headroom voltage. The ADP offers much lower noise performance than competing LDOs Dual, ma, Low Noise, High PSRR Voltage Regulator ADP/ADP VIN EN EN GND OFF OFF ON ON TYPICAL APPLICATION CIRCUITS A B C THERMAL SHUTDOWN CONTROL LOGIC AND ENABLE ADP EN GND EN VOUT VIN TOP VIEW (Not to Scale) VOUT Figure. Typical Application Circuit CURRENT LIMIT REFERENCE CURRENT LIMIT ADP ONLY V OUT =.8V µf V IN = 3.3V µf V OUT =.8V µf 6Ω 6Ω Figure. Block Diagram of the ADP/ADP 757- VOUT VOUT without the need for a noise bypass capacitor. The ADP also includes an active pull-down to quickly discharge output loads. The ADP/ADP are available in a miniature 6-ball WLCSP package and 6-ball bumped bare die and is stable with tiny µf ± 3% ceramic output capacitors, resulting in the smallest possible board area for a wide variety of portable power needs. The ADP/ADP are available in many output voltage combinations, ranging from.8 V to 3.3 V, and offer overcurrent and thermal protection to prevent damage in adverse conditions. 757- Rev. H Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 96, Norwood, MA 6-96, U.S.A. Tel: 78.39.47 8 3 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com
ADP/ADP TABLE OF CONTENTS Features... Applications... Typical Application Circuits... General Description... Revision History... Specifications... 3 Input and Output Capacitor, Recommended Specifications.. 4 Absolute Maximum Ratings... 5 Thermal Data... 5 Thermal Resistance... 5 ESD Caution... 5 Pin Configuration and Function Descriptions... 6 REVISION HISTORY /3 Rev. G to Rev. H Changes to Undervoltage Lockout Input Voltage Rising Parameter and Undervoltage Lockout Input Voltage Falling Parameter, Table... 3 / Rev. F to Rev. G Added 6-Ball Bumped Bare Die (CD-6-7)... Universal Change to Undervoltage Lockout Input Voltage Rising Parameter, Table... 3 Updated Outline Dimensions... 7 Moved Ordering Guide... 8 4/ Rev. E to Rev. F Changes to Ordering Guide... 7 / Rev. D to Rev. E Changes to Ordering Guide... 7 5/ Rev. C to Rev. D Changes to Figure... Changes to Ordering Guide... 7 Data Sheet Typical Performance Characteristics...7 Theory of Operation... Applications Information... Capacitor Selection... Undervoltage Lockout... 3 Enable Feature... 3 Current-Limit and Thermal Overload Protection... 4 Thermal Considerations... 4 Printed Circuit Board (PCB) Layout Considerations... 6 Outline Dimensions... 7 Ordering Guide... 8 / Rev. B to Rev. C Changes to Figure 4... /9 Rev. A to Rev. B Changes to Features Section... Changes to Table 3 and Table 4... 5 Changes to Figure 4, Figure 6, Figure 7, and Figure 9... 7 Changes to Figure and Figure... 8 Changes to Figure 7... 9 Changes to Figure 5... Changes to Enable Feature Section and Figure 3... 3 Changes to Current-Limit and Thermal Overland Protection Section and Thermal Considerations Section... 4 Changes to Ordering Guide... 7 3/9 Rev. to Rev. A Changes to Figure 5... 8 Changes to Figure 6... 9 Changes to Ordering Guide... 7 /8 Revision : Initial Version Rev. H Page of
Data Sheet ADP/ADP SPECIFICATIONS VIN = (VOUT +.5 V) or.5 V (whichever is greater), EN = EN = VIN, IOUT = IOUT = ma, CIN = COUT = COUT = µf, TA = 5 C, unless otherwise noted. Table. Parameter Symbol Conditions Min Typ Max Unit INPUT VOLTAGE RANGE VIN TJ = 4 C to +5 C.5 5.5 V OPERATING SUPPLY CURRENT WITH IGND IOUT = µa 6 µa BOTH REGULATORS ON IOUT = µa, TJ = 4 C to +5 C µa IOUT = ma 7 µa IOUT = ma, TJ = 4 C to +5 C 4 µa IOUT = ma µa IOUT = ma, TJ = 4 C to +5 C µa SHUTDOWN CURRENT IGND-SD EN= EN = GND. µa EN= EN = GND, TJ = 4 C to +5 C µa FIXED OUTPUT VOLTAGE ACCURACY VOUT + % µa < IOUT < ma, VIN = (VOUT +.5 V) to + % 5.5 V, TJ = 4 C to +5 C LINE REGULATION VOUT/ VIN VIN = (VOUT +.5 V) to 5.5 V. %/V VIN = (VOUT +.5 V) to 5.5 V, TJ = 4 C to +5 C.3 +.3 %/V LOAD REGULATION VOUT/ IOUT IOUT = ma to ma. %/ma IOUT = ma to ma, TJ = 4 C to +5 C.3 %/ma DROPOUT VOLTAGE VDROPOUT VOUT = 3.3 V mv IOUT = ma 7.5 mv IOUT = ma, TJ = 4 C to +5 C mv IOUT = ma 5 mv IOUT = ma, TJ = 4 C to +5 C 3 mv START-UP TIME 3 tstart-up VOUT = 3.3 V, both initially off, enable one 4 µs VOUT =.8 V, both initially off, enable one µs VOUT = 3.3 V, one initially on, enable second 8 µs VOUT =.8 V, one initially on, enable second µs ACTIVE PULL-DOWN RESISTANCE tshutdown VOUT =.8 V, RLOAD =, COUT = μf, ADP only 8 Ω CURRENT-LIMIT THRESHOLD 4 ILIMIT 4 3 44 ma THERMAL SHUTDOWN Thermal Shutdown Threshold TSSD TJ rising 55 C Thermal Shutdown Hysteresis TSSD-HYS 5 C EN INPUT EN Input Logic High VIH.5 V VIN 5.5 V. V EN Input Logic Low VIL.5 V VIN 5.5 V.4 V EN Input Leakage Current VI-LEAKAGE EN = EN = VIN or GND. µa EN = EN = VIN or GND, TJ = 4 C to +5 C µa UNDERVOLTAGE LOCKOUT UVLO Input Voltage Rising UVLORISE.45 V Input Voltage Falling UVLOFALL..35 V Hysteresis UVLOHYS mv OUTPUT NOISE OUTNOISE Hz to khz, VIN = 5 V, VOUT = 3.3 V 56 µv rms Hz to khz, VIN = 5 V, VOUT =.8 V 5 µv rms Hz to khz, VIN = 3.6 V, VOUT =.5 V 45 µv rms Hz to khz, VIN = 3.6 V, VOUT =. V 7 µv rms Rev. H Page 3 of
ADP/ADP Data Sheet Parameter Symbol Conditions Min Typ Max Unit POWER SUPPLY REJECTION RATIO PSRR VIN =.5 V, VOUT =.8 V, IOUT = ma Hz 76 db khz 76 db khz 7 db khz 6 db MHz 4 db VIN = 3.8 V, VOUT =.8 V, IOUT = ma Hz 68 db khz 68 db khz 68 db khz 6 db MHz 4 db Based on an end-point calculation using ma and ma loads. Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output voltages above.5 V. 3 Start-up time is defined as the time between the rising edge of ENx to VOUTx being at 9% of its nominal value. 4 Current-limit threshold is defined as the current at which the output voltage drops to 9% of the specified typical value. For example, the current limit for a 3. V output voltage is defined as the current that causes the output voltage to drop to 9% of 3. V, or.7 V. INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS Table. Parameter Symbol Conditions Min Typ Max Unit MINIMUM INPUT AND OUTPUT CAPACITANCE CMIN TA = 4 C to +5 C.7 µf CAPACITOR ESR RESR TA = 4 C to +5 C. Ω The minimum input and output capacitance should be greater than.7 µf over the full range of operating conditions. The full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended; Y5V and Z5U capacitors are not recommended for use with LDOs. Rev. H Page 4 of
Data Sheet ABSOLUTE MAXIMUM RATINGS Table 3. Parameter VIN to GND VOUT, VOUT to GND EN, EN to GND Storage Temperature Range Operating Junction Temperature Range Soldering Conditions Rating.3 V to +6.5 V.3 V to VIN.3 V to +6.5 V 65 C to +5 C 4 C to +5 C JEDEC J-STD- Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL DATA Absolute maximum ratings apply individually only, not in combination. The ADP/ADP can be damaged when the junction temperature limits are exceeded. Monitoring ambient temperature does not guarantee that the junction temperature (TJ) is within the specified temperature limits. In applications with high power dissipation and poor thermal resistance, the maximum ambient temperature may have to be derated. In applications with moderate power dissipation and low PCB thermal resistance, the maximum ambient temperature can exceed the maximum limit as long as the junction temperature is within specification limits. The junction temperature (TJ) of the device is dependent on the ambient temperature (TA), the power dissipation of the device (PD), and the junction-to-ambient thermal resistance of the package (θja). Maximum junction temperature (TJ) is calculated from the ambient temperature (TA) and power dissipation (PD) using the following formula: TJ = TA + (PD θja) ADP/ADP Junction-to-ambient thermal resistance (θja) of the package is based on modeling and calculation using a 4-layer board. The junction-to-ambient thermal resistance is highly dependent on the application and board layout. In applications where high maximum power dissipation exists, close attention to thermal board design is required. The value of θja may vary, depending on PCB material, layout, and environmental conditions. The specified values of θja are based on a four-layer, 4 inch 3 inch, circuit board. Refer to JEDEC JESD 5-9 for detailed information on the board construction. For additional information, see the AN-67 Application Note, MicroCSP TM Wafer Level Chip Scale Package. ΨJB is the junction-to-board thermal characterization parameter with units of C/W. ΨJB of the package is based on modeling and calculation using a 4-layer board. The JESD5-, Guidelines for Reporting and Using Package Thermal Information, states that thermal characterization parameters are not the same as thermal resistances. ΨJB measures the component power flowing through multiple thermal paths rather than a single path as in thermal resistance, θjb. Therefore, ΨJB thermal paths include convection from the top of the package as well as radiation from the package. Factors that make ΨJB more useful in realworld applications. Maximum junction temperature (TJ) is calculated from the board temperature (TB) and power dissipation (PD) using the following formula: TJ = TB + (PD ΨJB) Refer to JEDEC JESD5-8 and JESD5- for more detailed information on ΨJB. THERMAL RESISTANCE θja and ΨJB are specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 4. Package Type θja ΨJB Unit 6-Ball,.5 mm Pitch WLCSP 6 43.8 C/W 6-Ball Bumped Bare Die 6 43.8 C/W ESD CAUTION Rev. H Page 5 of
ADP/ADP Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS A EN VOUT B GND VIN C EN VOUT TOP VIEW (BALL SIDE DOWN) Not to Scale Figure 3. Pin Configuration 757-3 Table 5. Pin Function Descriptions Pin No. Mnemonic Description A EN Enable Input for Regulator. Drive EN high to turn on Regulator ; drive it low to turn off Regulator. For automatic startup, connect EN to VIN. B GND Ground Pin. C EN Enable Input for Regulator. Drive EN high to turn on Regulator ; drive it low to turn off Regulator. For automatic startup, connect EN to VIN. A VOUT Regulated Output Voltage. Connect a µf or greater output capacitor between VOUT and GND. B VIN Regulator Input Supply. Bypass VIN to GND with a µf or greater capacitor. C VOUT Regulated Output Voltage. Connect a µf or greater output capacitor between VOUT and GND. Rev. H Page 6 of
Data Sheet ADP/ADP TYPICAL PERFORMANCE CHARACTERISTICS VIN = 3.3 V, VOUT = VOUT =.8 V, IOUT = ma, CIN = COUT = COUT = µf, TA = 5 C, unless otherwise noted..85 4 OUTPUT VOLTAGE (V).83.8.79.77 I LOAD = µa I LOAD = µa I LOAD = ma I LOAD = ma I LOAD = ma I LOAD = ma GROUND CURRENT (µa) 8 6 4 I LOAD = µa I LOAD = µa I LOAD = ma I LOAD = ma I LOAD = ma I LOAD = ma.75 4 5 5 85 5 JUNCTION TEMPERATURE ( C) 757-4 4 5 5 85 5 JUNCTION TEMPERATURE ( C) 757-7 Figure 4. Output Voltage vs. Junction Temperature Figure 7. Ground Current vs. Junction Temperature, Single Output Loaded.85.83 V OUT =.8V V IN = 3.3V T A = 5 C V OUT =.8V V IN = 3.3V T A = 5 C OUTPUT VOLTAGE (V).8.79 GROUND CURRENT (µa) 8 6 4.77.75.. k LOAD CURRENT (ma) 757-5.. k LOAD CURRENT (ma) 757-8 Figure 5. Output Voltage vs. Load Current Figure 8. Ground Current vs. Load Current, Single Output Loaded.85 OUTPUT VOLTAGE (V).83.8.79.77 V OUT =.8V T A = 5 C I LOAD = µa I LOAD = µa I LOAD = ma I LOAD = ma I LOAD = ma I LOAD = ma GROUND CURRENT (µa) 8 6 4 I LOAD = µa I LOAD = µa I LOAD = ma I LOAD = ma I LOAD = ma I LOAD = ma.75 3.3 3.5 3.7 3.9 4. 4.3 4.5 4.7 4.9 5. 5.3 5.5 INPUT VOLTAGE (V) Figure 6. Output Voltage vs. Input Voltage 757-6 3.3 3.5 3.7 3.9 4. 4.3 4.5 4.7 4.9 5. 5.3 5.5 INPUT VOLTAGE (V) Figure 9. Ground Current vs. Input Voltage, Single Output Loaded 757-9 Rev. H Page 7 of
ADP/ADP Data Sheet GROUND CURRENT (µa) 6 4 8 6 4 4 5 5 85 5 JUNCTION TEMPERATURE ( C) I LOAD = µa I LOAD = µa I LOAD = ma I LOAD = ma I LOAD = ma I LOAD = ma Figure. Ground Current vs. Junction Temperature, Both Outputs Loaded 757- SHUTDOWN CURRENT (µa).9.8.7.6.5.4.3.. 3.3V 3.6V 4.V 4.3V 4.9V 5.5V 5 5 5 5 75 5 TEMPERATURE ( C) Figure 3. Shutdown Current vs. Temperature at Various Input Voltages 757-3 4 V OUT =.8V V IN = 3.3V T A = 5 C 5.5V.8V 3.3V GROUND CURRENT (µa) 8 6 4 DROPOUT VOLTAGE (mv) 5 5.. k LOAD CURRRENT (ma) Figure. Ground Current vs. Load Current, Both Outputs Loaded 757- k LOAD CURRENT (ma) Figure 4. Dropout Voltage vs. Load Current and Output Voltage 757-4 GROUND CURRENT (µa) 4 8 6 4 3.3 3.5 3.7 3.9 4. 4.3 4.5 4.7 4.9 5. 5.3 5.5 INPUT VOLTAGE (V) I LOAD = µa I LOAD = µa I LOAD = ma I LOAD = ma I LOAD = ma I LOAD = ma Figure. Ground Current vs. Input Voltage, Both Outputs Loaded 757- OUTPUT VOLTAGE (V).9.85.8.75.7.65.6.55 I LOAD = ma I LOAD = 5mA.5 I LOAD = ma I LOAD = 5mA.45 I LOAD = ma I LOAD = ma.4.6.7.8.9 3. 3. INPUT VOLTAGE (V) Figure 5. Output Voltage vs. Input Voltage (In Dropout) 757-5 Rev. H Page 8 of
Data Sheet ADP/ADP GROUND CURRENT (µa) 8 6 4 8 6 I LOAD = ma 4 I LOAD = 5mA I LOAD = ma I LOAD = 5mA I LOAD = ma I LOAD = ma.6.7.8.9 3. 3. INPUT VOLTAGE (V) Figure 6. Ground Current vs. Input Voltage (In Dropout) 757-6 PSRR (db) 3 4 5 6 7 8 9 V RIPPLE = 5mV V IN =.5V V OUT =.8V C OUT = µf ma ma ma ma µa k k k M M FREQUENCY (Hz) Figure 9. Power Supply Rejection Ratio vs. Frequency,.8 V 757-9 3 4 V RIPPLE = 5mV V IN = 3.8V V OUT =.8V C OUT =.µf ma ma ma ma µa 3 3.3V/mA.8V/mA.8V/mA 3.3V/µA.8V/µA.8V/µA PSRR (db) 5 6 7 PSRR (db) 4 5 6 8 7 9 8 9 k k k M M FREQUENCY (Hz) Figure 7. Power Supply Rejection Ratio vs. Frequency,.8 V 757-7 k k k M M FREQUENCY (Hz) Figure. Power Supply Rejection Ratio vs. Frequency, at Various Output Voltages and Load Currents 757- PSRR (db) 3 4 5 6 7 8 V RIPPLE = 5mV V IN = 4.3V V OUT = 3.3V C OUT = µf ma ma ma ma µa OUTPUT NOISE SPECTRUM (µv/ Hz). 3.3V µv/ Hz.8V µv/ Hz.8V µv/ Hz 9 k k k M M FREQUENCY (Hz) Figure 8. Power Supply Rejection Ratio vs. Frequency, 3.3 V 757-8. k k k FREQUENCY (Hz) Figure. Output Noise Spectrum, VIN = 5 V, ILOAD = ma 757- Rev. H Page 9 of
ADP/ADP Data Sheet 6 T V IN = 4V TO 5V, I LOAD = ma, I LOAD = ma 5 V IN NOISE (µv rms) 4 3 V OUT V OUT 3.3V.8V.8V.8V 3... k LOAD CURRENT (ma) Figure. Output Noise vs. Load Current and Output Voltage, VIN = 5 V 757- CH.V B W CH 5.mV B W M.μs A CH 4.46V CH3 5.mV B T 3.6% W Figure 5. Line Transient Response, VIN = 4 V to 5 V, ILOAD = ma, ILOAD = ma CH = VIN, CH = VOUT, CH3 = VOUT 757-5 T I LOAD I LOAD = ma TO ma, I LOAD = ma T V IN = 4V TO 5V, I LOAD = ma, I LOAD = ma V IN V OUT V OUT 3 V OUT 3 V OUT CH ma Ω B W CH 5.mV B W M4.μs A CH CH3.mV B T.% W Figure 3. Load Transient Response, ILOAD = ma to ma, ILOAD = ma CH = ILOAD, CH = VOUT, CH3 = VOUT 3mA 757-3 CH.V B W CH 5.mV B W M.μs A CH 4.46V CH3 5.mV B T.% W Figure 6. Line Transient Response VIN = 4 V to 5 V, ILOAD = ma, ILOAD = ma CH = VIN, CH = VOUT, CH3 = VOUT 757-6 T T I LOAD I LOAD = ma TO ma, I LOAD = ma V OUT 3 V OUT 3 CH ma Ω B W CH 5.mV B W M4.μs A CH CH3.mV B T.% W 3mA 757-4 CH 5.V B W CH.V B W M4.μs A CH.V CH3.V B T 9.8% W 757-7 Figure 4. Load Transient Response, ILOAD = ma to ma, ILOAD = ma, CH = ILOAD, CH = VOUT, CH3 = VOUT Figure 7. Shutdown Response, ADP Rev. H Page of
Data Sheet THEORY OF OPERATION The ADP/ADP are low quiescent current, low dropout linear regulators that operate from.5 V to 5.5 V and provide up to ma of current from each output. Drawing a low μa quiescent current (typical) at full load makes the ADP/ ADP ideal for battery-operated portable equipment. Shutdown current consumption is typically na. Optimized for use with small µf ceramic capacitors, the ADP/ADP provide excellent transient performance. VIN EN EN GND THERMAL SHUTDOWN CONTROL LOGIC AND ENABLE ADP CURRENT LIMIT REFERENCE CURRENT LIMIT ADP ONLY 6Ω 6Ω VOUT ADP/ADP Internally, the ADP/ADP consist of a reference, two error amplifiers, two feedback voltage dividers, and two PMOS pass transistors. Output current is delivered via the PMOS pass device, which is controlled by the error amplifier. The error amplifier compares the reference voltage with the feedback voltage from the output and amplifies the difference. If the feedback voltage is lower than the reference voltage, the gate of the PMOS device is pulled lower, allowing more current to flow and increasing the output voltage. If the feedback voltage is higher than the reference voltage, the gate of the PMOS device is pulled higher, allowing less current to flow and decreasing the output voltage. The ADP also includes an active pull-down circuit to rapidly discharge the output load capacitance when each output is disabled. The ADP/ADP are available in multiple output voltage options ranging from.8 V to 3.3 V. The ADP/ADP use the EN/EN pins to enable and disable the VOUT/VOUT pins under normal operating conditions. When EN/EN are high, VOUT/VOUT turn on; when EN/EN are low, VOUT/ VOUT turn off. For automatic startup, EN/EN can be tied to VIN. Figure 8. Internal Block Diagram VOUT 757-8 Rev. H Page of
ADP/ADP APPLICATIONS INFORMATION CAPACITOR SELECTION Output Capacitor The ADP/ADP are designed for operation with small, space-saving ceramic capacitors, but the parts function with most commonly used capacitors as long as care is taken with regards to the effective series resistance (ESR) value. The ESR of the output capacitor affects stability of the LDO control loop. A minimum of.7 µf capacitance with an ESR of Ω or less is recommended to ensure stability of the ADP/ADP. Transient response to changes in load current is also affected by output capacitance. Using a larger value of output capacitance improves the transient response of the ADP/ADP to large changes in the load current. Figure 9 and Figure 3 show the transient responses for output capacitance values of µf and 4.7 µf, respectively. V OUT T I LOAD I LOAD = ma TO ma, I LOAD = ma Data Sheet Input Bypass Capacitor Connecting a µf capacitor from VIN to GND reduces the circuit sensitivity to the PCB layout, especially when long input traces or high source impedance are encountered. If an output capacitance greater than µf is required, the input capacitor should be increased to match it. Input and Output Capacitor Properties Any good quality ceramic capacitor can be used with the ADP/ ADP, as long as the capacitor meets the minimum capacitance and maximum ESR requirements. Ceramic capacitors are manufactured with a variety of dielectrics, each with a different behavior over temperature and applied voltage. Capacitors must have an adequate dielectric to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. X5R or X7R dielectrics with a voltage rating of 6.3 V or V are recommended. Y5V and Z5U dielectrics are not recommended, due to their poor temperature and dc bias characteristics. Figure 3 depicts the capacitance vs. voltage bias characteristic of an 4 µf, V, X5R capacitor. The voltage stability of a capacitor is strongly influenced by the capacitor size and voltage rating. In general, a capacitor in a larger package or higher voltage rating exhibits better stability. The temperature variation of the X5R dielectric is about ±5% over the 4 C to +85 C temperature range and is not a function of the package or voltage rating. 3 V OUT, C OUT = µf. CH ma Ω B W CH 5.mV B W Mns A CH CH3.mV B T 6.6% W Figure 9. Output Transient Response ILOAD = ma to ma, ILOAD = ma CH = ILOAD, CH = VOUT, CH3 = VOUT, COUT = µf T I LOAD 3mA 757-9 CAPACITANCE (µf)..8.6.4 I LOAD = ma TO ma, I LOAD = ma V OUT. 4 6 8 VOLTAGE (V) Figure 3. Capacitance vs. Voltage Bias Characteristic 757-3 3 V OUT, C OUT = 4.7µF CH ma Ω B W CH 5.mV B W M.µs A CH CH3.mV B T.4% W 3mA Figure 3. Output Transient Response ILOAD = ma to ma, ILOAD = ma CH = ILOAD, CH = VOUT, CH3 = VOUT, COUT = 4.7 µf 757-3 Rev. H Page of
Data Sheet Equation can be used to determine the worst-case capacitance accounting for capacitor variation over temperature, component tolerance, and voltage. where: CEFF = CBIAS ( TEMPCO) ( TOL) () CBIAS is the effective capacitance at the operating voltage. TEMPCO is the worst-case capacitor temperature coefficient. TOL is the worst-case component tolerance. In this example, TEMPCO over 4 C to +85 C is assumed to be 5% for an X5R dielectric. TOL is assumed to be %, and CBIAS is.94 μf at.8 V from the graph in Figure 3. Substituting these values into Equation yields CEFF =.94 μf (.5) (.) =.79 μf Therefore, the capacitor chosen in this example meets the minimum capacitance requirement of the LDO over temperature and tolerance at the chosen output voltage. To guarantee the performance of the ADP/ADP, it is imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capacitors be evaluated for each application. UNDERVOLTAGE LOCKOUT The ADP/ADP have an internal undervoltage lockout circuit that disables all inputs and the output when the input voltage is less than approximately. V. This ensures that the inputs of the ADP/ADP and the output behave in a predictable manner during power-up. ENABLE FEATURE The ADP/ADP use the ENx pins to enable and disable the VOUTx pins under normal operating conditions. Figure 3 shows a rising voltage on ENx crossing the active threshold, then VOUTx turns on. When a falling voltage on ENx crosses the inactive threshold, VOUTx turns off. ADP/ADP As shown in Figure 3, the ENx pins have built-in hysteresis. This prevents on/off oscillations that can occur due to noise on the ENx pins as it passes through the threshold points. The active/inactive thresholds of the ENx pins are derived from the VIN voltage. Therefore, these thresholds vary with changing input voltage. Figure 33 shows typical ENx active/inactive thresholds when the input voltage varies from.5 V to 5.5 V. ENx PINS THRESHOLD (V)..95.9.85.8.75.7.65 EN ACTIVE EN INACTIVE.6.5 3. 3.5 4. 4.5 5. 5.5 INPUT VOLTAGE (V) Figure 33. Typical ENx Pins Thresholds vs. Input Voltage The ADP/ADP utilize an internal soft start to limit the inrush current when the output is enabled. The start-up time for the.8 V option is approximately µs from the time the ENx active threshold is crossed to when the output reaches 9% of its final value. The start-up time is somewhat dependent on the output voltage setting and increases slightly as the output voltage increases. T 757-33 T V OUTx ENx 3 CH 5.V B W CH.V B W M4.µs A CH.V CH3.V B W T 9.8% Figure 34. Typical Start-Up Time 757-34 CH 5mV B W CH 5mV B W M.ms A CH.76V T 7.4% Figure 3. Typical ENx Pin Operation 757-3 Rev. H Page 3 of
ADP/ADP CURRENT-LIMIT AND THERMAL OVERLOAD PROTECTION The ADP/ADP are protected against damage due to excessive power dissipation by current and thermal overload protection circuits. The ADP/ADP are designed to current limit when the output load reaches 3 ma (typical). When the output load exceeds 3 ma, the output voltage is reduced to maintain a constant current limit. Thermal overload protection is built-in, which limits the junction temperature to a maximum of 55 C (typical). Under extreme conditions (that is, high ambient temperature and power dissipation) when the junction temperature starts to rise above 55 C, the output is turned off, reducing the output current to zero. When the junction temperature drops below 4 C, the output is turned on again and the output current is restored to its nominal value. Consider the case where a hard short from VOUTx to GND occurs. At first, the ADP/ADP current limit, so that only 3 ma is conducted into the short. If self-heating of the junction is great enough to cause its temperature to rise above 55 C, thermal shutdown activates, turning off the output and reducing the output current to zero. As the junction temperature cools and drops below 4 C, the output turns on and conducts 3 ma into the short, again causing the junction temperature to rise above 55 C. This thermal oscillation between 4 C and 55 C causes a current oscillation between ma and 3 ma that continues as long as the short remains at the output. Current and thermal limit protections are intended to protect the device against accidental overload conditions. For reliable operation, device power dissipation must be externally limited so that junction temperatures do not exceed 5 C. THERMAL CONSIDERATIONS In most applications, the ADP/ADP do not dissipate much heat due to high efficiency. However, in applications with a high ambient temperature and high supply voltage to output voltage differential, the heat dissipated in the package is large enough that it can cause the junction temperature of the die to exceed the maximum junction temperature of 5 C. When the junction temperature exceeds 55 C, the converter enters thermal shutdown. It recovers only after the junction temperature has decreased below 4 C to prevent any permanent damage. Therefore, thermal analysis for the chosen application is very important to guarantee reliable performance over all conditions. The junction temperature of the die is the sum of the ambient temperature of the environment and the temperature rise of the package due to the power dissipation, as shown in Equation. Data Sheet To guarantee reliable operation, the junction temperature of the ADP/ADP must not exceed 5 C. To ensure that the junction temperature stays below this maximum value, the user needs to be aware of the parameters that contribute to junction temperature changes. These parameters include ambient temperature, power dissipation in the power device, and thermal resistances between the junction and ambient air (θja). The θja number is dependent on the package assembly compounds used and the amount of copper to which the GND pins of the package are soldered on the PCB. Table 6 shows typical θja values for the ADP/ADP for various PCB copper sizes. Table 6. Typical θja Values Copper Size (mm ) ADP/ADP ( C/W) 5 9 8 3 5 5 3 Device soldered to minimum size pin traces. The junction temperature of the ADP/ADP can be calculated from the following equation: TJ = TA + (PD θja) () where: TA is the ambient temperature. PD is the power dissipation in the die, given by PD = Σ[(VIN VOUT) ILOAD] + Σ(VIN IGND) (3) where: ILOAD is the load current. IGND is the ground current. VIN and VOUT are input and output voltages, respectively. Power dissipation due to ground current is quite small and can be ignored. Therefore, the junction temperature equation simplifies to TJ = TA + {Σ[(VIN VOUT) ILOAD] θja} (4) As shown in Equation 4, for a given ambient temperature, input-to-output voltage differential, and continuous load current, there exists a minimum copper size requirement for the PCB to ensure the junction temperature does not rise above 5 C. Figure 35 to Figure 39 show junction temperature calculations for different ambient temperatures, total power dissipation, and areas of PCB copper. In cases where the board temperature is known, the thermal characterization parameter, ΨJB, can be used to estimate the junction temperature rise. TJ is calculated from TB and PD using the formula TJ = TB + (PD ΨJB) (5) The typical ΨJB value for the 6-ball WLCSP is 43.8 C/W. Rev. H Page 4 of
Data Sheet ADP/ADP JUNCTION TEMPERATURE ( C) 45 35 5 5 5 95 85 75 65 55 5mm 45 5mm 35 mm T JMAX 5...3.4.5.6.7.8.9. TOTAL POWER DISSIPATION (W) Figure 35. Junction Temperature vs. Total Power Dissipation, TA = 5 C 757-35 JUNCTION TEMPERATURE ( C) 35 5 5 5 95 5mm 5mm mm T JMAX 85...3.4.5.6.7.8.9. TOTAL POWER DISSIPATION (W) Figure 38. Junction Temperature vs. Total Power Dissipation, TA = 85 C 757-38 JUNCTION TEMPERATURE ( C) 4 3 9 8 7 5mm 5mm 6 mm T JMAX 5...3.4.5.6.7.8.9. TOTAL POWER DISSIPATION (W) Figure 36. Junction Temperature vs. Total Power Dissipation, TA = 5 C 757-36 JUNCTION TEMPERATURE ( C) 4 8 6 4..4.6.8...4.6.8...4 TOTAL POWER DISSIPATION (W) T B = 5 C T B = 5 C T B = 65 C T B = 85 C T JMAX Figure 39. Junction Temperature vs. Total Power Dissipation and Board Temperature 757-39 45 JUNCTION TEMPERATURE ( C) 35 5 5 5 95 85 5mm 5mm 75 mm T JMAX 65...3.4.5.6.7.8.9. TOTAL POWER DISSIPATION (W) Figure 37. Junction Temperature vs. Total Power Dissipation, TA = 65 C 757-37 Rev. H Page 5 of
ADP/ADP Data Sheet PRINTED CIRCUIT BOARD (PCB) LAYOUT CONSIDERATIONS Heat dissipation from the package can be improved by increasing the amount of copper attached to the pins of the ADP/ADP. However, as shown in Table 6, a point of diminishing returns eventually is reached, beyond which an increase in the copper size does not yield significant heat dissipation benefits. Place the input capacitor as close as possible to the VIN and GND pins. Place the output capacitors as close as possible to the VOUT, VOUT, and GND pins. Use 4 or 63 size capacitors and resistors to achieve the smallest possible footprint solution on boards where area is limited. 757-4 Figure 4. Example of PCB Layout, Top Side 757-4 Figure 4. Example of PCB Layout, Bottom Side Rev. H Page 6 of
Data Sheet ADP/ADP OUTLINE DIMENSIONS..95.9 BALL A IDENTIFIER.5.45.4. REF A B.675.595.55 TOP VIEW (BALL SIDE DOWN) SIDE VIEW.38.355.33.5 BSC COPLANARITY.75.5 BSC BOTTOM VIEW (BALL SIDE UP) C SEATING PLANE.345.95.45.7.4. Figure 4. 6-Ball Wafer Level Chip Scale Package [WLCSP] (CB-6-) Dimensions show in millimeters -8--B..96.9 BALL A IDENTIFIER.5.46.4. REF A B.5 REF C.33.35.3 TOP VIEW (BALL SIDE DOWN) END VIEW.5 NOM COPLANARITY.5 NOM.5 REF BOTTOM VIEW (BALL SIDE UP) SEATING PLANE..7.4.9 NOM Figure 43. 6-Ball Bumped Bare Die Sales [BUMPED_CHIP] (CD-6-7) Dimensions show in millimeters 8-5--A Rev. H Page 7 of
ADP/ADP Data Sheet ORDERING GUIDE Model Temperature Range VOUT/VOUT Output Voltage (V) Package Description Package Option Branding ADPACBZ-8R7 4 C to +5 C./.8 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6- LFY ADPACBZ-8R7 4 C to +5 C.8/. 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6- LEK ADPACBZ-87R7 4 C to +5 C.8/.7 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6- LEH ADPACBZ-63R7 4 C to +5 C.6/.3 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6- LGD ADPACBZ-635R7 4 C to +5 C.6/.35 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6- L9L ADPACBZ-8R7 4 C to +5 C.8/. 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6- L8W ADPACBZ-88R7 4 C to +5 C.8/.8 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6- LEL ADPACBZ-87R7 4 C to +5 C.8/.7 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6- L8X ADPACBZ-88R7 4 C to +5 C.8/.8 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6- L8Y ADPACBZ7575R7 4 C to +5 C.75/.75 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6- L8Z ADPACBZ-333R7 4 C to +5 C 3./3.3 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6- LH4 ADPACBZ-R7 4 C to +5 C./. 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6- LLT ADPACBZ-55R7 4 C to +5 C.5/.5 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6- LLU ADPACBZ88-R7 4 C to +5 C.8/.8 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6- L9 ADPACBZ-88-R7 4 C to +5 C.8/.8 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6- LJ ADPACDZ-88-R7 4 C to +5 C.8/.8 6-Ball Bumped Bare Die Sales [Bump Chip] CD-6-7 LJ ADP-88-EVALZ 4 C to +5 C.8/.8.8 V/.8 V Evaluation Board ADP-88-EVALZ 4 C to +5 C.8/.8.8 V/.8 V with Output Discharge Evaluation Board Z = RoHS Compliant Part. For additional voltage options, contact a local Analog Devices sales or distribution representative. Rev. H Page 8 of
Data Sheet ADP/ADP NOTES Rev. H Page 9 of
ADP/ADP Data Sheet NOTES 8 3 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D757--/3(H) Rev. H Page of