Voltage Transient Detection and Induction for Debug and Test

Voltage Transient Detection and Induction for Debug and Test Rex Petersen, Pankaj Pant, Pablo Lopez, Aaron Barton, Jim Ignowski, Doug Josephson Intel Corporation Hudson, MA and Fort Collins, CO Abstract Voltage transients from circuit activity impact operation, testing and debug of complex designs. This paper describes a system which enables voltage transient detection and a capability to induce voltage transients in a controlled manner. Usage models and silicon results are described, along with limitations and future options for improvements. 1. Introduction The extraordinary level of integration in today s designs now allows a single chip to perform the functions that would have taken multiple separate chips in the past; this trend will continue in future generations. While these increases in size and complexity of designs are seemingly inevitable, a ramification is that it is becoming increasingly difficult to ensure that a design operates properly under a wide range of operating conditions and in different testing/functional environments. Due to this high level of integration in today s designs, voltage transients (droop and overshoot) are a common occurrence as the design operates due to changes in circuit activity. Such voltage transients may cause errors in operation if they are severe enough; it is not uncommon to see transients of 10-20+% of the supply voltage for a modern design during operation, and worse transients are possible during scan testing. Mitigation of voltage transients during functional operation, and their recreation when testing and debugging in various system and testing environments, has become increasingly important as the power density of devices has increased. 2. Overview One key issue encountered in complex, high frequency designs is droop in the power supply voltage that can make the circuit temporarily slow down and lead to erroneous computations. Since power supply droop is a transient phenomenon, and the extent and duration of the voltage excursion is dependent on a complex interaction between a number of different variables, it is very hard to isolate the cause of the voltage change. To complicate matters further, the power supply droop may be dependent upon the platform used to exercise the device (e.g. a functional system or a manufacturing tester) or the type of test being applied, making it difficult to replicate it under controlled conditions in different environments. Given the increasing impact that such voltage transients have in affecting the characterization of a design, it is essential to consider voltage transients from a DFX perspective in advanced designs. Previous work has described several possible methods for measuring power supply droop in silicon [1-4]. This paper will describe a DFX system to address the problems presented by voltage transients in advanced designs. An observation system (droop detectors) and control system (droop inducers) will be described, along with implementation details in a recent design. Usage models for each will be described, along with silicon results illustrating the usage of these systems separately and working together. A new methodology describing the use of inducers to mitigate voltage transients for testing and operation will be described. Finally, some limitations and problems discovered are discussed, along with new possible feature additions and other possible uses in the future. 3. Droop Detector System The on-die droop detection system (ODDD) is comprised of multiple detectors spread across a design to provide spatial observability. The detectors have an accuracy of 10-15mV after calibration. The detectors can be triggered [5] to measure droop over single/multiple clock cycles, or store the minimum/maximum droop and overshoot during a sample window. The detectors are fully configurable through scan and normal debug trigger response mechanisms. A recent implementation of the detectors in a microprocessor core accounted for less than 0.04% of the total area of the design, which was entirely hidden under routing channels, only using area that would have otherwise been filled up with bypass capacitors. Paper 8.2 INTERNATIONAL 1 TEST CONFERENCE 1 978-1-4244-4867-8/09/$25.00 2009 IEEE

The benefits of droop detectors include the ability to accurately measure droop events throughout a design, which opens up many new opportunities for testing and debug. The detectors can be used in any platform environment (e.g. a system or on a tester), with functional or test content. The system enables temporal and spatial isolation of voltage related failures, as well as volume collection of voltage droop data from many different parts, which has been very difficult in the past. With the ability to measure di/dt-induced voltage transients accurately, the inherent frequency of a given speedpath can be separated from the effects of droop. This focuses debug efforts toward debugging the cause of di/dt problems when they are systemically causing many electrical/speed issues. It also helps in correlation to system failures, and in steering testing and debugging toward droop-prone areas. clock domain at the pipeline latch. Diagrams of the ADC and its components are shown in Figure 2. A ripple counter topology is used in the ADC to allow for a very high speed first stage since the counter s least significant bit needs to track the maximum frequency of the VCO. However, this counter topology results in a datadependent latency for the voltage measurement due to the settling time of the ripple counter s most significant bit (higher order bits take longer to propagate). Therefore the required wait time for a valid measurement was carefully managed in designing the timing of the digital control interface and results in a pre-defined voltage/frequency range for valid operation. The detector circuit consists of 1) an analog front end that samples the voltage of the local power supply and 2) digital control logic. Figure 1 shows a block diagram of the droop detector circuit. The digital control blocks manage the interface to the analog to digital converter (ADC) block, process data from the ADC, and manage the scan-based interface to the processor. High and low watermark values are stored for longer duration measurements. CORE CLOCK High Water Latch SCAN OUT SCAN IN VDD SOF TRIGGER ADC HALT, COUNT, CLEAR Control Logic GRID ENABLE CORE CLOCK Pipeline Latch > < Low Water Latch Figure 1: Droop detector circuit block diagram The ADC consists of a 3-stage voltage controlled oscillator (VCO) that uses the local power supply grid as its control input. The VCO was designed for high frequency of operation, which translates to higher resolution in the analog to digital conversion, but it also has good linearity. The VCO produces a digital output signal with a frequency proportional to the voltage on the supply grid. The output of the ADC is generated by a counter that counts the number of cycles produced by the VCO for the duration of the measurement window. The ADC operates essentially in an asynchronous mode, with the ADC output data being synchronized into the core Figure 2: Analog to digital converter circuit diagrams Configuration of the droop detectors is done through scan. This configuration includes initial starting values for the high/low watermarks, mode selection bits, and the width of the droop detection sample window. All the detectors are designed to sample at the same time using a synchronous trigger signal that can be programmed to fire at any clock cycle. 4. Droop Detector Calibration In order to map the count values from the detectors to voltage levels, and to account for PVT variations, each detector is individually calibrated by taking measurements at three different voltages. Because the VCO has a very linear response to voltage in real silicon, it is easy to interpolate a line that represents a corresponding voltage level for each counter value for every detector. Process variation of the detectors is normalized by this calibration. Paper 8.2 INTERNATIONAL TEST CONFERENCE 2

The best calibration results are obtained when the power supply is quiet. We explored two different methods to address this. One method used a mode that stops instructions from executing while the clocks continue to run. In this case, the power supply is not stressed during calibration. The other method involved taking several detector measurements during any real testcase using a wide (30ns) window and averaging the values. With this method, any transient is averaged out. Both methods proved to be equally accurate. The first one is faster, while the second one is easier to implement. activated a slow circuit at cycle 107687, and the voltage droop in that region of the chip made the circuit operate even slower. 5. Droop Detector Usage Models There are two basic modes of operation for the droop detectors: single-shot mode, and repeat mode. In singleshot mode, one sampling window of configurable width is used. In repeat mode the window can be stepped through any given range, and the detector reports the highest and lowest readings in that period. These two modes of operation allow for several usage models: Droop on a specific clock cycle: Using single-shot mode the droop value can be captured at any given cycle. This can also be done on consecutive cycles to capture the shape of the voltage transient waveform. (See example in Figure 3). Worst droop in a test: Repeat mode quickly sweeps a long range and reports the highest/lowest values found. This can be used to identify content that is causing transients and quantify their magnitude. This can be used in a tester or system environment and is also useful for correlation between the two environments for the same test content. Binary search: Determines when in time the reported worst droop happened by using repeat mode and dividing the sample ranges in a binary search fashion. Region characterization: Maps droop profiles seen over different test content to the chip power grid (via droop detector locations) to identify blocks and regions which are more affected by supply issues. Figure 3: Reconstructed voltage waveforms from droop detector data used for speedpath debug Although speed failures are commonly seen when there are di/dt events that make them worse, there are cases that do not line up this way. The ability to quantify the amount of di/dt related droop in the region helps understand what component of the slowdown is related to droop. This example also illustrate the importance of having multiple droop detectors due to the spatial nature of di/dt events and how the effect attenuates as it moves further away from the location that created it. 7. Droop Inducer System The on-die droop inducers (ODDI) are comprised of large analog transistors that connect the supply to ground. These inducer circuits provide a way to create controlled di/dt events via programmable triggers. These devices are turned on and off in various modes to create different di/dt events that cause droop on the power supply. 6. Droop Detector Data Voltage waveforms can be reconstructed by taking detector measurements at consecutive clock cycles and plotting the results. Figure 3 shows the voltages measured at 3 detector locations during a testcase that hit a speedpath near detector #1. During this portion of the testcase there are three di/dt events occurring that create 60mV of droop at detector location #1, 40mV of droop at location #2 which is 4000μm away, and only 20mV of droop at detector #3 which is 8000μm away. One of these di/dt events lined up with a code sequence that Figure 4: The droop inducers can be configured to turn on large FETs to produce various di/dt events Paper 8.2 INTERNATIONAL TEST CONFERENCE 3

Current steps of up to 50A can be created based on triggers [5] that are synchronous with global clock edges with configurable delay. The slew rate, magnitude, location and repetition of the current steps are also controllable via scan configuration. Current Profile Modes Voltage Results (Actual Si Data) 8. Droop Inducer Usage Models Many droop inducers are spread across a design to provide the ability to create substantial di/dt events that can mimic the amount and location of di/dt that can be seen during normal functional operation. The design also allows the inducers to be independently controlled in small groups which provides a way to create localized droop and a way to determine in which section of the chip a failure is occurring. The ability to generate controlled di/dt events has many uses: Create droop at a given clock cycle to isolate a voltage related failure and make it worse to help with debug. Search for the critical cycle during a test that has the greatest effect on a voltage related failure. This is used to isolate when in time a failure is occurring. Create voltage overshoot to make high voltage issues worse, or to work around low voltage failures. Add droop into a test to match voltage transients seen when running content on different testing platforms with different power supply environments. Mitigate voltage droop by turning the inducers off at a time that will minimize the di/dt effect of other high current events such as enabling clocks. Isolate a voltage related failure to a specific region of a chip design, allowing for faster triage and debug. Power grid and package characterization. Testing and validation of the droop detectors. 9. Droop Inducer Modes of Operation A recent implementation of the droop inducer system has several current profile modes shown in Figure 5. The three modes include a step current, a square wave, and a triangular waveform created by staging on the inducers over several clock cycles. Each of these modes can be repeated to produce multiple di/dt events spaced by a configurable amount of time. The silicon data shown in Figure 5 was taken from one of the droop detector locations and shows the voltage response to each inducer di/dt event. Mode 0: Step I(t) Mode 1: Square Wave with configurable period Mode 2: Triangle Wave configurable slew rate Figure 5: Droop inducer modes with silicon data showing the resulting voltage droop and overshoot created by the inducers and measured by a detector. The inducers can be turned on in a single shot mode, producing one di/dt event that starts at a given clock cycle as shown in actual silicon measurements in Figure 6. This mode can be used to make a voltage related failure worse for isolation. It can also be used to see the effect of a droop event on any type of circuit failure or to slow down a speedpath. Paper 8.2 INTERNATIONAL TEST CONFERENCE 4

inducers via scan, the general location of the failure was also identified. This failure turned out to be a memory cell read stability issue, where the cell was getting corrupted when a different way but same index of the array was being written. At high voltage the memory cell was unable to retain a low value when fighting a bitline keeper device. Figure 6: Scope waveforms showing the effect on the voltage power grid of a single droop inducer di/dt event (top) and resonate mode waveform (bottom). The inducers can also run in a resonate mode: turning on for N cycles, off for N cycles, and repeat. This produces a sine wave on the power grid as shown on the bottom of Figure 6. This mode is useful for power grid characterization, testing the detectors, and quickly determining if a failure is sensitive to droop. Figure 7: Shmoo of a high voltage failure that the droop inducers were used to debug. 10. Using the Droop Inducers for Debug The droop inducer system has been used during the debug of several high and low voltage design problems. On an early stepping of one design, many parts showed a high voltage failure during a shmoo. The droop inducers were used to isolate the failure to a specific memory array and to determine when in time the data was getting corrupted. This was done by sweeping a di/dt event throughout the test until a cycle was found that made the failure worse. Figures 7-9 show actual silicon data containing voltage frequency shmoos of this failure with the droop inducers turning on at different cycles. (Dark red indicates a failure). Figure 7 shows the default case when the inducers are turning on at a cycle that does not affect the failure. Figure 8 shows when the voltage overshoot caused by the di/dt event is lined up with the critical failing cycle. This provided an important piece of data about that failure to know that overshoot at a specific time in the testcase made the failure worse. Figure 9 shows that the failure is much better when the droop inducers are turned on a few cycles later, which lined up the lowest voltage droop with the critical cycle. This sweep of the di/dt event provided key data in root causing and fixing the failing circuit. Also, by creating droop in different regions of the chip by selectively enabling various Figure 8: The failure is worse when a voltage overshoot event is lined up with the critical cycle Figure 9: The failure is better when the inducers create a voltage droop at the critical cycle. Paper 8.2 INTERNATIONAL TEST CONFERENCE 5

11. Determining Placement of Detectors & Inducers Droop detectors were placed in locations that were known to have the potential for large di/dt events. Remaining detectors were then placed to add visibility throughout the design. One implementation in a 65nm technology used 25 detectors in a rough 5x5 grid approximately 1500μm apart. Some data was collected to see if this was too many or too few. Several droop measurements were taken and a study was done to see how accurate a detector measurement could be derived by using neighboring measured values and interpolating. In most cases the interpolated value was within 10% of the actual measured value, but some data points showed an error of up to 20%. This means some di/dt events can cause large localized droop that would be underestimated by interpolation. The conclusion of this study was that 25 detectors was a reasonable number, and using fewer detectors and more interpolation could result in 10-20% less accuracy. The inducer circuits were each designed to draw 100mA. These were spread throughout the design about 750μm apart to avoid pulling too much current through any single package bump. One implementation used 16 groups of 8 inducers for a total of 128 per core. A key factor in the inducer design was the ability to pull a similar amount of total current that the chip could produce during a worst case di/dt event. 12. Using the Inducers and Detectors Together Silicon results shown in Figure 10 show what the voltage supply is doing when all of the droop inducers were turned on in a portion of a design using resonate mode. This data shows how each of the 25 detectors in the area responded to this droop inducer event. A curve fit has been drawn between the measurements of the detector that showed the largest voltage swing. Each of the detectors captured a similar sine shaped waveform but the variation in magnitude at different locations on this device was a high as 100mV on the voltage overshoot values. This variation between detectors further illustrates the importance of having multiple detector locations to quantify voltage differences in the power grid. 13. Measuring Detector Accuracy An oscilloscope was use to test the accuracy of the detectors. The inducers were used in resonate mode and the power grid was observed on an oscilloscope using high bandwidth, non-current carrying observation pads on the package that give visibility at the C4 bumps. The detector values were then extrapolated to those two probe point locations. The scope measured peak to peak voltage swings of 145mV and 104mV compared to 133mV and 99mV from the on-silicon detectors, a difference of 5-12mV and within the design expectation of 10-15mV of accuracy. 14. Droop System Use in Platform Correlation Tester to system miscorrelation occurs when some parts fail at a different frequency in the system than they do in the manufacturing production test at the same voltage and temperature. A computer system running applications under an operating system runs many orders of magnitude more cycles of code on the part than could possibly be run in a production test. Miscorrelation is due mainly to cases where some of the code run on systems is more electrically stressful for the processor than any of the content currently in the production test. Ideally the production test would contain content that includes the same failing mechanisms as seen on the system; however this can be a difficult and time consuming problem to port system failures to the production tester. This is where the droop system can help debug and eliminate much of this effort. Figure 10: 25 detectors measuring droop waveform The droop system enables measurement of the voltage droop in both systems and testers for comparison. Droop inducers can then be used to create additional droop on the tester cases to match the droop seen on the slowest system applications. This method can be used to reduce or eliminate the need to write custom content by decoupling the worst case droop from the functional mechanism to excite the speedpath. Paper 8.2 INTERNATIONAL TEST CONFERENCE 6

Figure 11 illustrates the decoupling of droop from the speedpath on several tester cases: on the x-axis is the voltage measured, including droop, and on the y-axis the frequency as seen on a tester. The four blue markers each represent a test case on the tester that is hitting the same speedpath as seen on systems, but at a faster frequency. The graph shows that the speed achieved by the tester cases is directly proportional to the droop seen in each one. The orange marker represents one of these four cases, originally the fastest one (testcase 4), after using the inducers to match the droop seen in systems. With the additional droop, the test slows down linearly and closely matches the frequency seen in the system. This new testcase with the inducers enabled to fire at the correct cycle can be used on a production tester to screen parts and close this correlation issue. At-speed scan testing causes a large voltage droop event coincident with the application of the capture clocks after a period of relative inactivity during which the scan chains are shifted at slow speeds. This voltage droop event brings into question the efficacy of at-speed testing [6-8]. It has also been demonstrated recently that voltage droop affects at-speed scan in a non-linear manner [6], complicating the comparison to traditional functional tests. This is illustrated in Figure 12, which plots the average maximum passing frequency (fmax) on a sample of parts for both at-speed scan and functional tests. The measurements were taken at four voltage points and both the at-speed scan test and an at-speed functional test targeted the same logic. It is clear in this case that the atspeed scan tests run faster than functional tests at higher voltages and get progressively slower as the operating voltage is reduced. In [6], the authors provide an explanation for this in terms of the voltage droop experienced by at-speed scan tests. Figure 12: Comparing at-speed scan vs. funct. tests A number of methods have been proposed to mitigate this voltage droop [9-12] including using low-activity patterns, targeting smaller sections of the design at a time and capture clocking sequences using a mixture of slow and fast clocks. However, each of these techniques has the disadvantage of longer pattern counts and increased test complexity. If it is not possible to apply any of these droop mitigation strategies, a frequency guardband has to be added as a normalizing factor when comparing the maximum passing frequency of functional and scan based at-speed content to cover the miscorrelation in voltage environments. Figure 11: Closing System Miscorrelation with Tester 15. Droop Mitigation During Scan Testing As described previously, droop inducers provide a mechanism to reduce or increase power supply droop. A unique application of this technique exists for at-speed scan based testing. However, since the occurrence of this voltage droop event is very deterministic, the droop inducer system provides an excellent way to modulate it, without requiring any constraints on the test generation process. Figure 13 shows a typical scan test event sequence. The scan chains are loaded with known values followed by a burst of atspeed capture clocks. The resultant values captured in the scan chains are then shifted out for comparison with the pre-computed expected state. As shown, the power supply experiences a large droop as the capture clocks are applied. Figure 13: Reducing supply droop during scan test Paper 8.2 INTERNATIONAL TEST CONFERENCE 7

To mitigate the effect of this droop, following the shifting of the chain, the droop inducer system is turned on. The inducers are then turned off simultaneously with the application of the capture clocks. This effectively shifts the current from the droop inducers to the circuit under test, thus eliminating the sudden change in current seen by the power delivery system. By carefully selecting the locations and number of droop inducers that are enabled, the process can be calibrated to reduce the droop to the desired extent as shown in Figure 13. Note that the droop inducers could be turned on gradually so as not to create a droop event that alters the test conditions. Figure 14 shows the original and reduced voltage droop by the application of this technique. The voltage response is shown for the case where the system clocks are turned on after a period of inactivity, during which the power supply is fully charged. As shown, the power supply droop is reduced from 14% to 10% by using the inducers. practical effectiveness of this method on the next implementation of the design and report the results. Figure 15: Droop reduction effect on frequency a) Original shmoo without inducers enabled b) Using inducers to mitigate droop increases frequency Figure 14: Measuring droop reduction The next step was to apply this technique to actual atspeed scan patterns and observe the effect on the shmoos. Figure 15 shows the before and after shmoos of a scan test, clearly demonstrating the effectiveness of the technique in reducing the power supply droop and improving the fmax of the test content. Note that the same voltage/frequency type axis was used in Figures 7-9, 15,17 with red indicating a failure and green is passing. During the course of these experiments, it was realized that the ODDI off event (Figure 13), needed to occur slightly earlier than the capture event. If the two events are coincident, there is not enough time to modulate the voltage profile before a 2-cycle scan test is over. Unfortunately, although it was feasible to prove this out via experiments, it wasn t possible to implement this offset in production test mode. As a consequence, volume correlation data against functional tests couldn t be collected. In the next design project, the ODDD/ODDI infrastructure is completely integrated with the scan test DFT, enabling full control of the number of ODDIs that participate in at-speed scan test mode, the amount of current they draw and the offset between the ODDI-off and the capture events. We plan to completely study the There can also be situations where the droop during atspeed scan testing is lower than that seen during typical functional testing. This can occur for short capture clock bursts at very high frequencies [6]. This is because the power grid is fully charged before the clocks are applied and there may not be enough time to see sufficient droop during a short clock burst. In this case, it may be desirable to actually increase the droop levels in order to get better correlation between scan and functional content, as shown below in Figure 16. In this case the droop inducers are turned on along with the capture clocks, causing the system to draw a larger instantaneous current. This results in a larger power supply droop. Again, careful calibration of the number and placement of droop inducers can create the desired droop levels during scan testing. Figure 16: Increasing supply droop during test by turning on droop inducers at the same time as the capture clocks begin toggling Paper 8.2 INTERNATIONAL TEST CONFERENCE 8

Figure 17 shows the before and after shmoos of an atspeed scan test with the ODDIs configured in this mode. As before, the modulation of the voltage profile is clearly demonstrated. Figure 17: Adding additional droop to decrease frequency a) Original shmoo without inducers enabled b) Using inducers to add droop decreases the frequency It should be noted that this technique is viable only for designs where the at-speed scan content is limited by the droop occurring due to the capture clock event, as was true in the design that these experiments were performed on. There are classes of designs where there is significant droop during the shift sequence itself leading to scan chain corruption. The proposed technology does not provide a solution for these cases, and alternative means must be explored to make the power delivery network robust enough to tolerate the scan chain shift operation. 16. Future Work The droop system described provides a high level of voltage droop observability with numerous detectors and controllability of di/dt events with multiple droop inducers across the die. These new DFX features are enabling new methodologies and new efficient ways to do debug, understand voltage droop, source voltage related failures, and select content. Silicon data shows that both features are working well and producing good data. Based on the learnings so far, there are several things that could be improved in future designs. Placing a detector right at the location of an oscilloscope observation pad would eliminate the need to extrapolate to compare and correlate the results from the internal/external measurement methods. Placement of detectors and inducers within blocks (instead of in routing channels) could provide more local detector observability, and better inducer effects, closer to critical circuits. However, this could have a higher cost for implementation. Finally, a limitation was encountered with use of the detectors during scan testing. By halting the clocks for scan, the clock to the detectors was also halted, which meant that they could not be used until clock steps began during atspeed scan tests. This limited the ability to observe the full voltage droop that occurred from initial clock steps in scan tests. This could be avoided by providing a freerunning clock to the detectors. The droop system is expected to play a broader role in additional new debug methodologies:. Package simulation model correlation to silicon This can be done by firing known inducer currents across the die, measuring the results with the detectors, and comparing this with package simulations of the same current source firing at the same points to determine the package simulation model fidelity. VBIST - Droop profiles from a system could be replayed on a tester through additional DFX; e.g., a programmable VBIST using an additional queue that could recreate a voltage profile from a system to help with platform correlation problems during test. Voltage FIBs - When a droop is seen in an area using the detectors, the inducers can be used to validate that creating a larger local droop can cause the failure to get worse, since not all voltage droops imply there will necessarily be a circuit failure. Online modulation of voltage transients. If other circuits/triggers/enable signals are provided in an integrated circuit s implementation that forecast high voltage transient events in advance (e.g. knowledge that particular piece of the design is about to draw a large amount of current, thus causing a voltage transient), the inducers can be used to ameliorate the resulting voltage transient. Monitoring voltage transients in real time during normal operation and continuously check that they are within the expected range that a device was tested for correct operation. Conclusion In summary, the droop system described has proven to be very useful in the area of measuring and controlling voltage droop and enabling many new methodologies for silicon testing and debug. The combination of both droop detectors and inducers provides ways to deal with the increasing voltage transients seen on modern day designs. Paper 8.2 INTERNATIONAL TEST CONFERENCE 9

Acknowledgements We would like thank Chris Bostak for original design ideas, Joel Grodstein for help with methodology and validation, Rob Etter and Tony Fourcroy for help with data collection, Warren Parks for power grid droop data, Kevin Zhu for data analysis, Michael Tulanowski and Rick Disney for RTL support, John Wanek and Justin Lorenz for global integration, Kevin Fagan for tools support, Rick Butler and Jerry Degroot for their work on miscorrelations, Isaac Kantorovich and Jim St. Laurent for oscilloscope measurements, Andy Allen and Doug Cutter for supporting these new features, and Adrian Carbine and Jason Stinson for helpful review and feedback. [12] B. Nadeau-Dostie, et al., Power-Aware At-Speed Scan Test Methodology for Circuits with Synchronous Clocks, International Test Conference, 2008. References [1] R. Franch, et al., On-chip Timing Uncertainty Measurements on IBM Microprocessors, International Test Conference, 2007. [2] A. Muhtaroglu, et al., On-Die Droop Detector for Analog Sensing of Power Supply Noise, IEEE Journal of Solid-State Circuits, Pg. 651-660, Vol. 39, No. 4, April 2004. [3] E. Alon, V. Stojanovic, Mark A. Horowitz,, Circuits and Techniques for High-Resolution Measurement of On- Chip Power Supply Noise, IEEE Journal of Solid-State Circuits, pp. 820-828, Vol. 40, No. 4, April 2005. [4] S. Naffziger, et al., The Implementation of a 2-Core, Multi-Threaded Itanium Family Processor, IEEE Journal of Solid-State Circuits, pp. 199-201, Vol. 41, No. 1, January 2006. [5] D. Josephson, B. Gottlieb, D. Gizopoulos (ed.), Advances in Electronic Testing: Challenges and Methodologies, Springer, 2006, ISBN 0-387-29408-2, pg. 85. [6] P. Pant, et al., Understanding Power Supply Droop During At-Speed Scan Testing, VLSI Test Symposium, 2009. [7] P. Maxwell, et al., Comparing Functional and Structural Tests, International Test Conference, 2000. [8] J. Zeng, et al., On Correlating Structural Tests with Functional Tests for Speed Binning of High Performance Design, International Test Conference, 2004. [9] S. Sde-Paz, et al., Frequency and Power Correlation between At-Speed Scan and Functional Tests, International Test Conference, 2008. [10] J. Saxena, et al., A Case Study of IR-Drop in Structured At-Speed Testing, International Test Conference, 2003. [11] H. Liu, et al., A Scan-Based Delay Test Method for Reduction of Over-testing, International Symposium on Electronic Design, Test & Applications, 2008. Paper 8.2 INTERNATIONAL TEST CONFERENCE 10