Supporting VHDL Design for Air-Conditioning Controller Using Evolutionary Computation

Proceedings of the 7th World Congress The International Federation of Automatic Control Seoul, Korea, July 6-, Supporting VHDL Design for Air-Conditioning Controller Using Evolutionary Computation Kazuyuki Kojima Keiichi Watanuki Saitama University, 55 Shimo-okubo, Sakura-ku, Saitama-shi, Saitama, JAPAN (Tel: -4-5-9576; e-mail: kojima@mech.saitama-u.ac.jp). Saitama University, 55 Shimo-okubo, Sakura-ku, Saitama-shi, Saitama, JAPAN (Tel: -4-5-4; e-mail: watanuki@mech.saitama-u.ac.jp). Abstract: In recent years, as part of the remarkable development of electronic techniques, electronic control has been applied to various systems. Many sensors and actuators have been implemented into those systems, and energy efficiency and performance have been greatly improved. However, these systems have been complicated, and much time has been required to develop system controllers. In this paper, a method of automatic controller design for those systems is described. In order to automate the design of an electronic controller, an evolutionary hardware is applied. First, the framework for applying the genetic algorithm to the automation of controller design is described. In particular, the coding of a chromosome is shown in detail. Then, how to make a fitness function is represented, with an air conditioner as an example, and the controller of the air conditioner is developed automatically using our proposed framework. Finally, an evolutionary simulation is performed to confirm our framework.. INTRODUCTION Advances in electronics have enabled highly efficient electronic parts to be built into control systems controlled more efficiently and intricately than ever. Many such systems convert analog signals from sensors to digital signals, which are processed by micro processing units (MPUs) or digital signal processors (DSPs), which determine controlled variables and/or control sequences. Digital signals are reconverted after processing into analog input to a drive circuit in order to drive actuators. When designing such a controller, a designer organically combines resources such as sensors, actuators, and an MPU that constitute a system. This can be done comparatively easily when the system is on a small scale and the signal from a sensor is used directly without any complex calculation or any estimation. For example, positioning controls and speed controls are such cases. Of course, since there is a problem of stability or response even with a small-scale system, tuning is required, and design is not easy, although compared with a large-scale system, the design of a controller is also not so difficult. The gain-regulating proportional-integral-derivative (PID) controller is an example of parameter tuning. However, considerable development work is required in a large-scale system, where complex operation must be implemented. Control of a robot s walking with obstacle avoidance is such an example. In this case, in order to develop a function, the controller designer will pay great attention to using the full resources that constitute a robot and will build the structure of a control program or a logical circuit. Systems in recent years have many components similar to that of a robot, therefore the flexibility of controller design is increasing, but the difficulty of controller design is also increasing. In home electronics and car components, many of such control systems exist. In this paper, in order to support the design of such a controller, a complex programmable logic device (CPLD) is used for the data-processing part of a controller, and very-high-speed integrated circuit hardware description language (VHDL) which describes the logical circuit in the CPLD is optimized using evolutionary computation.. COMPUTER-AIDED CONTROLLER DESIGN USING EVOLUTIONARY COMPUTATION. FPGA/CPLD/ASIC and VHDL In this paper, a programmable LSI is used for the implementation of evolutionary computation. CPLDs and FPGAs are both a sort of programmable LSI. The FPGA is SRAM-based where the scale of a logical block is comparatively small, and the CPLD is EEPROM-based where the scale of a logical block is large. The internal logic of both can be designed using HDL. The ASIC is one example of a device that can be designed using HDL in the same way as programmable LSIs. CPLDs and FPGAs can be immediately evaluated on the system for the designed logical circuit. In addition, they are flexible for the rearrangement of a specification. These merits make them suitable for the intended use in the case of a rapid prototyping. For this reason, a CPLD is used as a controller in this paper. However, the proposed framework is applicable to all devices that can be designed by HDL. 97--4-79-//$. IFAC./76-5-KR-.475

Blocks Blocks FastCONNECT Switch Matrix 7th IFAC World Congress (IFAC') Seoul, Korea, July 6-, library IEEE; use IEEE.std_logic_64.all; JTAG Port JTAG Controller In-System Programming Controller entity HALF_ADDER is port( A,B : in std_logic; S,CO : out std_logic); end HALF_ADDER; architecture DATAFLOW of HALF_ADDER is signal C, D : std_logic; begin C <= A or B; D <= A nand B; CO <= not D; S <= C and D; end DATAFLOW; A B S CO 4 /GCK /GSR /GTS 6 6 6 6 Block to Block to Block to Block 4 to Fig.. VHDL for a simple logical circuit Mutation Fig.. XC957 architecture Selection P(n) n th generation Gene Crossover n+ th generation P(n+) x: s = s s s s N Fig.. Outline of the genetic algorithm VHDL is one of the most popular HDLs, and is therefore used in this paper. The logic described by VHDL is verified and synthesized using a simulator or a logic synthesis tool so that it can be written into a device. When CPLD or FPGA serves as target devices, the programming code which determines the function of the target device can be, through a download cable, written into it in order to obtain the target LSI easily. The VHDL for a simple logical circuit is shown in Fig.. Sensor No. ( bit input ) Actuator No. ( bit output ) Actuator No. ( bit output ) Fig. 4. Example of CPLD application. Framework of controller design using evolutionary computation. Genetic algorithm The genetic algorithm used as a basis of our framework is outlined in Fig.. The decision-variable vector x of an optimization problem is expressed with the sequence of N notations s j (j=,, N) as follows: x : s = s s s s N () It is assumed that the symbol string s is a chromosome consisting of N loci. s j is a gene in the jth locus and value s j is an allelomorph. The value is assumed to be a real number, a mere notation, and so on of a group of integers or a certain range of observations as an allelomorph. The population consists of K individuals expressed with Eq. (). The population p(n) in generation n changes to the population p(n + ) in the next generation n + through the reproduction of a gene. If reproduction in a generation is repeated, and if the individual who expresses solution x nearer to an optimum value is chosen with high probability, then the value increases and an optimum solution is obtained as detailed in references [, ]. The study that optimizes a rewritable logical-circuit IC like the CPLD using a genetic algorithm has been applied in recent years. The framework which changes the internal configuration of logical-circuit IC so as to achieve its intended purpose in an evolutionary fashion is called evolvable hardware (EHW). Using this framework, a designer has only to define the criteria which evaluates a controller. In this paper, the framework of a controller design using EHW is explained with XC957[] as a test device. Internal blocks of XC957 are shown in Fig.. XC957 is a small CPLD that has 44 pins (4 user input-outputs), 7 macro cells, and the 6 usable gates. The designer chooses input and output signals from 4 user s, and defines the pin assignments. Each signal is configured to each. In the case that a CPLD is used in a control system, sensors and actuators can be associated to the pins of the CPLD. An example of association is shown in Fig. 4. In this example, pins are associated to one sensor and two actuators. The sensor value is inputted into the CPLD as an -bit digital signal, and two -bit digital signals are outputted as reference signals to two actuators. 9

7th IFAC World Congress (IFAC') Seoul, Korea, July 6-, The VHDL, which describes the internal logic of the CPLD, is encoded on a chromosome. An example of generated VHDL is shown in Fig. 5. This example serves as a description corresponding to Fig. 4. This VHDL consists of three declaration parts: (a) entity declaration part, (b) signal declaration part, and (c) architecture declaration part. The signals of the CPLD are defined on part (a). The internal signals of the CPLD are defined on part (b). As for a description of signals in VHDL, the std logic type and the std logic vector type are mainly used. The std logic type can be used when dealing with a signal alone, and the std logic vector type can be used when dealing with some signals collectively. It is better to use the std logic type and the std logic vector type considering maintenance and readability. However, when applying to our framework, the std logic type is better to use. If two or more types are used to describe signals, the VHDL decode process from the chromosome is complicated and searching space becomes wider. A VHDL description which uses a std logic vector type can be replaced by a VHDL description which uses two or more std logic types. The description can be restored if all input, output and internal signals are used as the same std logic type and only the number will be encoded on the chromosome. Then, the number of input signals, the number of output signals, and the number of internal signals are encoded on the head of the chromosome as shown in Fig. 6. In the case of Fig. 4, an input signal is set up with bits and an output signal with 6 bits. A chromosome which represents the VHDL statement of substitution indicated by Fig. 5(d) is shown in Fig. 7. The chromosome structure corresponding to a process statement is shown in Fig.. The value currently described in the figure is equivalent to the process statement in which S and DI are enumerated at the sensitivity list (Fig. 5(e)). A description of this VHDL has an if-statement in the inside of a process statement, and the description has two nesting levels. The hierarchy of the list structure is deep compared with the assignment statement indicated by line (d) in Fig. 5. As the gene of a multi-list structure is prepared, it would be possible to represent various VHDL expressions..4 Variable length chromosome and genetic operations The structure of the chromosome changes according to the design specification of the control system. The number of internal signals can be set up arbitrarily, and various descriptions in VHDL are expressed with different length of locus. The length of the chromosome is determined by the line count of VHDL. In addition, the length is determined by the number of internal signals enumerated on the sensitivity list or the length of the right-hand side of an assignment statement. When dealing with such a variable length chromosome, the problem is that the genetic operations will generate conflict on the chromosome. In order to avoid this problem, the following restrictions are observed. () With a top layer, the length of the chromosome is equal to the number of internal signals plus the number of output signals plus one. () All the signals are encoded on the chromosome using a reference number. library IEEE; use IEEE.std_logic_64.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; entity GA_VHDL is port( DI : in std_logic; DI : in std_logic; DI in std_logic; DI : in std_logic; DI4 : in std_logic; DI5 in std_logic; DI6 : in std_logic; DI7 : in std_logic; DO out std_logic; DO : out std_logic; DO : out std_logic; DO out std_logic; DO4 : out std_logic; DO5 : out std_logic; DO6 out std_logic; DO7 : out std_logic; DO : out std_logic; DO9 out std_logic; DO : out std_logic; DO : out std_logic; DO out std_logic; DO : out std_logic; DO4 : out std_logic; DO5 : out std_logic ); end GA_VHDL; architecture Behavioral of GA_VHDL is begin signal S std_logic; signal S : std_logic; S <= (((((not DI7 nand DI4) nor not DI5) or DI) and not DI7) nand not DI); S <= ((((not DI7 nor not DI7) nor DI4) or not DI) or DI); process(s, DI) begin if(s'event and S='')then DO <= (DI nand not S); DO <= not DI; process(s) begin DO <= S; DO <= (((((not DI6 and not DI) nand not DI) nand not DI) or not DI6) or DI5); DO4 <= ((((DI and not DI) nand DI6) and DI) nor not DI); process(di, S) begin DO5 <= (S nand DI); DO6 <= (((not DI and not DI) nor DI) and DI6); process(s, DI) begin if(s'event and S='')then DO7<=DI; DO <= ((((((((S or DI) and not DI6) or not DI) nand not DI) and not DI) nor DI) nand not DI) or DI); DO9 <= (((((not DI nand not DI) nor DI6) nand DI) nor not DI) and S); process(di4) begin DO <= not DI4; process(s) begin if(s'event and S='')then DO<=S; process(di, DI) begin if(di='')then DO<=(DI nand not DI); process(di5) begin DO <= DI5; DO4 <= ((((((((not S nand not DI) nand not DI6) or DI5) nand S) nand S) or not S) or DI5) nand DI7); DO5 <= ((((((((not DI nor not DI) or not DI7) nor not DI) nand not DI) or DI5) and not DI7) nor not DI7) nand not DI); end Behavioral; (a) Entity declaration (b) Signal declaration Fig. 5. Automatically generated VHDL (e) Process statement (c) Architecture body (d) Substitution () The signal with a large reference number is described by only the signal whose reference number is smaller than the signal. (4) The top layer of the chromosome describes the entity declaration part using all internal signals and output signals in order with a low reference number. Each signal can be used only once. (5) The crossover is operated on the top layer of the chromosome. These restrictions help avoid the conflict produced by genetic operations. Here, an example is given. Fig. 9 shows chromosomes of two different lengths. The length of the chromosome is determined at the initialization and it is changed by genetic operations. The length of a chromosome equals one plus the number of internal signals plus the number of output signals. The number of inputs and the number of outputs are determined by the specification of hardware. In Fig. 9, the number of inputs is determined as and the number of outputs is determined as 6. They are determined by the designer. They do not change in evolutionary calculation. The number of internal signals is determined randomly at the initialization. In Fig. 9, they are determined to be 5 and. A reference table is made

ID Blocks 7th IFAC World Congress (IFAC') Seoul, Korea, July 6-, (A) 5 6 (A ) 5 6 st locus Number of inputs Number of outputs 6 Number of signals Fig. 6. Signal definition on the first locus Architecture body Left term st Right term Right terms n th locus ID (B) 6 (B ) 6 Command ID ID_CMD_SUBSTITUTION 9 not 7 not Operator 7 ID_OP_NOR Fig. 7. Substitution Architecture body Fig.. Crossover Sensitivity list n th locus ID Process body Command ID ID_CMD_PROCESS_SENSITIVITY [] [] ID Substitution Command ID ID_CMD_PS_IFTHENELSE Event Edge Left term st Right term Right terms ( bit input ) motor ( bit output ) Mixture door ( bit output ) not not Operator ID_OP_NAND Fig.. If-then-else statement in process body Reference table (A) Signal name VHDL variable Input No. DI Input No. DI (A) Input No. DI Input No.4 DI 4 Input No.5 DI4 5 6 5 Input No.6 DI5 6 Input No.7 DI6 7 Input No. DI7 Signal No. S 9 Signal No. S Genes for internal signals 5 Signal No. S Signal No.4 S st locus Number of inputs Signal No.5 S4 Output No. DO 4 Output No. DO 5 Output No. DO Number of outputs 6 Output No.4 DO 6 7 Output No.5 DO4 Initialized number Output No.6 DO5 9 Output No.7 DO6 Output No. Number of signals DO7 5 Output No.9 DO Output No. DO9 Output No. DO 4 Output No. DO 5 Output No. DO 6 Output No.4 DO 7 Output No.5 DO4 Output No.6 DO5 Reference table (B) (B) Signal name VHDL variable Input No. DI 6 Input No. DI Input No. DI Input No.4 DI 4 Input No.5 DI4 5 Input No.6 DI5 6 Input No.7 DI6 Genes for internal signals 7 Input No. DI7 Signal No. S st locus Number of inputs 9 Signal No. S Output No. DO Output No. DO Output No. DO Number of outputs 6 Initialized number Output No.4 DO 4 Output No.5 DO4 5 Output No.6 DO5 6 Output No.7 DO6 Number of signals 7 Output No. DO7 Output No.9 DO 9 Output No. DO9 Output No. DO Output No. DO Output No. DO Output No.4 DO 4 Output No.5 DO4 5 Output No.6 DO5 Fig. 9. Two different length chromosomes Fig.. CPLD application to air conditioning according to the number of signals. If the number of signals differs, the size of the table also differs. An example of crossover is shown in Fig.. The back of the 6th gene is chosen in this example. (A) and chromosome (B) cross and change to chromosome (A ) and chromosome (B ). Only the gene before and behind the crossover point of each chromosome shows the gene of a lower layer. In the figure, chromosome (A) has two sensitivity lists and chromosome (B) has two assignment statements. The structure of a chromosome changes by replacing the gene from the back of a top gene to before a crossover point. Both chromosome (A ) and chromosome (B) came to have an assignment statement and a sensitivity list.. APPLICATION TO AIR CONDITIONING. Air-conditioning controller using evolutionary computation In the sample application of Fig. 4, if the -bit input is set to Predicted Mean Vote ()[4] in a cabin, and two -bit outputs are set to two actuators of the air conditioner, the controller can be used as an air-conditioning controller (Fig. ). In this paper,

Temperature [C] / Mix-door Temperature [C] / Mix-door Temperature [C] / Mix-door 7th IFAC World Congress (IFAC') Seoul, Korea, July 6-, evolutionary computation application to air conditioning is shown. An air-conditioning controller will be employed to keep the inside of a cabin comfortable with the internal and external thermal state. However, when developing the controller of such an air-conditioning system, the designer has to consider many sensors and actuators which constitute an air-conditioning system. The room temperature, water temperature, outdoor temperature, and solar radiation must be measured, and a controller has to control many actuators, such as a blower, an air mix door, and a mode change door. In such a case, since many parameters must be taken into consideration, trial and error of the system developments must be repeated many times. Great effort is required. So in this paper, evolutionary computation is applied to designing the controller in order to reduce such trial and error. The schematic diagrams of an air-conditioning system are shown in Fig.. Air is taken from the inlet by a blower. All the air that flows in is cooled by 5 degrees. They are dehumidified at this time. Then, a part of the air is warmed by a heater to degrees. The opening of a mix door is changed to adjust the mixing ratio of the warm air and the cold air. The input to a controller is as follows.. Predicted mean vote () is the predicted mean vote of a large population of people exposed to a certain environment. represents the thermal comfort condition on a scale from - to, derived from the physics of heat transfer combined with an empirical fit to sensation. Thermal sensation is matched as follows: + is hot. + is warm. + is slightly warm. is neutral. - is slightly cool. - is cool. - is cold. Fanger derived his comfort equation from an extensive survey of the literature on experiments on thermal comfort[4]. This equation contains terms that relate to clothing insulation I cl [clo], metabolic heat production M[W/m ], external work W [W/m ], air temperature T a [ C], mean radiant temperature T r [ C], relative air speed v[m/s], and vapor pressure of water vapor P [hpa]. [ = {. exp(.6m) +.} (M W ).5{5.7.7(M W ) P }.4{(M W ) 5.}.7M(5.7 P ).96 f cl {(T cl + 7.5) 4 (T mrt + 7.5) 4 } ] f cl h c (T cl T a ) () f cl is the ratio of clothed and nude surface areas given by: f cl =. +.I cl (I cl.5) f cl =.5 +.I cl (I cl >.5) () where T cl is the clothing surface temperature given by repeated calculation of: T cl = 5.7.(M W ) Outdoor Air temperature Humidity 5% Refrigerator 5 m /h max. 5 Heater Air mixture door Full cool % Full hot % Fig.. Air-conditioning system - - - - - - - - - 6 6 6 5 5 5 5 5 5 5 5 5 generations generations generations Cabin 6 6 6 Q...6.4.....6.4.....6.4.. Mix door 6 Mix door 6 Mix door 6 Fig.. Simulation results [.55I cl.96 f cl {(T cl + 7.5) 4 ] (T mrt + 7.5) 4 } + f cl h c (T cl T a ) where h c is the heat transfer coefficient, (4) h c = max{.(t cl T a ).5,. v} (5) and T mrt is mean radiant temperature. is detailed in [4].. Fitness function The fitness function is as follows, where E is the difference between target and estimated, t is time, T end is the end of calculation time. fitness = T end Edt (6) The value will become high if it is a minimum of the integrated value. In the simulation, a variation of a heat load is given as a disturbance. The load is given randomly between W and W. The load is changed two times in one fitness calculation; the timing of load switching is also given randomly. The fitness values of chromosomes are different from each other, even if the chromosomes are exactly the same. However, the logic generated in this way has high robustness to a disturbance.

Fitness / Mixdoor / Mixdoor / Mixdoor Heat [W] Heat [W] Heat [W] 7th IFAC World Congress (IFAC') Seoul, Korea, July 6-, - - - 6 9 5 6 4..6.4. 6 9 5 6 9 5 - - - 6 9 5 6 4..6.4. Fig. 4. Simulation results -5 - -5 - -5-6 9 5 6 9 5 - - - 6 4..6.4. -5 Generation Fig. 5. Ten elite values in each generation.4 Simulation results 6 9 5 6 9 5 6 9 5 Figures, 4, and 5 shows the simulation results. In this case, in a front cabin is fed back to the controller. In this calculation, the population size is 5, crossover rate is., mutation rate is.5, selection method is tournament, and tournament size is. In all graphs, a tendency changes every 6 seconds and changes at seconds. These variations are based on the load change. At the time of zero generation shown in Fig. (a), with a change of a heat load, the temperature rises or descends. also changes simultaneously. This means that the optimization of a controller is inadequate. After generations of calculation, the difference between the target value and the estimated value decreases (Fig. (b)). At the th generation as shown in Fig. (c), the tolerance decreases further. These results show that the hardware corresponding to the purpose can be obtained automatically by using this framework. Figure 4 shows the air-conditioning control under different heat loads. In order to correspond to an alternation of a disturbance and to minimize, the rotation of the blower and the opening of the air mixture door are controlled. Figure 5 shows ten fitness values in each generation. These values are the results of calculating the fitness value of each generation s elite times. Since the fitness value has given the thermal load at random as mentioned above, a value which is different whenever calculated is shown, but variation becomes small as a generation progresses. However, a possibility that the optimal solution from which evolution calculation is obtained is a partial solution is pointed out. Also in the framework which we propose, the obtained optimal solution may be a partial solution. This is considered as a future subject. Here, the calculation result up to generations was shown. However, in the case of this example simulation, about generations are enough. The slope of afitness value and the error of the maximum fitness values are consulted when deciding the end generation of calculation. 4. CONCLUSION In this paper, in order to support the design of a controller of a mechatronics system, a CPLD used for the data-processing section of the controller and VHDL which describes the logical circuit were optimized using evolutionary computation. First, the framework of how to apply the evolutionary computation to the automation of controller design was described. In particular, the coding of a chromosome was shown in detail. Then, how to constuct a fitness function was illuminated with an air conditioner as an example case, and the controller of the air conditioner was developed automatically using our proposed framework. Finally, an evolutionary simulation was performed to confirm our framework. REFERENCES [] D. E. Goldberg, Genetic Algorithm in Search, Optimization and Machine Learning, Addison-Wesley, 99. [] N. Sannomiya et al., Genetic Algorithm and Optimization, Asakura Publishing Co., Ltd., pp., 99. (in Japanese) [] Xilinx, XC957 In-System Programmable CPLD Product Specification, Xilinx, pp., 99. [4] P. O. Fanger, Thermal Comfort, McGraw-Hill, 97. [5] J. Koza, Genetic Programming, MIT Press, 994. [6] H. Iba, Genetic Programming, Tokyo Denki University Press, 996. (in Japanese) [7] H. Iba, Introduction to Genetic Programming, University of Tokyo Press, pp. 77,. (in Japanese) [] T. Higuchi et al., Evolvable Hardware with Genetic Learning: A First Step Towards Building a Darwin Machine, Proceedings of the nd International Conference on the Simulation of Adaptive Behavior, MIT Press, pp. 47, 99. (in Japanese) [9] H. Hemmi, J. Mizoguchi and K. Shimohara, AdAM: A Hardware Evolutionary System, Proc. 997 IEEE Conf. Evolutionary Computat.(ICEC 97), pp. 9-96, 997. [] I. Kajitani and T. Higuchi, Developments of Myoelectric Controllers for Hand Prostheses, Proc. of the Myoelectric Controls Symposium 5, pp. 7-, 5. [] H. Sakanash, M. Iwata and T. Higuchi, Evolvable Hardware for Lossless Compression of Very High Resolution Bi-level Images, IEEE Proceedings-Computers and Digital Techniques, Vol.5, No.4, pp.77-6, 4.