EVIEW TANSISTO BIAS CICUIT
OBJECTIVES Discuss the concept of dc biasing of a transistor for linear operation Analyze voltage-divider bias, base bias, and collectorfeedback bias circuits. Basic troubleshooting for transistor bias circuits.
LECTUE S OUTLINE Objectives Introduction DC operating point Voltage-divider bias Other bias methods Base bias Emitter bias Collector-feedback bias Troubleshooting Summary
INTODUCTION The term biasing is used for application of dc voltages to establish a fixed level of current and voltage. Transistor must be properly biased with dc voltage to operate as a linear amplifier. If amplifier is not biased with correct dc voltages on input and output, it can go into saturation or cutoff when the input signal applied. There are several methods to establish DC operating point. We will discuss some of the methods used for biasing transistors.
DC OPEATING POINT
THE DC OPEATING POINT The goal of amplification in most cases is to increase the amplitude of an ac signal without altering it. Improper biasing can cause distortion in the output signal.
THE DC OPEATING POINT The purpose of biasing a circuit is to establish a proper stable dc operating point (Q-point). The dc operating point between saturation and cutoff is called the Q-point. The goal is to set the Q-point such that it does not go into saturation or cutoff when an ac signal is applied.
Q-point of a circuit: dc operating point of amplifier specified by voltage and current values (V CE and I C ). These values are called the coordinates of Q-point. efer to figure a, given I B = 200μA and β DC =100.. I C = β DC I B so I C = 20mA and VCE VCC IC C 10V (20mA)(220) 10 4.4 5. 6V Figure b, V BB is increased to produce I B of 300μA and I C of 30mA. VCE VCC IC C 10V (30mA)(220) 10 6.6 3. 4V Figure c, V BB is increased to produce I B of 400μA and I C =40mA. So, V CE is: VCE VCC IC C 10V (40mA)(220) 10 8.8 1. 2V
DC OPEATING POINT DC LOAD LINE When IB increases, IC increases and VCE decreases or vice-versa. Each separate Q-point is connected through dc load line. At any point along line, values of IB, IC and VCE can be picked off the graph. Dc load line intersect VCE axis at 10V, where VCE=VCC. This is cutoff point because IB and IC zero. Dc load line also intersect IC axis at 45.5mA ideally. This is saturation point because IC is max and VCE=0.
DC OPEATING POINT LINEA OPEATION egion between saturation and cutoff is linear region of transistor s operation. The output voltage is ideally linear reproduction of input if transistor is operated in linear region. Let s look at the effect a superimposed ac voltage has on the circuit. IB vary sinusoidally 100μA above and below Q-point of 300μA. IC vary up and down 10mA of its Q-point(30mA). VCE varies 2.2V above and below its Q-point of 3.4V. However, as you might already know, applying too much ac voltage to the base would result in driving the collector current into saturation or cutoff resulting in a distorted or clipped waveform. When +ve peak is limited, transistor is in cutoff. When ve peak is limited, transistor is in saturation.
Variations in IC and VCE as a result of variation in IB.
Transistor being driven into SATUATION Q-point is too close to saturation for the given input signal Transistor being driven into CUTOFF Q-point is too close to cutoff for the given input signal Graphical load line illustration of transistor being driven into saturation or cutoff
Transistor being driven into both SATUATION and CUTOFF input signal is too large Graphical load line for transistor in saturation and cutoff
Example 1 Determine Q-point in figure below and find the maximum peak value of base current for linear operation. Assume β DC =200.
VOLTAGE-DIVIDE BIAS
VOLTAGE-DIVIDE BIAS Voltage-divider bias is the most widely used type of bias circuit. Only one power supply is needed and voltagedivider bias is more stable( β independent) than other bias types. For this reason it will be the primary focus for study. Dc bias voltage at base of transistor is developed by a resistive voltagedivider consists of 1 and 2. Vcc is dc collector supply voltage. 2 current path between point A and ground: i. through 2 ii. through BE junction and E.
VOLTAGE-DIVIDE BIAS If I B is much smaller than I 2, bias circuit is viewed as voltage divider of 1 and 2 as shown in Figure a. If I B is not small enough to be neglected, dc input resistance IN(base) must be considered. IN(base) is in parallel with 2 as shown in figure b.
INPUT ESISTANCE AT TANSISTO BASE V IN is between base and ground and I IN is the current into base. By Ohm s Law, IN(base) = V IN / I IN Apply KVL, Assume V IN = V BE + I E E V BE <<I E E, so V IN I E E Since I E I C = β DC I B, V IN β DC I B E I IN = I B, so IN(base) = β DC I B E / I B IN(base) = DC E
ANALYSIS OF VOLTAGE-DIVIDE BIAS CICUIT
ANALYSIS OF VOLTAGE-DIVIDE BIAS CICUIT Total resistance from base to ground is: 2 2 IN( base) DC A voltage divider is formed by 1 and resistance from base to ground in parallel with 2. V B 1 2 2 DC If DC E >> 2, (at least ten times greater), then the formula simplifies to 2 VB V CC 1 2 DC E E E V CC
ANALYSIS OF VOLTAGE-DIVIDE BIAS CICUIT Now, determine emitter voltage V E. V E = V B V BE Using Ohm s Law, find emitter current I E. I E = V E / E All the other circuit values I C I E V C = V CC I C C To find V CE, apply KVL: V CC I C C I E E V CE =0 Since I C I E, V CE V CC I C ( C + E )
Example 2 Determine VCE and IC in voltage-divider biased transistor circuit below if βdc = 100.
THEVENIN S THEOEM APPLIED TO VOLTAGE- DIVIDE BIAS FO NPN TANSISTO (a) an equivalent base emitter circuit for the circuit using Thevenin s theorem (b) Looking out from the base terminal, the bias circuit can be redrawn (c) The Thevenin equivalent of the bias circuit, connected to the transistor base
ANALYSIS OF VOLTAGE BIAS FO NPN TANSISTO efer to slide 27 (c) Thevenin s voltage V 2 TH V CC 1 2 Thevenin s resistance TH 1 1 2 2 By KVL around BE loop, V TH V TH V BE V E 0 I C DC I B I C I E
ANALYSIS OF VOLTAGE BIAS FO NPN TANSISTO Thus, I B V TH TH V DC BE E I E E V TH V BE ( TH / DC )
THEVENIN S THEOEM APPLIED TO VOLTAGE- DIVIDE BIAS FO PNP TANSISTO Pnp transistor has opposite polarities from npn. To obtain pnp, required negative collector supply voltage or with a positive emitter supply voltage. The analysis of pnp is basically the same as npn.
ANALYSIS OF VOLTAGE BIAS FO PNP TANSISTO Base voltage Emitter voltage By Ohm s Law, And, EE E DC B V V 2 1 1 BE B E V V V E E EE E V V I C E EC C C C V V V I V
ANALYSIS OF VOLTAGE BIAS FO PNP TANSISTO efer to slide 30(a) Thevenin s voltage Thevenin s resistance V By KVL around BE loop, 2 TH V CC 1 2 V TH TH V 1 1 E 2 2 V EB V TH 0 I C DC I B I C I E
ANALYSIS OF VOLTAGE BIAS FO PNP TANSISTO Thus, I B V TH TH V DC EB E I E E V TH V EB ( TH / DC )
ANALYSIS OF VOLTAGE BIAS FO PNP TANSISTO efer to slide 30, (b) Thevenin s voltage Thevenin s resistance By KVL around BE loop, V TH V TH = V EE TH V I C E 1 1 + 2 1 1 2 V DC I C I E V EE 2 EB I B V TH 0
ANALYSIS OF VOLTAGE BIAS FO PNP TANSISTO Thus, I B V EE TH V TH V DC EB E I E V EE E V TH V EB ( TH / DC )
Example 3 Find IC and VEC for the pnp transistor circuit in Figure below
OTHE BIAS METHODS BASE BIAS EMITTE BIAS COLLECTO-FEEDBACK BIAS
BASE BIAS KVL apply on base circuit. V CC V B V BE = 0 or V CC I B B V BE =0 Solving for I B, Then, apply KVL around collector circuit. V CC I C C V CE = 0 CC We know that I C = β DC I B, I B V V B BE I C DC V CC V B BE
BASE BIAS From the equation of I C, note that I C is dependent on DC. When DC vary, V CE also vary, thus changing Q-point of transistor. This type of circuit is beta-dependent and very unstable. ecall that DC changes with temperature and collector current. Base biasing circuits are mainly limited to switching applications.
EMITTE BIAS Npn transistor with emitter bias
EMITTE BIAS This type of circuit is independent of DC making it as stable as the voltage-divider type. The drawback is that it requires two power supplies. Apply KVL and Ohm s Law, I B B + I E E + V BE = -V EE Since I C I E and I C = DC I B, Solve for I E or I C, I C Voltage equations for emitter base circuit. V E = V EE + I E E V B = V E + V BE V C = V CC I C C V E I EE B V B BE / I DC E DC
COLLECTO-FEEDBACK BIAS Collector-feedback bias is kept stable with negative feedback, although it is not as stable as voltage-divider or emitter. With increases of I C, V C decrease and causing decrease in voltage across B, thus I B also decrease. With less I B, I C go down as well.
COLLECTO-FEEDBACK BIAS By Ohm s Law, Collector voltage with assumption I C >> I B. V C = V CC I C C And I B = I C / DC So, collector current equation I C Since emitter is ground, V CE = V C. V CE = V CC - I C C I B V C V C CC V B B V BE BE / DC
TOUBLESHOOTING
TOUBLESHOOTING Figure below show a typical voltage divider circuit with correct voltage readings. Knowing these voltages is a requirement before logical troubleshooting can be applied. We will discuss some of the faults and symptoms.
ALL INDICATED FAULTS
TOUBLESHOOTING Fault 1: 1 Open With no bias the transistor is in cutoff. Base voltage goes down to 0 V. Collector voltage goes up to10 V(V CC ). Emitter voltage goes down to 0 V. Fault 2: esistor E Open Transistor is in cutoff. Base reading voltage will stay approximately the same. Since IC=0, collector voltage goes up to 10 V(V CC ). Emitter voltage will be approximately the base voltage - 0.7 V.
TOUBLESHOOTING Fault 3: Base lead internally open Transistor is nonconducting (cutoff), I C =0A. Base voltage stays approximately the same, 3.2V. Collector voltage goes up to 10 V(V CC ). Emitter voltage goes down to 0 V because no emitter current through E. Fault 4: BE junction open Transistor is in cutoff. Base voltage stays approximately the same,3.2v. Collector voltage goes up to 10 V(V CC ) Emitter voltage goes down to 0 V since no emitter current through E.
TOUBLESHOOTING Fault 5: BC junction open Base voltage goes down to 1.11 V because of more base current flow through emitter. Collector voltage goes up to 10 V(V CC ). Emitter voltage will drop to 0.41 V because of small current flow from forward-biased base-emitter junction.
Fault 6: C open TOUBLESHOOTING Base voltage goes down to 1.11 V because of more current flow through the emitter. Collector voltage will drop to 0.41 V because of current flow from forward-biased collectorbase junction. Emitter voltage will drop to 0.41 V because of small current flow from forward-biased base-emitter junction.
Fault 7: 2 open TOUBLESHOOTING Transistor pushed close to or into saturation. Base voltage goes up slightly to 3.83V because of increased bias. Emitter voltage goes up to 3.13V because of increased current. Collector voltage goes down because of increased conduction of transistor.
SUMMAY
SUMMAY The purpose of biasing is to establish a stable operating point (Q-point). The Q-point is the best point for operation of a transistor for a given collector current. The DC load line helps to establish the Q-point for a given collector current. The linear region of a transistor is the region of operation within saturation and cutoff.
SUMMAY Voltage-divider bias is most widely used because it is stable and uses only one voltage supply. Base bias is very unstable because it is β dependent. Emitter bias is stable but require two voltage supplies. Collector-feedback is relatively stable when compared to base bias, but not as stable as voltage-divider bias.