590 Desig of a Mixed Prime Factor FFT for Portable Digital Radio Modiale Receiver Dog-Su Kim, Member, IEEE, Sag-Seol Lee, Jae-Yeo Sog, Kyu-Yeul Wag, ad Duck-Ji Chug Abstract To achieve better soud quality ad to improve data receptio, digital radio modiale (DRM) offers a worldwide iitiative to brig aalog amplitude modulatio (AM) radio ito the digital era. DRM systems use coded orthogoal frequecy divisio multiplexig (COFDM) modulatio with a multilevel codig scheme to get high resistace to the multipath paddig ad iterferece. The badwidth of a DRM passbad sigal is less tha 20 khz ad the umber of carriers used i orthogoal frequecy divisio multiplexig (OFDM) modulatio is relatively small. For this reaso, DRM systems use o-power-of-two Fast Fourier Trasforms (FFT) for OFDM demodulatio, such processig gives way to more speed ad power cosumptio i critical paths i DRM receivers. I this paper, we propose a mixed radix-2 ad prime factor FFT algorithm for portable DRM receivers. Usig the proposed architecture, we ca reduce the processig time ad eergy cosumptio compared to covetioal digital sigal processor (DSP) based DRM receivers. Idex Terms Digital radio modiale, prime factor fast fourier trasform, orthogoal frequecy divisio multiplexig. I. INTRODUCTION With the developmet of multimedia techology, the desire for high quality audio ad video services has rapidly icreased. May researchers have met these eeds [], [2], ad several uiversal stadards have bee proposed [3], [4]. The digital radio modiale (DRM) is a digital broadcastig system for log, medium, ad short-wave bads for the radio frequecies below 30 MHz. DRM has bee stadardized by the Europea Telecommuicatio Stadards Istitute as ETSI ES 20 980 [4]. A DRM system uses existig amplitude modulatio (AM) broadcast frequecy bads ad it is desiged to fit i with a 9 khz or 0 khz badwidth. Additioally, four trasmissio modes ad differet system badwidths have bee defied to permit broadcastig with variable chaelizatio costraits ad propagatio coditios. Besides the omial badwidths of 9/0 khz, the system also supports also half chael modes (4.5 ad 5 khz) to allow for simulcast with aalog AM as well as double chael modes (8 ad 20 khz) where desig costraits allow for such facility resultig i larger capacity. The trade-off betwee capacity ad ruggedess to oise, multipath spread ad Dog-Su Kim is with the Departmet of Advaced Mobile Techology Research Ceter, Korea Electroics Techology Istitute, Gyeoggi-do, Seogam-si, Korea (e-mail: dskim@ keti.re.kr). Sag-Seol Lee, Jae-Yeo Sog, Kyu-Yeul Wag, ad Duck-Ji Chug are with the Iformatio Techology ad Telecommuicatios, INHA Uiversity, Icheo, Korea. Cotributed Paper Mauscript received October 0, 2008 0098 3063/08/$20.00 2008 IEEE Fig.. Digital broadcastig system usig DRM receivers Doppler spread ca be defied by the costellatio, code rate ad the orthogoal frequecy divisio multiplexig (OFDM) mode. Cosiderig all the parameters, a typical data rate i the 9kHz or 0 khz chaels is betwee 20 24 kbit/s, the maximum data rate i a 20 khz chael is 72 kbit/s [], [5]. As show i Fig., DRM provides the opportuity to deliver a ew rage of both audio ad data services usig existig ad ew trasmissio ifrastructure i curret AM frequecy allocatios. The DRM system uses coded orthogoal frequecy divisio multiplex (COFDM) for digital broadcastig over AM bads. All the data produced from the digitally ecoded audio ad associated data sigals are shared for trasmissio across a large umber of closely spaced carriers. All of these carriers are cotaied withi a allotted trasmissio chael ad time iterleavig is applied i order to mitigate fadig. DRM system parameters are selected to allow trasmissio to be desiged to fid the best combiatio of trasmit power, robustess, ad data capacity [5]. Most of the computatio power is used i the COFDM demodulatio to compute Fast Fourier Trasforms (FFT) ad Iverse Fast Fourier Trasforms (IFFT) o complex samples. Because the badwidth of a DRM passbad sigal is less tha 20 khz ad the umber of carriers used i the OFDM modulatio is relatively small, FFT for OFDM demodulatio has to be performed o o-power-of-two umbers of samples, which is rare i the sigal processig field [6], [7]. DRM systems use 4 differet modes ad each mode has differet FFT size as show i Table I. A FFT the size of mode B ca be replaced by a power-of-two FFT ad the other modes eed opower-of-two FFT. For the implemetatio of FFT algorithms, commo factor algorithms ad prime factor algorithms are commoly used. These algorithms are distiguished by the scheme i which two iput sequeces are decomposed. The radix-2 FFT algorithm takes two data poits cocurretly from
D.-S. Kim et al.: Desig of a Mixed Prime Factor FFT for Portable Digital Radio Modiale Receiver 59 memory ad performs butterfly computatios. This procedure is repeated N log 2 N/2 times i a N-poit Discrete Fast Fourier Trasform (DFT). Butterfly computatios require twiddle factors at various stages i either atural or bit-reversed order. I this paper, we propose a ew FFT architecture that combies prime factor FFT with modified radix-2 FFT i order to reduce processig time ad eergy cosumptio. The proposed hybrid prime factor FFT architecture uses two-dimesioal idex mappig ad a reusig techique to reduce the complexity of the multiplier ad twiddle factor. The rest of this paper is orgaized as follows. Sectio II explais the hybrid prime factor FFT for DRM systems. Implemetatio results are discussed i sectio III, ad the coclusios are preseted i sectio IV. TABLE II INDEX AND RANGE FOR PRIME FACTOR MAPPING INDEX = A + B (( 2)) N k = Ck + Dk (( 2)) N RANGE 0 N 0 2 N2 0 k N 0 k2 N2 TABLE I DRM SYSTEM PARAMETERS Mode FFT Size Used carriers (I 0kHz chael) A 288 226 B 256 206 C 76 38 D 2 88 Fig. 2. Covetioal OFDM commuicatio system II. PRIME FACTOR FFT FOR OFDM DEMODULATION IN DRM RECEIVERS The OFDM techique divides the data ito several frequecy sub-chaels whose badwidth is less tha the total data rate [7]. A covetioal OFDM system is represeted i Fig. 2, ad Fig. 3 shows a DRM system usig OFDM techique. The key part to a OFDM receiver is the FFT for multicarrier demodulatio, ad the computatioal complexity is proportioal to the square of the FFT size. To reduce the complexity of implemetatio ad it is desirable to covert the calculatio of a log DFT ito short DFTs, various decompositio algorithms have bee proposed [8], [9]. For a radix-2 FFT calculatio, a umber of radix-2 DFTs are formed by decomposig a log DFT usig commo factor mappig (CFM). But the CFM method geerates a large umber of twiddle factors ad requires umerous multiplicatio operatios. To elimiate the requiremet for twiddle factor multiplicatio, prime factor mappig (PFM) ca be used for the decompositio if the composite factors of the sequece legth of the DFT are prime umbers [0]. For usig PFM method, it is ecessary to defie the idex mappigs of the DFT form. If N ad N 2 are relatively prime (N = N N 2 ), a differet choice of the costats ca be selected to elimiate the twiddle factors as show i Table II. Equatio () shows the relatio of the twiddle factor ad the idex mappig; it requires that ((AC)) N = N 2, ((BD)) N = N ad ((AD)) N = ((BC)) N = 0. We must fid the coefficiet A, B, C, ad D i () so that all values of ad k betwee 0 ad N- are uique ad such that the twiddle factors disappear [2], [3]. W ( A+ B2)( Ck+ Dk2) k2 N = W () Fig. 3. DRM system usig the OFDM techique A. Uiqueess Coditio To fid the uiqueess coditio, the Chiese Remaider Theorem (CRT) is used. Oe set of coefficiets that satisfies the uiqueess coditio ad elimiates the twiddle factor ca be described as below. A = N, B = N The DFT is defied by C = N (( N )) N, D = N (( N )) N 2 2 N = 0 (2) k X[ k] = x[ ] W, k=0,,, N N - (3) Usig these idex mappigs, we ca express the DFT as a fuctio of the two idices k ad k 2. If we substitute (2) ito (3), the DFT equatio ca be expressed as show below. X[(( N (( N )) k + N (( N )) k )) ] 2 2 N N 2 N 2 N N = [ x[(( N + N )) ] W ] W 2 N N N2 (4)
592 B. Middle Expressio The two dimesioal array represetatio of the iput is show i Table III. Modulo N reductio is ecessary for these idex maps so that the effective values of ad k remai betwee 0 ad N-. The N-poit trasforms of the rows lead to the represetatio show below. summatio block. Several summatios are calculated for the DFT i the secod step. I the third step, the results of the secod step are multiplied with 5 complex multipliers. I the last step, the fial summatios for DFT are calculated, ad the results are stored i the D output register block i which output data is ordered by the shufflig module. N k = + (5) 2 N N = 0 M [, k] x[(( N N)) ] W TABLE III Iput Idex 2D Expressio 2 0 N 0 x[0]... Iput Register Output Register Middle shufflig module Middle Register/Multiplier Iput shufflig module Fig. 4. Pipelied mixed PFA for DRM system Output shufflig module.... N2.. X N + N 2 [(( )) ] N C. Output Expressio Sice o twiddle factors are eeded, the colum trasforms are give by X[(( N (( N )) k + N (( N )) k )) ] 2 2 N N 2 N 2 N 2 = M [, k] W = 0 2 k 2 2 N 2 Usig (6) ad cosiderig DRM system eeds 288, 256, 76, ad 2 FFT sizes, the complexity of mixed prime factor FFT ca be dramatically reduced by 32, 6,, 9, ad 7 factors with sie ad cosie coefficiets; the maximum umber of coefficiets is 22. (6) Fig. 5. Block diagram of the modified -poit DFT A. Expressios of PFA FFT for DRM Usig the exteded pipelie architecture of the CRT mappig, the iput, middle, ad output data sequeces ca be directly loaded ito 4 kids of FFT poits. More importatly, the CRT mappig ca also be used to represet the output data, ad the computed results should be stored i 3 kids of shufflig registers. From (6), the proposed PFA FFT expressios with CRT mappig ca be described as below. III. PROPOSED PIPELINED MIXED PFA FFT The proposed pipelied architecture of a mixed prime factor algorithm (PFA) for DRM maily comprises a radix-2 FFT module, oe modified -poit DFT module, ad three shufflig modules, as show i Fig. 4. The iput shufflig module arrages the outputs of the iput register block to provide proper CRT mappig for the radix-2 FFT module ad is comprised of multiplexers for proper routig of the outputs. A middle shufflig module is used to support the 4 differet modes of the DRM system. It arrages the outputs of the radix-2 FFT module to provide the proper iputs for the modified -poit DFTs module usig CRT mappig. The -poit DFT module is a combiatioal circuit, ad the DFT is computed usig a Wiograd Fourier Trasform Algorithm (WFTA) [8]. The implemetatio of the -poit DFT is divided ito 4 steps that correspod to the flow i the algorithm, as show i Fig. 5. I the first step, stored values of middle register perform the switchig for the secod 288 poit : X[((225k + 64 k )) ] 2 288 8 3 = [ x[((9 + 32 )) ] W W 2 76 poit : X[((33k + 44 k )) ] 76 2 288 32 9 0 5 = [ x[(( + 6 )) ] W W 2 2 poit : X[((49k + 64 k )) ] 2 76 6 6 5 = [ x[((7 + 6 )) ] W W 2 6 7 Mixed PFA FFT calculates 32 poits ad 6 poits usig the radix-2 method. A pipelie radix-2 structure is devised, ad a multiplexer is used to distiguish 288, 256 poits or 76, 256 (7) (8) (9)
D.-S. Kim et al.: Desig of a Mixed Prime Factor FFT for Portable Digital Radio Modiale Receiver 593 poits. Because of the multiplyig twiddle factor i 256 poit, a complex multiplier is used betwee the radix-2 FFT module ad the middle register. A multiplied twiddle factor results i a factor value for arithmetic ad is stored i read-oly memory (ROM). B. -poit DFT Block The -poit DFT block calculates 4 kids of DFT ad multiplexig operatio to distiguish the 7, 8, 9, poits. By usig a multiplexer, 4 kids of DFT poits ca be calculated without chagig hardware. If the cotrol sigal idicates the use of the poit mode, values from a0 to a0 are received ad multiplied by the twiddle factor. The -poit DFT has a maximum twiddle factor parameter of 5. Because the iput ad output sequeces are ot i ormal order, the elimiatio of the twiddle factor multiplicatios by the PFA is at the expese of complex idexig withi the algorithm. I cotrast to radix-2 algorithms, which use a sigle butterfly computatio ad a highly ested program structure, a PFA requires a differet butterfly for each factor ad is most easily programmed by takig oe factor at a time. The radix-2 3 algorithm has the same computatioal complexity as the split-radix algorithm [7]. As show i Fig. 6, the multiplicative operatios are i such a arragemet that for every 3 colums, oe has otrivial full complex multiplicatio operatio. are i ormal order, ad the mixed PFA FFT is chose as the most attractive approach. From experimetal results, it was show that the proposed mixed PFA FFT ca dramatically reduce the total umber of multipliers ad adders eeded. The mixed PFA FFT requires less data storage memory, ad the umber of multiplicatios by differet costats is much smaller tha that i the other algorithm. As a result, the proposed architecture reduces the processig time ad eergy cosumptio of portable DRM receivers. TABLE IV Compare the umber of operatios PFA FFT R2SDF R4SDC R2 3 SDF Poit Mul Add Mul Add Mul Add Mul Add 288 000 5928 52 4096 926 2560 7680 2048 926 76 860 2688 256 792 4096 768 4096 768 3840 2 396 288 28 768 792 384 408 256 792 TABLE V Compariso of the umber of multipliers ad adders PFA FFT Poit Real Multiplier Adder 288 22 28 256 22 28 76 26 26 8 22 Total 88 04 Proposed PFA 30 30 Fig. 6. Block diagram of pipelied 2 3 -FFT C. Performace Aalysis For performace evaluatio, the covetioal structure ad the proposed mixed PFA FFT structure are compared by the umber of arithmetic operator uits eeded, such as multipliers ad adders. The proposed mixed PFA FFT structure uses a multiplexer-based architecture to calculate radix-2 poits. Such architecture decreases the total umber of multipliers ad adders. As show i Tables IV ad V, the total umber of multipliers ad adders are reduced by approximately 34.% ad 28.9%, respectively. From the compariso, we ca coclude that proposed PFA FFT structure decreases the umber of operator uits ad is excellet for area ad power cosumptio. IV. CONCLUSION I this paper, we proposed a mixed prime factor algorithm ad a efficiet architecture for DRM systems. For opower-of-two FFT, either the iput or the output sequeces REFERENCES [] F. Hofma, C. Hase, ad W. Schafer, Digital Radio Modiale (DRM) Digital Soud Broadcastig i the AM Bads, IEEE Tras., vol. 49, pp.39-328, Sept. 2003. [2] C. S. Burms, Idex Mappigs for Multidimesioal Formulatio of the DFT ad Covolutio, IEEE Tras. Acoust., Speech, Sigal Processig, vol. ASSP-25, pp. 239-242, Jue 977. [3] ETS 300 40 Radio Broadcastig System: Digital Audio Broadcastig to mobile portable ad fixed receiver, ETSI, May 997. [4] Digital Radio Modiale (DRM); System Specificatio, Europea Telecommuicatio Stadards Istitute (ETSI). [5] http://www.drm.org/. [6] A. Rivato, J. Quevremot, Z. Qiwei, P. Wolkotte, ad G. Smit, Implemetig No-Power-of-Two FFTs o Coarse-Grai Recofigurable Architectures, Proceedigs of 2005 Iteratioal Symposium o System-o-Chip, pp. 74-77, Nov. 2005. [7] J. H. Stott, Explaiig Some of the Magic of COFDM, 20th Iteratioal Televisio Symposium, Jue 997. [8] M. D. Macleod, Multiplierless Wiograd ad Prime Factor FFT Implemetatio, IEEE Tras. Sigal processig, vol., o.9, Sept. 2004. [9] A. V. Oppeheim ad R. W. Schafer, Discrete-time Sigal Processig, Pretice-Hall [0] D. Kolba ad T. Parks., A Prime Factor FFT Algorithm Usig Highspeed Covolutio, IEEE Tras. Acoust., Speech, Sigal Processig, vol. ASSP-25, pp. 28-294, Aug 977. [] B. Nog ad Z. Wag, A New Nestig Scheme of Prime Factor Algorithm, IEEE ICASSP, vol. 3, pp. 495-498, April 990.
594 [2] D. C. Muso, Jr., Floatig Poit Roud-off Error i the Prime Factor FFT, IEEE Tras. Acoust., Speech, Sigal Processig, vol. ASSP-29, pp. 877-882, Aug 98. [3] C. S. Burms, A I-Place, I-Order Prime Factor FFT Algorithm, IEEE Tras. Acoust., Speech, Sigal Processig, vol. ASSP-29, pp. 806-87, Aug 98. [4] S. Bouguezel, M. O. Ahmad, A Geeral Class of Split-Radix FFT Algorithms for the Computatio of the DFT of Legth-2m, IEEE Tras o Sigal Processig, vol. 55, o. 8, August 2007. [5] D. P. Kolba, A Prime Factor FFT Algorithm usig High Speed Covolutio, M.S. thesis, Rice Uiv., Husto, TX, May 977. [6] S. Xu, H. Yag, H. Zhag, ad H. Wag, A New Modulatio Scheme for DRM, IEEE VCT2005, pp. 245-247 vol. 2, Jue 2005. [7] S. Bouguezel, M. O. Ahmad, ad M. N. S. Swamy, A Geeral Class of Split-Radix FFT Algorithms for the Computatio of the DFT of Legth- 2m, IEEE Tras. Sigal Processig, vol. 55, No. 8, Aug. 2007. Dog-Su Kim (M 99) was bor i Icheo, South Korea, i 972. He received his B.S. ad M.S. degrees from the School of Electroics ad Electrical Egieerig at INHA Uiversity, Icheo, South Korea i 997 ad 999, respectively. I 2005, he received the Ph.D. degree from the School of Iformatio ad Telecommuicatio Egieerig at INHA Uiversity, Icheo, South Korea. Sice 999, he has worked with the Korea Electroics Techology Istitute (KETI), Gyeoggi-do, South Korea, workig i R&D at the Advaced Mobile Techology Research Ceter. Curretly he is a seior researcher ad team leader. He is a member of the IEEE. His research iterests are i the areas of wireless/wired commuicatio systems, wireless sesor etworks, VLSI & SoC desig, multimedia codec desig, computer architecture, ad embedded system desig. Jae-Yeo Sog was bor i Bou, South Korea i 980. He received his B.S. degree from the school of Iformatio ad Telecommuicatio Egieerig from the INHA Uiversity, South Korea, i 2007. He is curretly pursuig a M.S. degree i Iformatio ad Commuicatio Egieerig at INHA Uiversity, South Korea. His curret research iterests are SoC desig, wireless commuicatio, JPEG2000, ad UWB system. Kyu-Yeul Wag was bor i Icheo, South Korea i 98. He received a B.S. ad M.S. degree from the School of Iformatio ad Telecommuicatio Egieerig of INHA Uiversity, Korea i 2006 ad 2008, respectively. He is curretly pursuig a Ph.D. degree i Iformatio ad Commuicatio Egieerig at INHA Uiversity. His curret research iterests are wireless commuicatio, MPEG-4, WLAN, ad VLSI & SoC desig. Duck-Ji Chug was bor i Korea o February 8, 948. He received his B.S degree from the Seoul Natioal Uiversity of Electrical Egieerig, Korea o 970, ad his M.S. degree from Utah State Uiversity o 984. I 988, he received his Ph.D. degree from Uiversity of Utah. He is curretly a professor at the school of Iformatio ad Commuicatio Egieerig of INHA Uiversity, Icheo, South Korea. He is a member of IEEE. His research iterests are the VLSI & SoC desig ad computer architecture ad embedded system desig. Sag-Seol Lee was bor i Chug-Ju, South Korea i 98. He received his B.S. degree from the school of Iformatio ad Telecommuicatio Egieerig from the INHA Uiversity, South Korea, i 2007. He is curretly pursuig a M.S. degree i Iformatio ad Commuicatio Egieerig at INHA Uiversity, South Korea. His curret research iterests are wireless commuicatios, PCMCIA, UWB, ad VLSI & SoC desig.