ULNA, ULNA, ULNA, ULNA SLRS DECEMBER REVISED APRIL HIGH-VOLTAGE HIGH-CURRENT -ma Rated Collector Current (Single ) High-Voltage s... V Clamp Diodes Inputs Compatible With Various Types of Logic Relay Driver Applications Designed to Be Interchangeable With Sprague ULNA Series description D OR N PACKAGE (TOP VIEW) The ULNA, ULNA, ULNA, and ULNA are monolithic high-voltage, high-current Darlington transistor arrays. Each consists of seven npn Darlington pairs that feature high-voltage outputs with common-cathode clamp diodes for switching inductive loads. The collector-current rating of a single Darlington pair is ma. The Darlington pairs may be paralleled for higher current capability. Applications include relay drivers, hammer drivers, lamp drivers, display drivers (LED and gas discharge), line drivers, and logic buffers. For -V (otherwise interchangeable) versions, see the SN through SN. The ULNA is a general-purpose array and can be used with TTL and CMOS technologies. The ULNA is specifically designed for use with - to -V PMOS devices. Each input of this device has a zener diode and resistor in series to control the input current to a safe limit. The ULNA has a.-kω series base resistor for each Darlington pair for operation directly with TTL or -V CMOS devices. The ULNA has a.-kω series base resistor to allow its operation directly from CMOS devices that use supply voltages of to V. The required input current of the ULNA is below that of the ULNA, and the required voltage is less than that required by the ULNA. B B B B B B B E C C C C C C C COM logic symbol logic diagram B B B B B B B CLAMP This symbol is in accordance with ANSI/IEEE Std - and IEC Publication -. COM C C C C C C C B B B B B B COM C C C C C C B C PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright, Texas Instruments Incorporated POST OFFE BOX DALLAS, TEXAS
ULNA, ULNA, ULNA, ULNA SLRS DECEMBER REVISED APRIL schematics (each Darlington pair) COM C Input B. kω kω E ULNA POST OFFE BOX DALLAS, TEXAS
ULNA, ULNA, ULNA, ULNA SLRS DECEMBER REVISED APRIL
ULNA, ULNA, ULNA, ULNA SLRS DECEMBER REVISED APRIL switching characteristics, T A = C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tplh tphl Propagation delay time, low-to-high-level output Propagation delay time, high-to-low-level output See Figure. µs. µs VOH High-level output voltage after switching VS = V, See Figure IO ma, VS mv PARAMETER MEASUREMENT INFORMATION EX EX VI Figure. I CEX Test Circuit Figure. I CEX Test Circuit II(off) II(on) VI Figure. I I(off) Test Circuit Figure. I I Test Circuit hfe = I C II II VI(on) NOTE: II is fixed for measuring (sat), variable for measuring hfe. Figure. h FE, V CE(sat) Test Circuit Figure. V I(on) Test Circuit POST OFFE BOX DALLAS, TEXAS
ULNA, ULNA, ULNA, ULNA PARAMETER MEASUREMENT INFORMATION SLRS DECEMBER REVISED APRIL VR IR VF IF Figure. I R Test Circuit Figure. V F Test Circuit Input % % t PHL t PLH % % VOLTAGE WAVEFORMS Figure. Propagation Delay Time Waveforms VS Pulse Generator (see Note A) Input ULNA only. kω ULNA ULNA ULNA N mh Ω CL = pf (see Note B) TEST CIRCUIT Input ns % %. V. V % % µs ns VIH (see Note C) V VOLTAGE WAVEFORMS VOH VOL NOTES: A. The pulse generator has the following characteristics: PRR =. khz, ZO = Ω. B. CL includes probe and jig capacitance. C. For testing the ULNA and the ULNA, VIH = V; for the ULNA, VIH = V; for the ULNA, VIH = V. Figure. Latch-Up Test Circuit and Voltage Waveforms POST OFFE BOX DALLAS, TEXAS
ULNA, ULNA, ULNA, ULNA SLRS DECEMBER REVISED APRIL TYPAL CHARACTERISTS COLLECTOR-EMITTER SATURATION VOLTAGE COLLECTOR CURRENT (ONE DARLINGTON) COLLECTOR-EMITTER SATURATION VOLTAGE TOTAL COLLECTOR CURRENT (TWO DARLINGTONS PARALLELED) (sat) V Collector-Emitter Saturation Voltage V CE(sat)... TA = C Collector Current ma Figure II = µa II = µa II = µa (sat) Collector-Emitter Saturation Voltage V... TA = C II = µa II = µa II = µa (tot) Total Collector Current ma Figure Collector Current ma RL = Ω TA = C COLLECTOR CURRENT INPUT CURRENT VS = V VS = V II Input Current µa Figure POST OFFE BOX DALLAS, TEXAS
ULNA, ULNA, ULNA, ULNA THERMAL INFORMATION SLRS DECEMBER REVISED APRIL D PACKAGE MAXIMUM COLLECTOR CURRENT DUTY CYCLE N PACKAGE MAXIMUM COLLECTOR CURRENT DUTY CYCLE Maximum Collector Current ma N = N = N = N = N = N = TA = C N = Number of s Conducting Simultaneously N = Duty Cycle % Maximum Collector Current ma N = N = N = TA = C N = Number of s Conducting Simultaneously N = Duty Cycle % N = N = N = Figure Figure POST OFFE BOX DALLAS, TEXAS
ULNA, ULNA, ULNA, ULNA SLRS DECEMBER REVISED APRIL APPLATION INFORMATION VSS ULNA V VCC ULNA V P-MOS TTL Lamp Test Figure. P-MOS to Load Figure. TTL to Load VDD ULNA V VCC ULNA V RP CMOS Figure. Buffer for Higher Current Loads TTL Figure. Use of Pullup Resistors to Increase Drive Current POST OFFE BOX DALLAS, TEXAS
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