A New High Performance Complementary Bipolar Technology Featuring 45GHz NPN and 20GHz PNP Devices. M C Wilson, P H Osborne, S Thomas and T Cook Mitel Semiconductor Cheney Manor, Swindon, Wiltshire, SN2 2QW, U.K. Tel: +44 1793 518000, FAX: +44 1793 518351 E-mail: martin_wilson@mitel.com ABSTRACT A new high performance silicon complementary bipolar technology is introduced. In addition a novel process "enhancement" technique based on a local oxidation is described and demonstrated and NPN devices with cut-off frequencies up to 45GHz and PNP devices of 20GHz have been fabricated. We propose that the technique we have used will allow specific transistors within a circuit to be optimised, as required. Keywords: Silicon, RF, Bipolar technology, Complementary, Local oxidation 1. INTRODUCTION To meet the challenge of future 5GHz RF communications systems we have developed a high performance complementary bipolar process technology. We have adopted the complementary approach as it enables more efficient design of power consumption stages, synthesisers, linear amplifiers and active filters. Our new silicon complementary bipolar technology, Process HJ, is fully isolated, is wholly silicon and includes a full suite of passive components. The high performance PNP of this process has been designed with comparable current handling to the NPN and generally gives greater design flexibility. The process is considered ideal for low voltage, low power mixed signal RF and IF applications and primary applications will be synthesisers, converters, mixers, tuners and amplifiers. In this paper we build on the performance and flexibility of Process HJ by recognizing that in certain RF circuit stages the resulting chip could have improved performance if the technology available to the designer comprised transistors with different levels of performance. In a complementary process, for example, we propose that the technology could comprise not only "standard" NPN and PNP transistors but also "super" NPN and PNP transistors as well. In this paper we outline the basic complementary process HJ and introduce a novel process "enhancement" technique. We fully describe the enhancement technique, a technique based on the sacrificial oxidation of part of the epitaxial layer, and demonstrate its use to tailor the NPN device of the complementary. In the initial application we have enhanced the performance of all NPN test devices while maintaining the PNP performance. We propose that the technique we have used to be highly selective and could permit specific devices, NPN or PNP, to be optimized, if required. We report first results on enhanced NPN devices with cut-off frequencies up to 45GHz and PNP devices of 20GHz. 2. PROCESS DESCRIPTION The complementary process, HJ, was developed from an earlier NPN-only technology [1] and has been described fully elsewhere [2]. In summary, HJ includes standard NPN transistors, standard vertical PNP transistors, lateral PNP transistors, high and low value polysilicon resistors, low value capacitors (with an optional high value capacitor), integrated inductors, ESD protection and substrate contacts. The complete complementary process comprises a high performance NPN and a fully integrated PNP and uses 7 photomasks more than a comparable high performance NPN-only process. The additional photo operations are for low tolerance implant clearance masks. The buried layers for the PNP are formed by deep implants, optimised for zero defects, but without any degradation to performance. The thin n-type epitaxial layer is determined by the NPN, and over-doped with an implanted p-well for the PNP. The minimum photolithographic feature for HJ is 0.6µm, for the NPN and PNP emitters
and isolation is achieved by 0.8µm wide, 7µm deep trenches. The process has 3-level metallisation with a contact pitch of 2.4µm at the first level. The NPN and PNP transistors are shown schematically in cross-section in figures 1 and 2. The emitter region of a PNP device (without metal layers, for clarity) is shown in the TEM cross-section of figure 3. Base Emitter Collector oxide P+ base P+ epitaxy (n-) DC Oxide BN CS Substrate (p-) CS Figure 1. Schematic cross-section of a NPN transistor. Base Emitter Collector Well N+ N+ Base pwell DC Oxide Oxide Oxide BP CS BSUB oxide Oxide Substrate (p-) CS Figure 2. Schematic cross-section of a PNP transistor. Figure 3. TEM cross-section of fabricated PNP "standard" emitter.
3. DEVICE RESULTS: STANDARD Typical "standard" device parameters are shown in Table 1 and passive component parameters in Table 2. The current gain of NPN and PNP transistors are typically 150 and 50 respectively yielding beta-early voltage products of 5250 and 1650 respectively. The collector-emitter breakdown voltages are normally 3.5V and 4.5V for the NPN and PNP devices, respectively. Table 1. Typical "standard" device parameters. Param. Condition NPN PNP Units Emitter size 0.6 x 3 0.6 x 3 µm Hfe Vbe=0.7V 150 50 Vcb=0V Hfe Vbe=0.8V 150 50 Vcb=0V Ic(on) Vbe=0.7V 1 0.4 µa Vcb=0V Ic(on) Vbe=0.8V 40 15 µa Vcb=0V BVcbo Ic=1µA 12 9 V BVces Ic=1µA 12 9 V BVceo Ic=1µA 3.5 4.5 V BVebo Ie=1µA 3 3 V Vaf 35 33 V ft Vce=3V 30 20 GHz (@Ic) (1.3mA) (0.9mA) Re 15 18 Ω Rb 400 400 Ω Rc 100 320 Ω Cje Vbe=0V 10 10 ff Cjc Vcb=0V 4.5 9 ff Cjs Vcs=0V 16 20 ff Table 2. Typical passive component parameters. Comp. Type Value Units poly res LoN 110 Ω/sq poly res LoP 155 Ω/sq poly res HiP 1400 Ω/sq PtSi res PtSi 9 Ω/sq Cap MIM 0.5 ff/µm 2 HVCap dc 1.4 ff/µm 2 Varactor c-b 0.6 ff/µm 2 Inductor integrated 3.5 nh Inductor integrated >10 Q Schottky PtSi diode 500 mv@100ua
Figures 4 and 5 are average Forward Gummel plots of NPN and PNP transistors respectively and show constant gain over 6 decades of current, in each case. The curves are mean values from 686 sites distributed across multiple wafers and lots. Good ideality was observed indicating good quality junctions. Figure 4. Average Gummel plot for 0.6x3.0µm "standard" NPNs. Figure 5. Average Gummel plot for 0.6x3.0µm "standard" PNPs. Figures 6 and 7 show the variation of the cut-off frequency (ft) with collector current (Ic) at a Vce of 3V for NPN and PNP devices. The peak ft for the NPN was 30GHz at 1.3mA and for the PNP was 20GHz at 0.9mA. The NPN at 2V Vce had a 1sigma spread in ft (at peak ft) of 8% and the PNP, 3.5%. The data was from more than 300 sites distributed across multiple wafers and lots and demonstrated good overall process control. The degradation in cut-off frequency at high collector currents is attributed to the Kirk effect and carrier saturation at the base-collector junction. The PNP exhibits slightly more pronounced degradation beyond the ft peak, compared to the NPN device, due to its higher collector resistance. The PNP collector was optimised for performance, voltage-breakdown and yield. The resulting PNP transistor exhibited an excellent peak ft, a 4.5V collector-emitter breakdown and a forward beta of 50.
30 25 Vce 3V 20 15 10 5 0 1E -05 1E -04 1E -03 1E -02 Ic (A) Figure 6. ft versus Ic plot for 0.6x3.0µm "standard" NPN. 25 20 Vce=3V 15 10 5 0 1E -05 1E -04 1E -03 1E -02 Ic (A) Figure 7. ft versus Ic plot for 0.6x3.0µm "standard" PNP. Figures 8 and 9 show typical Gummel plots from multiple NPN and PNP transistor arrays. The arrays comprised up to 30K minimum geometry (0.6x1.6µm) transistors which exhibited current scaling with array size. This impressively demonstrates the integrity of the transistors and is particularly significant for the PNP as it reinforces our claim that the implanted layers were of good quality.
1E -01 Ic 1E -02 1E -03 1E -04 Ib 1E -05 1E -06 1E -07 1E -08 1E -09 1E -10 0.40 0.50 0.60 0.70 0.80 0.90 Vbe (V) Figure 8. Gummel plots of parallel arrays of 3k and 30k "standard" NPN devices. 1E -01 1E -02 Ic 1E -03 Ib 1E -04 1E -05 1E -06 1E -07 1E -08 1E -09 1E -10 0.50 0.60 0.70 0.80 0.90 Vbe (V) Figure 9. Gummel plots of parallel arrays of 3k and 24k "standard" PNP devices. 4. CIRCUIT PERFORMANCE: STANDARD Initial circuit performance has been demonstrated using both NPN and PNP ring oscillators. The ROs for the NPN devices were 11-stage CML circuits with a divide-by-sixteen stage attached. For minimum geometry NPN devices the power delay product was 20fJ with a minimum gate delay of 31ps at 300uA. The minimum gate delay achieved for optimised NPN devices was 23ps. The ROs for the PNP devices were 41-stage CML circuits and minimum geometry devices exhibited a power delay product of 40fJ with a minimum gate delay of 50ps at 300uA. Circuit performance has been further assessed by fabricating a wide dynamic range RF amplifier with automatic gain control for applications up to 2GHz. The circuit had a maximum gain of +22dB, noise figure of 7dB and IIP2 of +12dBm with IIP3 of +15dBm. Additional circuits have been designed including RF down-converters and up-converters for media tuners, dual band GSM lineariser circuits for digital mobile phone base stations and pre-amplifiers for optical disc drives. 5. DEVICE RESULTS: ENHANCED As stated earlier, in certain RF circuit stages the resulting chip could have improved performance if the technology available to the designer comprised transistors with different levels of performance. To demonstrate this we have used a technique based on LOCOS to sacrificially oxidise part of the epitaxial layer to tailor the NPN device. In an initial application we have enhanced the performance of all NPN test devices while maintaining the PNP performance. However, the technique we have used will allow specific devices, NPN or PNP, to be optimised, if required. In many ways this "sacrificial oxidation" technique is analogous to that of the "selective implanted collector" (SIC) but, we believe, has the advantage of superior control, manufacturability and flexibility [3], [4]. Figure 10 shows an SEM micrograph of an NPN transistor during processing. In this example the device has had buried layer processing, epitaxy, deep trench etching and sacrificial oxidation. All oxide has been removed and the small, depressed region in the silicon is evident. This results in a localised reduction of the epitaxial layer. In this experiment a range of sacrificial oxides were grown, the details for which are shown in Table 3. Subsequent device fabrication was standard with no further modification necessary.
Table 3. Sacrificial oxide thickness details. Sample Sacrificial Tox Sacrificial Tox Units NPN PNP Oxide.0 0 0 A Oxide.1 1660 0 A Oxide.2 2650 0 A Oxide.3 3500 0 A Figure 10. NPN transistor showing local thinning of epitaxy after removal of sacrificial oxide The resulting NPN device parameters are shown in Table 4. The cut-off frequency, breakdown voltages and Early voltage are a function of the reduced epitaxial thickness and grown sacrificial oxide. The NPN beta remained constant throughout because the emitter-base processing was identical in each case. This is considered another advantage over the SIC technique. Finally, the cut-off frequencies at a Vce of 2.4V are shown in figure 11 for NPN devices of each sacrificial oxide. The peak cut-off frequencies were 28GHz, 36GHZ, 40GHZ and 45GHz. Table 4. "Enhanced" NPN device parameters. NPN Oxide.1 Oxide.2 Oxide.3 Units Parameter Emitter size 0.6 x 3 0.6 x 3 0.6 x 3 µm Hfe 110 110 130 Vbe=0.8V Ic(on) 0.28 0.33 0.26 µa Vbe=0.8V BVcbo 10.9 9.5 8.2 V BVceo 3.7 3.4 3.1 V Vaf 26 25 10 V ft Vce=2.4V 36 40 45 GHz
50 Vce=2.4V 40 30 ft (GHz) 20 10 0 1E-06 1E-05 1E-04 1E-03 1E-02 Ic (A) Oxide.0 Oxide.1 Oxide.2 Oxide.3 Figure 11. ft versus Ic plots for 0.6x3.0µm standard (oxide.0) and "enhanced" NPNs.
6. SUMMARY AND CONCLUSIONS A new high performance silicon complementary bipolar technology has been reported. A novel process "enhancement" technique based on LOCOS has been demonstrated and NPN devices with cut-off frequencies up to 45GHz and PNP devices of 20GHz have been fabricated. ACKNOWLEDGEMENTS The authors would like to thank our Mitel collegues and all members of the Swindon Fab. The authors acknowledge the contribution of P Pearson and P Augustus of GEC-Marconi Materials Technology Ltd. REFERENCES 1. P C Hunt and M P Cooke, "Process HE: A highly advanced trench isolated bipolar technology for analogue and digital applications", Proc. 1988 IEEE CICC, pp22.2.1-22.2.4, Rochester, New York, USA. 2. M C Wilson et. al. "Process HJ: A 30GHz NPN and 20GHz PNP complementary bipolar process for high linearity RF circuits", Proc. IEEE 1998 BCTM, pp164-167, Minneapolis, USA. 3. S Konaka et.al. "A 20ps/G Si bipolar IC using advanced SST with collector ion implantation", Proc 19th ICSSDM 1987, p331, Tokyo, Japan. 4. M C Wilson et.al. "Application of a selective implanted collector to an advanced bipolar process", Proc 20th ESSDERC 1990, p349, Nottingham, UK.