37th CDC, Tampa, December 1998 Analyss of Delays n Synchronous and Asynchronous Control Loops Bj rn Wttenmark, Ben Bastan, and Johan Nlsson emal: bjorn@control.lth.se, ben@control.lth.se, and johan@control.lth.se Department of Automatc Control, Lund Insttute of Technology Box 118, SE-221 00 Lund, Sweden Abstract In ths paper we descrbe how to determne the tme delays caused by synchronous and asynchronous control loops. These tme delays can vary n a qute rregular way and can cause problems for the control loops closed over a communcaton network of, for nstance, eldbuses. Derent setups allowng an arbtrary number of communcaton layers are analyzed. The theoretcal dervatons are llustrated wth a smple, although realstc, example. 1. Introducton One of the problems whch occurs n commercal control systems s tme varatons due to asynchronous sgnals wthn the control loops. An example s when the communcaton s done over a eld-bus where the sgnal s sampled wth a rate hgher than the samplng rate of the controller and then sent to the controller node. Ths means that due to the samplng and synchronzaton of the sgnals to and from the I/O devce to the controller there may be a delay varaton whch aects the performance of the closed loop system. An example s shown n Fgure 1. Ths smple system conssts of a communcate usng a eld-bus. In the I/O module the output of the process s A/D converted, and the result s coped nto memory cell m1. Synchronzed wth ths s the D/A converson whch wrtes the content of m4 to the process. Both these events occur every 250 ms, however, they may not necessarly be completely synchronous, that s there may be a phase derence between the nput and the output. There mght also be derent samplng rates n the nput and output processes leadng to asynchronous loops. The A/D and D/A converters may very well be located n derent nodes. In a smlar way, both the wrte bus, transferrng values from m1 to m2, and the read bus, transferrng values from m3 to m4, share the same tmng, although there may also be a phase derence between the two. The samplng rate s 256 ms. Fnally, the controller s samplng and wrtng back to the bus wth a samplng perod of 1.1 s. The seres of events of a typcal cycle are shown n Fgure 2. a) b) Contnuous tme system From sensor To actuator I/O devce A/D D/A m1 m4 Feld-bus m2 m3 Controller Algorthm c) d) A/D converter Feld-bus Fgure 1 Control system wth asynchronous loop. control system and an I/O unt whch are connected by a eld-bus. Ths example was gven n Nlsson (1998) and Nlsson et al. (1998a), and s one motvaton for lookng at the problem of tmng and delays n asynchronous loops. The example s used to llustrate the deas n ths paper. The control system n Fgure 1 has two unts, an I/O module and a controller, whch On leave from Department of Electrcal and Computer Engneerng, Unversty of Newcastle, Newcastle, NSW, Australa e) f) τ d Controller Feld-bus D/A Converter (s) Fgure 2 Tmng of a typcal cycle n a system wth asynchronous loops.
In Fgure 2(a) we have the contnuous tme sensor sgnal, whch s the output of the process whch s to be controlled. In Fgure 2(b) the sgnal s rst A/D converted. In our example ths occurs once every 250 ms. Ths sgnal corresponds to the value of m1. In Fgure 2(c) the sgnal s mrrored usng the bus, thus ths sgnal corresponds to the value of m2. In Fgure 2(d) the sgnal s used by the controller and the next control sgnal s computed. Ths sgnal s wrtten to the output of the controller, m3. There may also be delays due to the calculatons n the controller algorthm. These delays are n ths paper neglected. The computatonal delays are dscussed n, for nstance, str m and Wttenmark (1997) and Nlsson (1998). In Fgure 2(e) the sgnal s mrrored by the bus once agan. Ths occurs every 256 ms and the sgnal obtaned here corresponds to that found n m4. In Fgure 2(f) the sgnal s A/D converted and sent to the actuator. The descrbed system s a smple verson typcal of commercal control systems wth dstrbuted I/O and control. Complcatons can nclude extra layers of control, for nstance, a plant-wde Ethernet wth lmted real tme capabltes. Ths setup wll gve a system wth varyng delay from sensor to actuator. We wll look at the varatons of the control delay, whch s the tme from when the measurement sgnal s sampled to when t s used n the actuator. The total tme delay due to the communcaton s d, see Fgure 2. Fgure 3 shows a smulaton of the system n Fgure 1. The tme delay can n ths case take the values 190, 440, and 690 ms. More complcated delay patters can also be obtaned as dscussed n Secton 7. Notce that the delays can be qute long compared to the basc samplng rates at the converters and n the bus. In ths case the longest delay s almost three tmes the samplng perod n the eld-bus. Descrpton of the delays The delay pattern n Fgure 3 looks qute rregular. To compensate for the tme delay we may try to model them as a random process and use the desgn methods n Nlsson et al. (1998b) and Nlsson (1998) to compensate for the delays. Other references are Ray (1994), Krtolca et al. (1994), and Chan and zguner (1995). The method pursued n Nlsson (1998) s a stochastc approach modelng the delays usng a sequence of Markov chans. Nlsson and Bernhardsson (1997) also gves the optmal LQG controllers for stochastc delays n control loops. Usng tme stampng the delays can be computed and the controllers can then be desgned to compensate for the delays. Event drven versus clock drven events In ths paper t s assumed that the events are clock drven. Clock drven means that events take place at prespeced tmes accordng to parameters set by a tmng devce, usually perodc samplng. It s also possble for events to be event drven, thus an event wll trgger another event. In Nlsson (1998) t s assumed that whle the nput s clock drven, the output and controllers are both event drven, thus they start processng as soon as nformaton s at hand. Here a derent case s beng examned, and all events are assumed to be clock drven, creatng rregular tme delays due to the nested loops. The computatonal tme n the control algorthm can also be ncluded usng the methodology n ths paper. 2. Model structure and assumptons The man part of the modelng s descrbed n further detals n the master thess Bastan (1998). The basc model whch wll be examned s descrbed by a seres of \layers", lke an onon, wth the controller beng encapsulated by the bus, the I/O, etc, see Fgure 4. An ncomng process sgnal must pass through several 0.6 Control delay 0.4 0.2 Level L 0 0 100 200 Sample number Fgure 4 The varous archtecture layers can be seen as layers of an onon. Fgure 3 Control delay due to asynchronous loops of the system n Fgure 1. layers to reach the controller and the outgong control sgnal must agan pass through several layers to get to
the process. Layer 0 s the controller process. In our example layer 0 corresponds to the controller process, layer 1 corresponds to the bus layer, and layer 2 to the I/O layer. The layers wll now be examned wth reference to the tme delays caused by ther nteracton. Ths wll be done both for a general model,.e. for any number of layers, and then as a case study for our example, to llustrate the propertes of the derved model. For the model, each layer s modeled by a separate tmng dagram, whch looks lke the one shown n Fgure 5. Input/Output Input Output 3. Dente synchronous systems Layer 0 has a sngle acton whch s the core of the system. Informaton goes no further than layer 0. In the example layer 0 s a controller. Intally layer zero s assumed to be nstantaneous, snce the computatonal delay s neglected, and t s clock drven, wth perod h 0. The case wth only a sngle layer s a trval case, where the tme delay s zero. We now consder a system wth two layers, layers 0 and 1. It s assumed that events don't occur nstantaneously,.e, a sgnal cannot be nput, processed, and output at the same nstant. In ths case layer 1 has two I/O events and at least a sngle event occurs n layer 0 between them. See Fgure 6, whch shows the three cases h 0 = h 1, h 0 h 1, and h 0 < h 1. The gure ndcates that all delays must be a multple of the samplng perod h 1. (For cases wth no phase derence n layer 1 t makes no derence whether the events n layer 0 are clock or event drven.) h θ Level L Fgure 5 The format of the tmng dagrams used for the models. In the case where h 0 = h 1 there s a controller event for every nterval of h 1 thus the total tme delay s equal to h 1. In the case where h 0 > h 1 nformaton 1 s sampled, but no controller event occurs. The nformaton s therefore dscarded when the next sample occurs, wth nformaton 2. Ths then s the nformaton processed when the event on layer 0, the controller event, occurs. The correspondng nformaton s then output at the next output of layer 1. It follows from ths that the total tme delay s h 1. In the case where h 0 < h 1 the nformaton receved by all ntermedate events on In Fgure 5 a crcle ndcates the tmng of the nput to the layer and a cross ndcated the tmng of the output. A sgnal s dened as beng nput when t s movng towards layer 0, and output when movng away from layer 0. Thus n our example the D/A converted sgnal s consdered an output on layer 2. For the analyss we need to ntroduce some notatons. The samplng frequency of layer, h, s dened to be the perod of the nputs of that layer. A layer s dened to be dente synchronous f the nput and the output of that layer occur at exactly the same tmes. See level 0 n Fgure 5. A layer where both nput and output have the same samplng rate, but do not occur at the same tme s dened as partally synchronous. See level 1 n Fgure 5. A layer where the nput and the output have derent samplng tmes s sad to be asynchronous. See level L n Fgure 5. The phase of a layer,, s dened to be the tme derence between the nput of the layer and the next occurrng output. For a dente synchronous system the phase s zero, for a partally synchronous system t s a constant, however, for an asynchronous system the phase wll be tme varyng. a) b) c) h 0 h 1 h 0 1 2 h 0 h 1 h 1 Fgure 6 Delays n a dente synchronous system wth two layers for the cases (a) h 0 = h 1, (b) h 0 h 1, and (c) h 0 < h 1.
layer 0 s the same durng each nterval h 1. Thus also n ths case the total tme delay s equal to h 1. n τ delay on layer The model can now be generalzed to accommodate for a system wth more than two layers. Informaton can only pass through the layer at samplng tmes. Informaton goes n at tme n h, and leaves at tme n h + k h. The total tme delay for samplng and returnng nformaton from process to controller and back to process s k h where k s a postve nteger. Therefore on layer L (the bottom layer) the total tme delay s d = k L h L (1) where k L s a postve nteger. For our example the tme delay of nterest s the total delay at the I/O layer. delay on layer + 1 It s now assumed that the delay at layer s and constant. From (1) t follows that +1 = k +1 Consder rst the case. See Fgure 7. Now s τ 2 +1 Fgure 7 Delay on layer +1 for a dente synchronous system when. drftng n relaton to due to the derent samplng rates. The possblty that the delay falls wthn a samplng perod of layer + 1 s (? )=. For ths case t follows that +1 =. Ths gves P(k +1 = 1) =? (2) The other opton s that +1 = 2. Ths occurs f and only f a samplng tme n layer + 1 falls n the nterval. Thus P(k +1 = 2) = (3) Now a longer delay tme for layer wll be examned,.e. consder >, then we wrte the delay as = n + where < (4) (n + 1) +1 Fgure 8 delay on layer + 1 for a dente synchronous system when >. Analogously to (2) and (3) and replacng by gves, see Fgure 8, P(k +1 = n + 1) = h? P(k +1 = n + 2) = =? (? n) =? n (5) We thus can conclude that for every delay on level there are two possble delays for level + 1. Example To llustrate the dente synchronous model, the numercal values of our example are used. Snce 1 = h 1 = 256 > h 2 = 250 t follows from (4) that the delay s 500 or 750 ms. The probabltes for the two delays can now be found from (5) P( d = 500) = 244 250 = 0:9760 P( d = 750) = 6 250 = 0:0240 4. Partally synchronous systems We now ntroduce phase derences,, between the nputs and the outputs for all derent levels, see Fgure 5. For the partally synchronous systems the phase for each layer s constant. The derent possbltes for delays when < are shown n Fgure 9. If a sgnal a) b) c) t n t out a t outb t outc +1 Fgure 9 Delay possbltes for for a partally synchronous system when < ; (a) k = 0, (b) k = 1, and (c) k = 2. enters the layer +1 at tme t n, and the correspondng sgnal exts the layer at t out, then t s ntutvely seen that the delay n layer + 1 s +1 = k +1 + +1 (6)
where k +1 = 0; 1; 2; : : :. Consder the case where. Usng the same dea to that used n the dente synchronous model we nd that for an arbtrary tme the probabltes for the derent cases are found by takng ratos between derent tme ntervals. From (6) and Fgure 9 t s easly found that +1? P(k +1 = 0) = max P(k +1 = 1) =? j +1? j? +1 P(k +1 = 2) = max (7) Note that there are only two possble delays for a constant delay on level, as k = 0 and k = 2 are mutually exclusve. For the case > can be dvded nto = n + where <. Usng the same dea as n dervng (7) but replacng by gves +1? P(k +1 = n) = max P(k +1 = n + 1) =? j +1? j? +1 P(k +1 = n + 2) = max 5. Jonng levels (8) The possble delays on layer L, the bottom layer are gven by k L h L + L. The probablty for any one k s the addtve condtonal probabltes for all tme delay lengths n the layer above. P(k +1 = n) = P(k +1 = nj = +1 )P( = +1 ) + P(k +1 = nj = + +1 )P( = + +1 ) + P(k +1 = nj = 2 + +1 )P( = 2 + +1 ) + : : : (9) Ths expresson s obtaned snce the derent events are mutually exclusve. Maxmum number of tme delays From the analyss above t can be seen that there s a possble maxmum number of tme delays for both dente synchronous systems and partal synchronous systems. Dente synchronous systems For layer 0 there s no tme delay. For level 1 there s one possble tme delay. For level two, two possble delays. Now say for level there are D possble tme delays. Then at layer + 1 there are 2D possble tme delays because for each tme delay on a layer there are two possble tme delays on layer on the layer below, see Secton 4. Thus, for a dente synchronous system the number of possble tme delay values s equal to 2 L?1 where L s equal to the layer number of the last layer. Partally synchronous systems There s no tme delay on layer 0, on layer 1 there are two possble tme delays, and on layer 2 there are four possble tme delays. Thus for each tme delay on a layer there are two possble tme delays on layer on the layer below, by extenson of the results n Secton 4. Ths shows that, for a system whch s partally synchronous, there are 2 L possble tme delay values. Maxmum possble tme delay The theoretcal maxmum occurs when the phases of the nput layers and the output layers all just about lne up. Thus t can be seen that the maxmum tme s equal to double the added delays from all layers except layer 0. A possble delay n layer 0 s then added. Ths can, for nstance, be a computatonal delay. 6. Example Ths example uses our example n Fgure 1 wth three derent layers, as well as two derent phase derences for each layer. The numbers correspond to the smulaton n Nlsson (1998) and Nlsson et al. (1998a),.e. Fgure 3, where h 1 = 256 ms, h 2 = 250 ms, 1 = 166 ms, and 2 = 190 ms. Frst layer 1 s examned. Here t can be seen that there are two possble tme delays, 1 and 1 + h 1 P( 1 = 1 ) = P( 1 = 166) = 166 256 = 0:6484 P( 1 = 1 + h 1 ) = P( 1 = 422) = 90 256 = 0:3516 Possble tme delays n layer 2 correspond to 190 ms and 440 ms due to the rst value of 1 and 440 ms and 690 ms due to the second value of 1. From (9) P( d = 190) = P(k +1 = 0j = 166)P( = 166) = 0:0622 P( d = 440) = P(k +1 = 1j = 166)P( = 166) + P(k +1 = 1j = 422)P( = 166) = 0:6115 P( d = 690) = P(k +1 = 2j = 422)P( = 422) = 0:3263 Fgure 10 shows the estmated hstogram over 2000 samples for the same stuaton as n Fgure 3. The gure conrms the theoretcal calculaton.
7. Asynchronous systems Asynchronous systems are obtaned when the nputs and outputs n the derent layers have not the same samplng perods. Ths mples that the nputs and outputs wll drft wth respect to each other. The pattern for the delays wll now become much more complcated and there wll, n general, be a rcher dstrbuton of delays as opposed to the prevous cases where the delays get a few dstnct values. For nstance, f n our example the nput samplng rate s changed from 250 ms to 260 ms we get the pattern n Fgure 11. The gure shows the estmated hstogram from a smulaton of 2000 samples. The values of the tme delays are separated nto quanta separated by 10 ms; that s, the derence between the nput and output samplng rates. The gure agrees wth the theoretcal dstrbuton. More detals about the dervaton can be found n Bastan (1998). Frequency Frequency 0.5 0 0 0.2 0.4 0.6 0.8 1 Control delay Fgure 10 Estmated hstogram over 2000 samples of the delays for the same example as shown n Fgure 3. 0.03 0.02 0.01 0 0 0.5 1 Control delay Fgure 11 Estmated hstogram over 2000 samples of the delays for the example when the nput samplng rate s changed from 250 ms to 260 ms. 8. Conclusons In ths paper we have shown how the tme delays n nested communcaton loops can be derved and descrbed. It s found the the varatons can be qute large and that the pattern can be very rregular. Ths can make t mportant to consder the delays n the desgn of the controller. Examples n Nlsson (1998) and Bastan (1998) show that t can be advantageous to take the delay varatons nto account n the desgn. Acknowledgments Ths work s partally supported by NUTEK, Swedsh Natonal Board for Industral and Techncal Development, Project Dcosmos P9068-2. References str m, K. J. and B. Wttenmark (1997): Computer-Controlled Systems, thrd edton. Prentce Hall. Bastan, B. (1998): \Analyss of tme delays n synchronous control loops." Master thess ISRN LUTFD2/TFRT--5597--SE. Department of Automatc Control, Lund Insttute of Technology, Lund, Sweden. Chan, H. and U. zguner (1995): \Closed-loop control of systems over a communcatons network wth queues." Internatonal Journal of Control, 62:3, pp. 493{510. Krtolca, R., U. zguner, H. Chan, H. G ktas, J. Wnkelman, and M. Lubakka (1994): \Stablty of lnear feedback systems wth random communcaton delays." Internatonal Journal of Control, 59:4, pp. 925{953. Nlsson, J. (1998): Real- Control Systems wth Delays. PhD thess ISRN LUTFD2/TFRT--1049-- SE, Department of Automatc Control, Lund Insttute of Technology, Lund, Sweden. Nlsson, J. and B. Bernhardsson (1997): \LQG control over a Markov communcaton network." In Proceedngs of the 36th IEEE Conference on Decson and Control, pp. 4586{4591. San Dego. Nlsson, J., B. Bernhardsson, and B. Wttenmark (1998a): \Some topcs n real-tme control." In Proceedngs Amercan Control Conference, pp. 2391{2395. Phladelpha. Nlsson, J., B. Bernhardsson, and B. Wttenmark (1998b): \Stochastc analyss and control of real-tme systems wth random tme delays." Automatca, 34, pp. 57{64. Ray, A. (1994): \Output feedback control under randomly varyng dstrbuted delays." Journal of Gudance, Control, and Dynamcs, 17:4, pp. 701{711.