April, 2018 Sixth Semester Time: Three Hours Answer Question No1 compulsorily Answer ONE question from each unit 1 Answer all questions a Draw the symbol of Zener diode III/IV BTech (Regular) DEGREE EXAMINATION-Schema 14ME605 Mechanical Engineering Electronics and Microprocessors Maximum : 60 Marks (1X12 = 12 Marks) (4X12=48 Marks) (1X12=12 Marks) b c Give the ripple factor of a HWR r=121 Draw the transfer characteristics of N-channel JFET d e Define Op-Amp An operational amplifier is a DC-coupled high-gain electronic voltage amplifier with a differential input and, usually, a single-ended output Draw the comparator circuit using Op-Amp f) Define CMRR The CMRR is defined as the ratio of the powers of the differential gain over the commonmode gain g Convert (110111001010)2 into equivalent Octal system (6712)8
h Give the truth table of two input Ex-OR gate A B 0 0 0 0 1 1 1 0 1 1 1 0 i) Draw the symbols of universal gates A B j) Write any two examples for arithmetic applications arithmetic mean, which is a quantity that is used in a wide variety of applications, such as science, engineering, medicine, statistics and finance k ) Which interrupt has highest priority in 8085? TRAP has the highest priority l) What is the noof flag bits in 8085? Five 2 a UNIT I Construct an N-channel JFET and explain its drain characteristics Junction Field Effect Transistors (JFETs) are a type of FETs (high input impedance devices) which have three terminals namely, Source (S), Gate (G) and Drain (D) These devices are also called voltage controlled devices as the voltage applied at the gate terminal determines the amount of current flowing in-between the drain and the source terminals FETs can either be composed of pn- or Schottky-junction due to which they are called pn JFETs or Metal Semiconductor FETs (MESFETs), respectively Further, the pn JFETs can be classified into two types viz, (i) n-channel JFET and (ii) p-channel JFET, depending on whether the current flow is due to electrons or holes, respectively The schematic of an n-channel JFET along with its circuit symbol is shown in Figure 1 From the layered structure shown by Figure 1a, it is clear that the n-channel JFET has its major portion made of n-type semiconductor The mutually-opposite two faces of this bulk material from the source and the drain terminals Further, it is also seen that there are two relativelysmall p-regions embedded into this substrate which are internally joined together to form the gate terminal Thus, here, the source and the drain terminals are of n-type while the gate is of p-type Due to this, two pn junctions will be formed within the device, whose analysis reveals the mode in which the JFET works Further the circuit symbol shown by Figure 1b has an arrow pointing towards the device at its Gate terminal which indicates the direction in which the current would flow, provided the pn junction is forward biased 8M
Working of n-channel JFET In n-channel JFET, the majority charge carriers will be the electrons as the channel formed inbetween the source and the drain is of n-type Further, the working of these devices depends upon the voltages applied at its terminals (Figure 2) Case I: Consider the case where no voltage is applied to the device ie VDS = 0 and VGS = 0 At this state, the device will be idle and no current flows through it ie IDS = 0 Case II: Now consider that the drain terminal of the device is connected to the positive terminal of the battery while its negative is connected to the source ie VDS = +ve However let the gate terminal remain at unbiased state, which means VGS = 0 At this instant, the electrons within the n-substrate of the device start moving towards the drain being attracted by the positive force exerted by the battery At the same time, the electron will also be repelled from the source as it is connected to the negative terminal of the voltage supply This results in a net flow of current from drain to source (as per conventional direction) whose value is restricted only by the resistance offered to it by the channel Further, it is seen that the increase in VDS increases the current flowing through the device at an initial state which can be termed to be JFET's Ohmic region However, it is to be noted that the increase in VDS also causes an increase in the width of the depletion regions surrounding the pn junctions This inturn causes the channel width to reduce, thereby increasing its resistance This phenomenon continues till both of the depletion regions grow upto an extent wherein they almost seem to touch each other, a condition referred to as pinch-off The corresponding value of VDS is referred to as pinch-off voltage, VP Nevertheless, even in this case, a narrow channel with high current density exists within the device due to which IDS will get saturated to a level of IDSS as indicated in Figure 2 It is this behaviour of the JFET which causes it to behave as a constant current source Case III: Next, for the set-up described in Case II, let us add the voltage source at the gate terminal such that the gate is negative wrt source ie VGS = -ve while VDS is +ve In this case, the device behaves in a way very-similar to that in Case II, but for a lower value of VDS This means that the pinch-off and the saturation occur quite earlier and are decided by the negative potential applied at the gate ie more negative the VGS, earlier the pinch-off due to which earlier will be the saturation, reducing IDSS (Figure 3) As the phenomenon continues, it is seen that a condition arises wherein the saturation level of the drain-to-source current I DS occurs right for a value of 0 ma This means that there is no current flow through
the device and essentially the device will turn OFF The value of VDS for which this happens will be nothing but the negative pinch-off voltage ie VDS = -VP b Find the dynamic resistance of a PN junction diode at a forward current of 2mA Assume VT=25mA 4M 3 (OR) a Explain the input characteristics of an NPN transistor 7M
b Derive the expressions for average, RMS currents and ripple factor of a FWR Average value of current, 5M = RMS value of current, = = = =
= Full Wave Rectifier: RF=0482 4 a UNIT II Describe the application of Op-Amp as current to voltage convertor Following figure shows the circuit diagram of the current to voltage converter It uses simple operational amplifier and a feedback resistance The output voltage of operational amplifier is directly proportional to the current given to the inverting terminal of the op amp 6M A current to voltage converter will produce a voltage proportional to the given current This circuit is required if your measuring instrument is capable only of measuring voltages and you need to measure the current output If your instrument or data acquisition module (DAQ) has a input impedance that is several orders larger than the converting resistor, a simple resistor circuit can be used to do the conversion However, if the input impedance of your instrument is low compared to the converting resistor then the following opamp circuit should be used To analyse the current to voltage converter by inspection, if we apply KCL to the node at V- (the inverting input) and let the input current to the inverting input be I-, then Vout V Rf=Ip+I (1) since the output is connected to V- through Rf, the opamp is in a negative feedback configuration Thus V =V+=0 (2) and assuming that I- is 0 and simplifying, Vout=IpRf (3) One example of such an application is using the photodiode sensor to measure light intensity The output of the photodiode sensor is a current which changes proportional to the light intensity Another advantage of the opamp circuit is that the voltage across the photodiode (current source) is kept constant at 0V
b Derive an expression for an output voltage of a summing Operational amplifier using inverting amplifier configuration 6M Summing amplifier is a type operational amplifier circuit which can be used to sum signals The sum of the input signal is amplified by a certain factor and made available at the output Any number of input signal can be summed using an opamp The circuit shown below is a three input summing amplifier in the inverting mode Summing amplifier circuit In the circuit, the input signals Va,Vb,Vc are applied to the inverting input of the opamp through input resistors Ra,Rb,Rc Any number of input signals can be applied to the inverting input in the above manner Rf is the feedback resistornon inverting input of the opamp is grounded using resistor Rm RL is the load resistor By applying kirchhoff s current law at not V2 we get, Ia+Ib+Ic = If+Ib Since the input resistance of an ideal opamp is close to infinity and has infinite gain We can neglect Ib & V2 There for Ia+Ib+Ic = If (1) Equation (1) can be rewritten as (Va/Ra) + (Vb/Rb)+ (Vc/Rc) = (V2-Vo)/Rf Neglecting Vo, we get Va/Ra + Vb/Rb + Vc/Rc = -Vo/Rf Vo = -Rf ((Va/Ra)+(Vb/Rb)+(Vc/Rc)) Vo = -((Rf/Ra )Va + (Rf/Rb) Vb + (Rf/Rc) Vc) (2) If resistor Ra, Rb, Rc has same value ie; Ra=Rb=Rc=R, then equation (2) can be written as Vo = -(Rf/R) x (Va + Vb +Vc) (3) If the values of Rf and R are made equal, then the equation becomes, Vo = -(Va + Vb +Vc) 5 a (OR) Draw the circuit of Op-Amp as subtractor and find the expression for output The subtraction of the two input voltages is possible with the help of subtractor The subtractor using op-amp is shown in figure below It is also called as difference amplifier 6M
The input signals applied are V1 and V2Let us assume that the non-inverting terminal is at potential V Due to virtual ground concept, the inverting terminal appears to be at the same potential V as shown in the circuit diagram Let the current flowing through resistance R1 and R2 are I1 and I2 respectively Since input current to the op-amp is zero, the two currents flows through the resistance Rf as shown in circuit diagram above The current I2 is given as From the above equation voltage V can be calculated as The current I1 is given as Simplify the equation,
Substituting the voltage V from the equation we get, If R1=R2 If R1=R2=Rf Thus at the output we get subtraction of the two input voltages The subtractor circuits are used to solve various mathematical equations b Design an adder circuit using an Op-Amp to get the output expression as Vout= -(V1+5V2+25V3) Where V1,V2,V3 are the inputs Given that Rf=50 KΩ 6M The inverting operational amplifier that the inverting amplifier has a single input voltage, (Vin) applied to the inverting input terminal If we add more input resistors to the input, each equal in value to the original input resistor, (Rin) we end up with another operational amplifier circuit called a Summing Amplifier, summing inverter or even a voltage adder circuit as shown below In this simple summing amplifier circuit, the output voltage, ( Vout ) now becomes proportional to the sum of the input voltages, V1, V2, V3, etc Then we can modify the original equation for the inverting amplifier to take account of these new inputs thus:
However, if all the input impedances, ( Rin ) are equal in value, we can simplify the above equation to give an output voltage of: Summing Amplifier Equation 6 a UNIT III Show that the Excess-3 code is a self complimenting code with an example 6M 0 is complement of 15, 1 is complement of 14, 2 is complement of 13 b What are the universal gates? Implement all basic gates using universal gates 6M Universal gates - NAND and NOR NAND gate is a universal gate since it can implement the AND, OR and NOT functions
Using only NOR Gate NOR gate is a universal gate since it can implement the AND, OR and NOT functions 7 (OR) a Design a full adder using two half adders 4M
b Briefly describe R-S, J-K, D and T- type flip-flops 8M
8 a UNIT IV Explain the difference between JMP and CALL A JMP instruction permanently changes the program counter A CALL instruction leaves information on the stack so that the original program execution sequence can be resumed A jump just transfers control to a new place in memory, and continues from there as if nothing unusual had happened - the program counter is simply loaded with a new value A call first saves the processor state on the stack, including the current program counter, then jumps to a new place in memory If that code executes a return, then the processor state is restored from the stack, including the program counter, meaning that the processor jumps back to the place it was at when it made the call (or just past it, in fact) This allows us to implement subroutines (known as functions or procedures in higher level languages) which is a vital necessity in practical programming 4M b Write an assembly language program for finding the largest number in a series Program 8M MEMORY LABEL MNEMONIC HEX COMMENT CODE 4400 LXI H,4200 21 Load the array size to the 4401 00 HL pair 4402 42 4403 MOV B,M 46 Copy the array size to B register 4404 INX H 23 Increment the memory 4405 MOV A,M 7E Copy the first data to the Accumulator 4406 DCR B 05 Decrement the Array size by 1 4407 LOOP INX H 23 Increment the memory 4408 CMP M BE Compare accumulator content and memory 4409 JNC AHEAD D2 Jump on no carry to label 440A 0D AHEAD 440B 44 440C MOV A,M 7E Copy the memory content to the accumulator 440D AHEAD DCR B 05 Decrement register B by 1 440E JNZ LOOP C2 440F 07 Jump on non-zero to label 4410 44 LOOP 4411 STA 4300 32 4412 00 4413 43 4414 HLT 76 Program ends Store accumulator content to 4300 Algorithm 1) Load the address of the first element of the array in HL pair 2) Copy the count to register B 3) Increment the pointer 4) Get the first data in accumulator 5) Decrement the count 6) Increment the pointer
7) Compare the content of memory addressed by HL pair with that of Accumulator] 8) If Carry = 0, go to step 10 or if Carry = 1 go to step 9 9) Copy the content of the memory addressed by HL to Accumulator 10) Decrement the count 11) Check for Zero of the count If Zero Flag (ZF) = 0, go to step 6, or if ZF = 1 go to next step 12) Store the largest data in memory 13) Terminate the program Observation Input at 4200 : 05H --------------- Array Size 4201 : 0AH 4202 : F1H 4203 : 1FH 4204 : 26H 4205 : FEH Output at 4300 : FEH 9 a (OR) Write an assembly language program to convert a BCD number into its equivalent decimal form 8M
b What are the operations performed by ALU of 8085 ALU performs Athematic and logical operations 1 Addition 2 Subtraction 3 AND 4 OR 5 NOT 6 XOR 4M Scheme of Evaluation 1 a) Symbol of zener diode b) 121 c) transfer characteristics graph d) forward current gain in common emitter configuration e) comparator circuit f) Ratio of common mode gain to the differential mode gain g) (6712)8 h) Truth table of Ex-OR gate i) Symbols of NAND and NOR gates j) ADD, SUB, MUL, DIV any two k) TRAP l) Five 2 a) Schematic of construction ------ 3M Explanation ------ 3M Graph ------ 2M b) Formula for dynamic resistance ------ 2M Answer ------ 2M 3 a) circuit diagram ------ 2M Characteristic plot ------ 2M Explanation ------ 3m b) Circuit diagram ------ 2M Average, RMS and ripple factor ------ 3M 4 a) Circuit diagram ------ 3M Explanation ------ 3M b) Circuit diagram ------ 3M Explanation ------ 3M 5 a) Circuit diagram ------ 3M Derivation of output expression ------ 3M b) Design equations ------ 3M Circuit diagram ------ 3M 6 a) Excess-3 code for an example ------ 3M Compliment of the example ------ 2M Proof ------ 1M b) Universal gates ------ 1M implementation of OR, AND, EX-OR, EX-NOR, NOT ------ 5M 7 a) Full adder truth table ------ 2M
Logic diagram using half adders ------ 2M b) Four flip-flop diagrams ------ 4M Truth tables ------ 4M 8 a) Syntax for JMP and CALL instructions ------ 2M Differences ------ 2M b) Assembly language program ------ 8M 9 a) Assembly language program ------ 8M b) Functions of ALU ------ 4M