458 / 1004 The Electronics Readout and Measurement of Parameters of a Monitor System Abdolkazem Ansarinejad 1, Roberto Cirio 2 1 Physics and Accelerators School, Nuclear Science and Technology Research Institute, Tehran 2 Experimental Physics Department, University of Torino, Torino, Italy Abstract In a protontherapy center one of the main issues is to assure the correct delivery of the dose to the patient. The beam has to be monitored in a non-invasive way downstream of the spreading system and its position, shape and intensity have to be measured just before the target in order to feedback the relevant beam parameters to the upstream elements of the beam line. The electronics read-out for the beam monitor system is based on an ASIC chip- TERA06, The integrated circuit as the current-to-frequency converter, built in 0.8 μm CMOS technology, 64-channel wide dynamic range charge measurement at high converter frequency (20 MHz), developed by the Torino medical physics group. The pedestal and quantum charge tests on the FrontEnd- TERA06 cards have been presented good results useful to development of front-end electronics. Keywords: Front-end electronics, monitor system, background current, quantum charge Introduction Torino University and Istituto Nazionale Fisica Nucleare (INFN) in cooperation with Centro Nazionale Adroterapia Oncologica (CNAO) work on development of a detector which can be used both as a monitor chamber and as part of a dosimetry system. The detector is based on a parallel plate ionization chamber with the anode subdivided into strips or pixels. The electronics read-out for the CNAO beam monitor system is based on the TERA chip which is part of a development line carried out by the Torino group. It is a VLSI recycling integrator, with 64 channels converting the integrated charge into counts. A dead time free operation allows latching at the same time all the counters in registers that are read in sequence without stopping the charge collection. The pedestal rate is less than 1 count/sec. The most important features of these versions are summarized in table 1. On each side of detectors(pixels- The 1024 tracks from the pixels are fanned out to the four sides) are mounted two motherboards (FrontEnd-TERA06), each one housing two 64-channel TERA06 chips and all the electronics needed to receive and to send the signal to the data acquisition system [1], [2]. Table 1: Main features of TERA 06 Technology CMOS 0.8 µm Die size 6mm 7mm Number of channels 64 Max clock frequency Input current Latch Max I-f converter frequency 20 MHz unipolar Free dead time read-out 5MHz Non Linearity <1% Materials and method The design of TERA06 is based on the recycling integrator architecture. With reference to Figure 1, the current from each pixel is integrated and a number of pulses proportional to the charge collected by an individual channel which are sent to a 16-bit counter. the input current is integrated over a 600 ff capacitor via an Operational Transconductance Amplifier (OTA). The integrator output is a positive ramp which is compared with a threshold voltage by a synchronous comparator. When the comparator fires, a calibrated current pulse is sent to the circuit input via a pulse generator. Thus a fixed amount of charge (charge quantum, Q) is subtracted from the main integrator capacitor. This results in a sharp decrease of the voltage across 600 ff capacitor, proportional to the charge injected by the subtraction circuit[3].
459 / 1004 Figure 1: Channel scheme of TERA06 IC. After charge subtraction, the voltage at OTA output ramps up again, and the process is repeated, thus giving a saw tooth waveform. For each charge subtraction a pulse is also sent to the digital counter. The frequency of the pulses is proportional to the current where the relation between output frequency (f ) and input current (I IN ) is given by the ratio of the input current and the charge quantum (Q C ): f= I in /Q c The number of pulses generated in the measurement time multiplied by the value of the charge quantum Q C gives the total charge read-out from the detector. The charge quantum Q C represent therefore the quantization error. The charge quantum is generated by sending a voltage pulse over a 200 ff capacitor (called subtraction capacitor C sub ). The charge quantum value is defined by: Q = C sub V pulse where V pulse is the amplitude of the pulse generated by a pulse generator which can be externally set at a maximum value of 5 V. A voltage variation V across the subtraction capacitor correspond to a voltage variation of: V 1 = V C sub /C int across the integration capacitor. This voltage variation is applied at the input of the comparator, and has to be able to switch it back. The maximum input current is limited by the pulse generator state machine. This circuit needs 4 clock cycles to generate each pulse. The maximum frequency of the converter is therefore one quarter of 20 MHz clock frequency. At any given time all the 64 counters can be latched and the results are stored in a register and the 64 registers output are multiplexed over a 16 bit output bus signal. In Figure 2, the ASIC architecture is showed[3]. Figure 2: The TERA06 architecture [4.9]. FrontEnd-TERA06, Figure 3, shows the mother boardwhere two TERA06 IC s and all electronics needed to receive and to send the signal to the data acquisition system are mounted. Figure 3, Snapshot of the FrontEnd-TERA06 card. The card is composed by six layers, three for the reference voltages (V CC, GND and OTA REF ) and three for the signal tracks. Figure 4 and 5, show the most significant layers of the card, where the tracks of the IC s input are housed. Figures show how, to avoid the leakage currents, a guard ring are carefully positioned around the connections between the IC s input and the connectors which are used to connect the card to MOPI detector. The guard rings are polarized to the same voltage of the OTA reference voltage (OTA REF =2.05V). Figure 4: Exploded view of the top layer of FrontEnd-TERA06 card.
460 / 1004 Table 3, shows the mean value and the standard deviation of the charge quantum for each card. For each card, the single value of the charge quantum is computed as mean value on the 128 charge quantum of channels of two IC s housed on the card. Table 7.1 shows Summary of test results on the forty FrontEnd-TERA06 cards dedicated for the monitor system[4], [5]. Discussion Figure 5: Exploded view of the layer # 2 of FrontEnd-TERA06 card. Figure 6: The block diagram of the FrontEnd-TERA06 card. Figure 6, shows the block diagram of the card. The bus from the motherboard to the data acquisition includes 16 data lines and the bus from the DAQ to the card includes: 11 address lines to multiplex all 1024 pixels (A10-A7 to select the card, A6 to select the ASIC and A5-A0 to select the channel) and others three lines: an analog reset (rsta) to discharge the integrator capacitor at the beginning of the operations, a digital reset (rstd) to clear all the counters, and a latch to store them. Risults The performance of the cards has been studied by measuring of the background currents and the charge quantum value. The second and third columns of Table 2 show respectively the mean value and the standard deviation of the counts per second for each board. The fourth and fifth column show the mean value and the standard deviation of the background currents where their values are less than 200 fa. The differences between the set value (400 fq) and the experimental values can be attributed to the presence of the parasitic capacitor inside to TERA IC s. The relevant features of the front-end circuit are summarized below: - charge corresponding to a pulse (charge quantum) can be adjusted between 100 fc and 800 fc via an externally regulated voltage; - maximum pulse frequency is 5 MHz which results in a limit for the input current of 4 µα for a charge quantum set at 800 fc and 500 na for a charge quantum set at 100 fc; - linearity from 100 pa up to the maximum current is within 1%; - dark current counting rate is at the level of ~1 Hz; - charge quantum spread is less than 1%; - the change of charge quantum as function of temperature in the range 20-30 C is less than 1 fc/ C for a charge quantum set at 600 fc; - polarization voltage of the chip is +5 V; - no dead time is introduced during read-out because the charge quantum is subtracted from the integrator input as the current from the detector flows in and the latch located at the output of the counters does not affect the counting itself. In the Pedestal Test, all the electronics boards have shown to operate correctly: the channel counts mean value is less than 1 Hz. In the Quantum Test, the FrontEnd-TERA06 that have been tested to show the appropriate response and stability in time. The current values are obtained using the charge quantum and the counts per second measured. The charge quantum has been measured by injecting a fix current (-100 na) to all channels of the chips. To measure the leakage currents the IC's inputs are left open. For this measurement the charge quantum was set to 400 fc. Data were taken at regular time intervals for several seconds and the counts per second of every channel were recorded. For each card we have computed an average of the counts per second obtained from each channel [6]. Conclusion The background currents are more the 5 orders of magnitude smaller than the typical currents associated to the therapeutic beam, which are of the order of 10 na. The mean value of the quantum charge has been compute for each electronics board, showing an uniformity better than 1.3%.
461 / 1004 Table 2: Background currents of the FrontEnd-TERA06 cards. Table 3: Mean value and standard deviation of the charge quantum of the FrontEnd-TERA06 cards. Table 4: Summary of pedestal and quantum charge test results on the forty FrontEnd-TERA06 cards
462 / 1004 References [1] A Ansarinejad, A Attili, F Bourhaleb, R Cirio, M Donetti, M A Garella, F Marchetto,V Monaco, J Pardo, A Pecka, C Peroni,, R Sacch "The on-line detectors of the beam delivery system for Centro Nazionale di Adroterapia Oncologica (CNAO)" Nuclear Physics B 197, 186 (2009) [2] Amaldi U., "CNAO- the Italian centre for light-ion therapy, Radiology and Oncology", 73(2), (2005), S191-S201. [3] G. C. Bonazzola," Performances of a VLSI wide dynamic range current-to-frequency converter for strip ionization chambers" Nuclear Instruments and Methods in Physics Research A 405 (1998) 111. [4] G. Mazza, A. La Rosa, A Attili, F Bourhaleb, R Cirio, M Donetti, M A Garella, F Marchetto,V Monaco, J Pardo, A Pecka, C Peroni,, R Sacch," A 64-channel wide dynamic range charge measurement ASIC for strip and pixel ionization detectors". IEEE Transactions on Nuclear Science, Vol. 52, NO. 4, (August 2005) 847-853 [5] La Rosa A, A Attili, F Bourhaleb, R Cirio, M Donetti, M A Garella, F Marchetto,V Monaco,C Peroni,, R Sacch "A pixel ionization chamber used as beam monitor at the Institut Curie Centre de Protontherapie de Orsay (CPO)",Nucl. Instr. and Meth. A 565,833 (2006) [6] La Rosa A. A Attili, F Bourhaleb, R Cirio, M Donetti, M A Garella, F Marchetto,V Monaco,C Peroni,, R Sacch, " Development of a pixel ionization chamber for beam monitor in proton therapy", Nucl.Instr. Meth. A 572, 257(2007)