IWORID J. Schmitz page 1 Wafer-level CMOS post-processing Jurriaan Schmitz
IWORID J. Schmitz page 2 Outline Introduction on wafer-level post-proc. CMOS: a smart, but fragile substrate Post-processing steps System examples Conclusions
IWORID J. Schmitz page 3 45 years of integrated circuits Enormous skill in micro-manufacturing High performance computing Solid-state memories Can we do more with this skill than number crunching and memorizing? One approach: wafer level post-processing
IWORID J. Schmitz page 4 Wafer-level post-processing Add process steps only here
There s plenty of room at the top IWORID J. Schmitz page 5
IWORID J. Schmitz page 6 The idea of CMOS post-proc. (1) Wafer-scale post-processing: Chips are finished and fully functional No intrusion into clean IC fab Still benefit from planar technology (yield, efficiency, cost, existing toolkit ) A microchip is fragile, so take care!
IWORID J. Schmitz page 7 The idea of CMOS post-proc. (2) Attractive when: The monolithic solution is cheaper (saving assembly & testing expenses) The monolithic solution outperforms hybrid technologies Size matters See www.akustica.com
IWORID J. Schmitz page 8 Is post-processing trivial? 1. The chip is vulnerable: Heat > 400 ºC destroys the metallization Plasma charging destroys the MOSFETs Mechanical stress changes components H 2 passivation must be maintained 2. Packaging has to be re-invented. Without package: contamination 3. How to deposit high-quality thin films?
IWORID J. Schmitz page 9 High temperature in IC fabrication Heat is necessary during IC fabrication: To oxidise silicon To diffuse impurities in silicon To repair silicon lattice damage To activate impurities To deposit materials by CVD To initiate reactions, e.g. Ti+2Si TiSi 2
IWORID J. Schmitz page 10 Deposition Oxidation Anneal Pad oxide Si3 N 4 HDP trench fill STI sidewall Si3 N 4 sacox Well anneal Gate oxide Gate RTA (predoping) Poly reoxidation Extension RTAs Si3 N 4 spacer Gate/s/d RTA Si3 N 4 deopsition Locsal RTA 2nd silicide RTA 1100 1000 900 800 700 time Temperature ( C)
IWORID J. Schmitz page 11 Thermal budget of an IC Keep it cool(er) Transistor ready: stop diffusion wires ready: avoid Al melt Soldering ready: avoid solder melt Temperature (ºC) Front-end 1000 Back-end 500 Packaging 300 Soldering 200 Time
IWORID J. Schmitz page 12 Thermal budget trend Smaller dimension transistors: diffusion should be reduced High-temperature steps are reduced in time and temperature, where possible New machines (RTP, laser) New materials (SiLK) New techniques (ICP-CVD)
IWORID J. Schmitz page 13 (Post) process-induced damage Mechanical damage (e.g. scratches) Electrostatic discharges Plasma damage in IC technology: Plasma etching Plasma-assisted depositions (PECVD) Photoresist removal All three: hard to do without!
IWORID J. Schmitz page 14 Plasma etching Ions bombarding the surface Radicals reacting with atoms
IWORID J. Schmitz page 15 Plasma etching induced damage High anisotropy vertical profiles Charge pile-up can lead to discharging inside the chip plasma SiO 2 Wafer + + + + + + + MOS gate
The antenna effect IWORID J. Schmitz page 16
IWORID J. Schmitz page 17 Plasma processing induced damage Suppression: Adopt design rules (unfit for wafer-scale post-processing) Tune the plasma settings Use other approach (e.g. remove photoresist in a liquid)
IWORID J. Schmitz page 18 Other alerts H 2 passivation essential for MOSFET Final alloy step (30 400 ºC in H 2 /N 2 ) Hot processing leads to H 2 outgassing Mechanical stress should stay low Metal ions can ruin the chip, even at room temperature! Stick to IC mfg. rules Eijkelboom et al., ECN 2002
May we introduce a new material? (source: www.intel.com) IWORID J. Schmitz page 19
IWORID J. Schmitz page 20 What is allowed above CMOS? All backend tricks can be repeated! Metal deposition Dielectric deposition CMP Patterning Semiconductors? Polymers? Suspended structures?
IWORID J. Schmitz page 21 Example: Medipix2 modification Technique: wafer-level lift-off lithography, using aluminum Result: Medipix2 still fully functional Good for ball-grid-arrays Good for gaseous particle detection
IWORID J. Schmitz page 22 CMOS post-proc. steps (3) Chemical Mechanical Polishing allows to pattern any new material E.g. piezo-electric films, ferro-electrics
IWORID J. Schmitz page 23 Dielectric and semiconductor thin films Some activation energy is necessary to form strong bonds Low-temp depositions: ECR-CVD, ICP-CVD Laser crystallization?
IWORID J. Schmitz page 24 Suspended structures Sacrificial material: SU8 SiGe (T. J. King et al., UCB) BCB Parylene Structural material: rigidity residual stress impact on IC
IWORID J. Schmitz page 25 wlpp microsystems CMOS image sensor LCOS Micromirrors Ultrasound imaging detectors SIAM X-ray detectors Integrated Micromegas Integrated microchannel plate
IWORID J. Schmitz page 26 The CMOS image sensor (= monolithic active pixel sensor) Incident light lens R/G/B filter lens R/G/B filter Standard CMOS photodiode silicon photodiode
IWORID J. Schmitz page 27 Liquid crystal on silicon (LCOS) Transparent electrode Liquid crystal Mirror electrode Standard CMOS silicon
TI s micromirrors IWORID J. Schmitz page 28
IWORID J. Schmitz page 29
IWORID J. Schmitz page 30 Ultrasound detector arrays Sensant (now acquired by Siemens)
IWORID J. Schmitz page 31 Monolithic X-ray detector SIAM collaboration http://asi-hdet-project.web.cern.ch/asi-hdet-project/
IWORID J. Schmitz page 32 The GOSSIP gaseous detector HV cathode V. Carballo Blanco et al., IWORID 2006 Naked Medipix2 chip
IWORID J. Schmitz page 33 Integrated microchannel plates Principle: J. Vallerga et al., IWORID 2004 Wafer-level manufacturing: Porous alumina? Naked Medipix2 chip J. Melai et al., IWORID 2006
IWORID J. Schmitz page 34 Conclusions IC Technology now offers a wide range of manufacturing techniques Computing and data storage + extra s Many new microsystems under study Our focus: systems with high internal data rates wiring is not an option
IWORID J. Schmitz page 35 Acknowledgements Thanks to: The IWORID committee Dutch Technology Foundation STW Our academic and industrial partners My coworkers