LT39 Series 3µA I Q, 2mA Low Dropout Linear Reguators FEATURES n Utraow Quiescent Current: 3μA n Input otage Range: 1. to 2 n Output Current: 2mA n Dropout otage: 28 n Adjustabe Output ( ADJ = OUT(MIN) = ) n Fixed Output otages: 1.2, 1.5, 1.8, 2.5, 3.3, 5 n Output Toerance: ±2% Over Load, Line and Temperature n Stabe with Low ESR, Ceramic Output Capacitors (1μF minimum) n Shutdown Current: <1μA n Current Limit Protection n Reverse-Battery Protection n Therma Limit Protection n 8-Lead SC7 and 2mm 2mm DFN Packages APPLICATIONS n Low Current Battery-Powered Systems n Keep-Aive Power Suppies n Remote Monitoring Utiity Meters Hote Door Locks DESCRIPTION The LT 39 Series are micropower, ow dropout votage (LDO) inear reguators. The devices suppy 2mA output current with a dropout votage of 28. No-oad quiescent current is 3μA. Ground pin current remains at ess than 5% of output current as oad increases. In shutdown, quiescent current is ess than 1μA. The LT39 reguators optimize stabiity and transient response with ow ESR ceramic capacitors, requiring a minimum of ony 1μF. The reguators do not require the addition of ESR as is common with other reguators. Interna protection circuitry incudes current imiting, therma imiting, reverse-battery protection and reversecurrent protection. The LT39 Series are idea for appications that require moderate output drive capabiity couped with utraow standby power consumption. The device is avaiabe in fixed output votages of 1.2, 1.5, 1.8, 2.5, 3.3 and 5, and as an adjustabe device with an output votage range down to the reference. The LT39 is avaiabe in the -ead DFN and 8-ead SC7 packages. L, LT, LTC, LTM, Linear Technoogy and the Linear ogo are registered trademarks of Linear Technoogy Corporation. A other trademarks are the property of their respective owners. TYPICAL APPLICATION 3.3, 2mA Suppy with Shutdown Dropout otage/quiescent Current IN 3.75 TO 2 1μF IN OUT LT39-3.3 SHDN GND 1μF OUT 3.3 2mA 39 TA1a DROPOUT OLTAGE () 5 I LOAD = 2mA 5. 45 4.5 4 3 25 2 15 1 I Q 4. 35 DROPOUT 3.5 OLTAGE 3. 2.5 2. 1.5 1. QUIESCENT CURRENT (μa) 5.5 5 25 25 5 75 1 125 15 39 TA1b 39fd 1
LT39 Series ABSOLUTE MAXIMUM RATINGS (Note 1) IN Pin otage...±22 OUT Pin otage...±22 Input-to-Output Differentia otage...±22 ADJ Pin otage...±22 SHDN Pin otage (Note 8)...±22 Output Short-Circuit Duration... Indefinite Operating Junction Temperature Range (Notes 2, 3) (E, I Grades)... 4 C to 125 C Storage Temperature Range... 5 C to 15 C Lead Temperature: Sodering, 1 sec SC8 Package Ony... 3 C PIN CONFIGURATION ADJ/NC* OUT OUT 1 2 3 TOP IEW 7 GND SHDN DC PACKAGE -LEAD (2mm 2mm) PLASTIC DFN T JMAX = 125 C, θ JA = 5 C/W TO 85 C/W** EXPOSED PAD (PIN 7) IS GND, MUST BE SOLDERED TO PCB 5 4 IN SHDN 1 GND 2 GND 3 GND 4 TOP IEW 8 NC 7 ADJ/NC* OUT 5 IN SC8 PACKAGE 8-LEAD PLASTIC SC7 T JMAX = 125 C, θ JA = 75 C/W TO 95 C/W** * The ADJ pin is not connected in fi xed output votage versions. ** See the Appications Information section. ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT39EDC#PBF LT39EDC#TRPBF LCQX -Lead (2mm 2mm) Pastic DFN 4 C to 125 C LT39IDC#PBF LT39IDC#TRPBF LCQX -Lead (2mm 2mm) Pastic DFN 4 C to 125 C LT39EDC-1.2#PBF LT39EDC-1.2#TRPBF LDTW -Lead (2mm 2mm) Pastic DFN 4 C to 125 C LT39IDC-1.2#PBF LT39IDC-1.2#TRPBF LDTW -Lead (2mm 2mm) Pastic DFN 4 C to 125 C LT39EDC-1.5#PBF LT39EDC-1.5#TRPBF LDB -Lead (2mm 2mm) Pastic DFN 4 C to 125 C LT39IDC-1.5#PBF LT39IDC-1.5#TRPBF LDB -Lead (2mm 2mm) Pastic DFN 4 C to 125 C LT39EDC-1.8#PBF LT39EDC-1.8#TRPBF LDKC -Lead (2mm 2mm) Pastic DFN 4 C to 125 C LT39IDC-1.8#PBF LT39IDC-1.8#TRPBF LDKC -Lead (2mm 2mm) Pastic DFN 4 C to 125 C LT39EDC-2.5#PBF LT39EDC-2.5#TRPBF LDTY -Lead (2mm 2mm) Pastic DFN 4 C to 125 C LT39IDC-2.5#PBF LT39IDC-2.5#TRPBF LDTY -Lead (2mm 2mm) Pastic DFN 4 C to 125 C LT39EDC-3.3#PBF LT39EDC-3.3#TRPBF LDKD -Lead (2mm 2mm) Pastic DFN 4 C to 125 C LT39IDC-3.3#PBF LT39IDC-3.3#TRPBF LDKD -Lead (2mm 2mm) Pastic DFN 4 C to 125 C LT39EDC-5#PBF LT39EDC-5#TRPBF LDKF -Lead (2mm 2mm) Pastic DFN 4 C to 125 C LT39IDC-5#PBF LT39IDC-5#TRPBF LDKF -Lead (2mm 2mm) Pastic DFN 4 C to 125 C 2 39fd
LT39 Series ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT39ESC8#PBF LT39ESC8#TRPBF LCQY 8-Lead Pastic SC7 4 C to 125 C LT39ESC8-1.2#PBF LT39ESC8-1.2#TRPBF LDTX 8-Lead Pastic SC7 4 C to 125 C LT39ESC8-1.5#PBF LT39ESC8-1.5#TRPBF LDC 8-Lead Pastic SC7 4 C to 125 C LT39ESC8-1.8#PBF LT39ESC8-1.8#TRPBF LDKG 8-Lead Pastic SC7 4 C to 125 C LT39ESC8-2.5#PBF LT39ESC8-2.5#TRPBF LDTZ 8-Lead Pastic SC7 4 C to 125 C LT39ESC8-3.3#PBF LT39ESC8-3.3#TRPBF LDKH 8-Lead Pastic SC7 4 C to 125 C LT39ESC8-5#PBF LT39ESC8-5#TRPBF LDKJ 8-Lead Pastic SC7 4 C to 125 C LEAD BASED FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT39EDC LT39EDC#TR LCQX -Lead (2mm 2mm) Pastic DFN 4 C to 125 C LT39IDC LT39IDC#TR LCQX -Lead (2mm 2mm) Pastic DFN 4 C to 125 C LT39EDC-1.2 LT39EDC-1.2#TR LDTW -Lead (2mm 2mm) Pastic DFN 4 C to 125 C LT39IDC-1.2 LT39IDC-1.2#TR LDTW -Lead (2mm 2mm) Pastic DFN 4 C to 125 C LT39EDC-1.5 LT39EDC-1.5#TR LDB -Lead (2mm 2mm) Pastic DFN 4 C to 125 C LT39IDC-1.5 LT39IDC-1.5#TR LDB -Lead (2mm 2mm) Pastic DFN 4 C to 125 C LT39EDC-1.8 LT39EDC-1.8#TR LDKC -Lead (2mm 2mm) Pastic DFN 4 C to 125 C LT39IDC-1.8 LT39IDC-1.8#TR LDKC -Lead (2mm 2mm) Pastic DFN 4 C to 125 C LT39EDC-2.5 LT39EDC-2.5#TR LDTY -Lead (2mm 2mm) Pastic DFN 4 C to 125 C LT39IDC-2.5 LT39IDC-2.5#TR LDTY -Lead (2mm 2mm) Pastic DFN 4 C to 125 C LT39EDC-3.3 LT39EDC-3.3#TR LDKD -Lead (2mm 2mm) Pastic DFN 4 C to 125 C LT39IDC-3.3 LT39IDC-3.3#TR LDKD -Lead (2mm 2mm) Pastic DFN 4 C to 125 C LT39EDC-5 LT39EDC-5#TR LDKF -Lead (2mm 2mm) Pastic DFN 4 C to 125 C LT39IDC-5 LT39IDC-5#TR LDKF -Lead (2mm 2mm) Pastic DFN 4 C to 125 C LT39ESC8 LT39ESC8#TR LCQY 8-Lead Pastic SC7 4 C to 125 C LT39ESC8-1.2 LT39ESC8-1.2#TR LDTX 8-Lead Pastic SC7 4 C to 125 C LT39ESC8-1.5 LT39ESC8-1.5#TR LDC 8-Lead Pastic SC7 4 C to 125 C LT39ESC8-1.8 LT39ESC8-1.8#TR LDKG 8-Lead Pastic SC7 4 C to 125 C LT39ESC8-2.5 LT39ESC8-2.5#TR LDTZ 8-Lead Pastic SC7 4 C to 125 C LT39ESC8-3.3 LT39ESC8-3.3#TR LDKH 8-Lead Pastic SC7 4 C to 125 C LT39ESC8-5 LT39ESC8-5#TR LDKJ 8-Lead Pastic SC7 4 C to 125 C Consut LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a abe on the shipping container. For more information on ead free part marking, go to: http://www.inear.com/eadfree/ For more information on tape and ree specifi cations, go to: http://www.inear.com/tapeandree/ 39fd 3
LT39 Series ELECTRICAL CHARACTERISTICS The denotes the specifi cations which appy over the fu operating temperature range, otherwise specifi cations are at T J = 25 C. (Note 2) PARAMETER CONDITIONS MIN TYP MAX UNITS Operating otage 1. 2 Reguated Output otage (Note 4) ADJ Pin otage (Notes 3, 4) Line Reguation (Note 3) Load Reguation (Note 3) Dropout otage IN = OUT(NOMINAL) (Notes 5, ) Quiescent Current (Notes, 7) GND Pin Current IN = OUT(NOMINAL) +.5 (Notes, 7) LT39-1.2: IN = 1.7, I LOAD = 1μA 1.7 < IN < 2, 1μA < I LOAD < 2mA LT39-1.5: IN = 2, I LOAD = 1μA 2 < IN < 2, 1μA < I LOAD < 2mA LT39-1.8: IN = 2.3, I LOAD = 1μA 2.3 < IN < 2, 1μA < I LOAD < 2mA LT39-2.5: IN = 3, I LOAD = 1μA 3 < IN < 2, 1μA < I LOAD < 2mA LT39-3.3: IN = 3.8, I LOAD = 1μA 3.8 < IN < 2, 1μA < I LOAD < 2mA LT39-5: IN = 5.5, I LOAD = 1μA 3.8 < IN < 2, 1μA < I LOAD < 2mA IN = 1., I LOAD = 1μA 1. < IN < 2, 1μA < I LOAD < 2mA LT39-1.2: IN = 1.7 to 2, I LOAD = 1mA LT39-1.5: IN = 2. to 2, I LOAD = 1mA LT39-1.8: IN = 2.3 to 2, I LOAD = 1mA LT39-2.5: IN = 3. to 2, I LOAD = 1mA LT39-3.3: IN = 3.8 to 2, I LOAD = 1mA LT39-5: IN = 5.5 to 2, I LOAD = 1mA LT39: IN = 1. to 2, I LOAD = 1mA LT39-1.2: IN = 1.7, I LOAD = 1μA to 2mA LT39-1.5: IN = 2, I LOAD = 1μA to 2mA LT39-1.8: IN = 2.3, I LOAD = 1μA to 2mA LT39-2.5: IN = 3, I LOAD = 1μA to 2mA LT39-3.3: IN = 3.8, I LOAD = 1μA to 2mA LT39-5: IN = 5.5, I LOAD = 1μA to 2mA LT39: IN = 1., I LOAD = 1μA to 2mA I LOAD = 1μA I LOAD = 1μA I LOAD = 1mA I LOAD = 1mA I LOAD = 1mA I LOAD = 1mA I LOAD = 2mA I LOAD = 2mA I LOAD = μa I LOAD = μa I LOAD = μa I LOAD = 1μA I LOAD = 1mA I LOAD = 1mA I LOAD = 2mA 1.188 1.17 1.485 1.47 1.782 1.74 2.475 2.45 3.27 3.234 4.95 4.9 594 588 1.2 1.2 1.5 1.5 1.8 1.8 2.5 2.5 3.3 3.3 5 5.8 1. 1.2 1.7 2.2 3.3.4 1.4 1.8 2.1 2.9 3.9 5.8.7 1.212 1.224 1.515 1.53 1.818 1.83 2.525 2.55 3.333 3.3 5.5 5.1 12 3. 3.8 4.5.3 8.3 12.5 1.5 7.5 9. 12.5 1.5 25 3 115 18 25 17 25 35 25 31 41 28 35 45 3 3 23 2 45 12 5 5 1 μa μa μa μa μa μa μa 4 39fd
LT39 Series ELECTRICAL CHARACTERISTICS The denotes the specifi cations which appy over the fu operating temperature range, otherwise specifi cations are at T J = 25 C. (Note 2) PARAMETER CONDITIONS MIN TYP MAX UNITS Output otage Noise (Note 9) C OUT = 1μF, I LOAD = 2mA, BW = 1Hz to 1kHz 15 μ RMS ADJ Pin Bias Current 1.3 1 na Shutdown Threshod OUT = Off to On. 1.5 OUT = On to Off.2.3 SHDN Pin Current SHDN =, IN = 2 SHDN = 2, IN = 2.5 Quiescent Current in Shutdown IN =, SHDN = <1 μa Rippe Rejection (Note 3) IN OUT = 1.5, RIPPLE =.5 P-P, f RIPPLE = 12Hz, I LOAD = 2mA LT39 LT39-1.2 LT39-1.5 LT39-1.8 LT39-2.5 LT39-3.3 LT39-5 Current Limit IN = 2, OUT = IN = OUT(NOMINAL) + 1, OUT = 5% 22 57 55.5 54 52 49 44 72 8 7 3 1 5 ±1 1. μa μa db db db db db db db ma ma Input Reverse Leakage Current IN = 2, OUT = 2 35 μa Reverse Output Current OUT = 1.2, IN =. 1 μa Note 1: Stresses beyond those isted under Absoute Maximum Ratings may cause permanent damage to the device. Exposure to any Absoute Maximum Rating condition for extended periods may affect device reiabiity and ifetime. Note 2: The LT39 reguators are tested and specifi ed under puse oad conditions such that T J T A. The LT39E is guaranteed to meet performance specifications from C to 125 C operating junction temperature. Specifications over the 4 C to 125 C operating junction temperature range are assured by design, characterization and correation with statistica process contros. The LT39I is guaranteed over the fu 4 C to 125 C operating junction temperature range. Note 3: The LT39 adjustabe version is tested and specifi ed for these conditions with the ADJ pin connected to the OUT pin. Note 4: Operating conditions are imited by maximum junction temperature. The reguated output votage specification wi not appy for a possibe combinations of input votage and output current. When operating at the maximum input votage, the output current range must be imited. When operating at the maximum output current, the input votage must be imited. Note 5: Dropout votage is the minimum input to output votage differentia needed to maintain reguation at a specifi ed output current. In dropout, the output votage equas ( IN DROPOUT ). For the LT39-1.2, dropout votage wi be imited by the minimum input votage under some votage/ oad conditions. Note : To satisfy minimum input votage requirements, the LT39 adjustabe version is tested and specifi ed for these conditions with an externa resistor divider (1.9k bottom, 28k top) which sets OUT to 3.3. The externa resistor divider adds 9.9μA of DC oad on the output. This externa current is not factored into GND pin current. Note 7: GND pin current is tested with IN = OUT(NOMINAL) +.5 and a current source oad. GND pin current wi increase in dropout. For the fi xed output votage versions, an interna resistor divider wi add to the GND pin current (2μA for the LT39-5, 1μA for the LT39-1.2, LT39-1.5, LT39-1.8, LT39-2.5 and LT39-3.3). See the GND Pin Current curves in the Typica Performance Characteristics section. Note 8: The SHDN pin can be driven beow GND ony when tied to the IN pin directy or through a pu-up resistor. If the SHDN pin is driven beow GND by more than.3 whie IN is powered, the output wi turn on. Note 9: Output noise is isted for the adjustabe version with the ADJ pin connected to the OUT pin. See the RMS Output Noise vs Load Current curve in the Typica Performance Characteristics Section. 39fd 5
LT39 Series TYPICAL PERFORMANCE CHARACTERISTICS T A = 25 C, uness otherwise noted. DROPOUT OLTAGE () Dropout otage Dropout otage Minimum Input otage 45 I LOAD = 2mA 4 35 3 25 T A = 125 C T A = 25 C 2 15 1 5 5 1 15 2 OUTPUT CURRENT (ma) DROPOUT OLTAGE () 45 4 35 3 25 2 15 2mA 1mA 1mA 1μA 1 5 5 25 25 5 75 1 125 15 MINIMUM INPUT OLTAGE () 1. I LOAD = 2mA 1.4 1.2 1.8..4.2 5 25 25 5 75 1 125 15 39 G1 39 G2 39 G3 ADJ PIN OLTAGE () OUTPUT OLTAGE ().12.1.8..4.2..598.59.594.592.59 ADJ Pin otage I LOAD = 1μA.588 5 25 25 5 75 1 125 15 Output otage LT39-1.8 39 G4 1.83 1.83 I LOAD = 1μA 1.824 1.818 1.812 1.8 1.8 1.794 1.788 1.782 1.77 1.77 1.74 5 25 25 5 75 1 125 15 39 G5 OUTPUT OLTAGE () OUTPUT OLTAGE () Output otage LT39-1.2 1.224 1.22 I LOAD = 1μA 1.21 1.212 1.28 1.24 1.2 1.19 1.192 1.188 1.184 1.18 1.17 5 25 25 5 75 1 125 15 2.55 2.54 2.53 2.52 2.51 2.5 2.49 2.48 2.47 2.4 Output otage LT39-2.5 I LOAD = 1μA 39 G27 2.45 5 25 25 5 75 1 125 15 39 G29 OUTPUT OLTAGE () OUTPUT OLTAGE () 1.53 1.525 1.52 1.515 1.51 1.55 1.5 1.495 1.49 1.485 1.48 Output otage LT39-1.5 I LOAD = 1μA 1.475 1.47 5 25 25 5 75 1 125 15 Output otage LT39-3.3 39 G28 3.3 3.355 I LOAD = 1μA 3.344 3.333 3.322 3.311 3.3 3.289 3.278 3.27 3.25 3.245 3.234 5 25 25 5 75 1 125 15 39 G 39fd
TYPICAL PERFORMANCE CHARACTERISTICS T A = 25 C, uness otherwise noted. LT39 Series OUTPUT OLTAGE () 5.1 5.75 5.5 5.25 5. 4.975 4.95 4.925 Output otage LT39-5 I LOAD = 1μA ADJ PIN BIAS CURRENT (na) 1 8 4 2 2 4 8 ADJ Pin Bias Current QUIESCENT CURRENT (μa) 5 4 3 2 1 Adjustabe ersion Quiescent Current 4.9 5 25 25 5 75 1 125 15 1 5 25 25 5 75 1 125 15 5 25 25 5 75 1 125 15 39 G7 39 G8 39 G9 QUIESCENT CURRENT (μa) 2 18 1 14 12 1 8 4 2 Quiescent Current LT39-1.2 LT39-1.5 LT39-1.8 QUIESCENT CURRENT (μa) 2 18 1 14 12 1 8 4 2 Quiescent Current LT39-2.5 LT39-3.3 LT39-5 GND PIN CURRENT (μa) 5 45 4 35 3 25 2 15 1 5 GND Pin Current LT39-1.2 R L = 12k, I L = 1μA R L = Ω, I L = 2mA R L = 12Ω, I L = 1mA R L = 1.2k, I L = 1mA 1 2 3 4 5 7 8 9 1 INPUT OLTAGE () 39 G1 1 2 3 4 5 7 8 9 1 INPUT OLTAGE () 39 G3 1 2 3 4 5 7 8 9 1 INPUT OLTAGE () 39 G31 39fd 7
LT39 Series TYPICAL PERFORMANCE CHARACTERISTICS T A = 25 C, uness otherwise noted. GND PIN CURRENT (μa) 5 45 4 35 3 25 2 15 1 5 GND Pin Current LT39-1.5 R L = 15k, I L = 1μA R L = 75Ω, I L = 2mA R L = 15Ω, I L = 1mA R L = 1.5k, I L = 1mA 1 2 3 4 5 7 8 9 1 INPUT OLTAGE () 39 G32 GND PIN CURRENT (μa) 5 45 4 35 3 25 2 15 1 5 GND Pin Current LT39-1.8 R L = 18k, I L = 1μA R L = 9Ω, I L = 2mA R L = 18Ω, I L = 1mA R L = 1.8k, I L = 1mA 1 2 3 4 5 7 8 9 1 INPUT OLTAGE () 39 G11 GND PIN CURRENT (μa) 5 45 4 35 3 25 2 15 1 5 GND Pin Current LT39-2.5 R L = 25k, I L = 1μA R L = 125Ω, I L = 2mA R L = 25Ω, I L = 1mA R L = 2.5k, I L = 1mA 1 2 3 4 5 7 8 9 1 INPUT OLTAGE () 39 G33 GND PIN CURRENT (μa) 5 45 4 35 3 25 2 15 GND Pin Current LT39-3.3 R L = 15Ω, I L = 2mA R L = 33Ω, I L = 1mA 1 R L = 33k, I L = 1μA 5 R L = 3.3k, I L = 1mA 1 2 3 4 5 7 8 9 1 INPUT OLTAGE () 39 G12 GND PIN CURRENT (μa) 45 4 35 3 25 2 15 1 5 GND Pin Current LT39-5 R L = 25Ω, I L = 2mA R L = 5Ω, I L = 1mA R L = 5k, I L = 1μA R L = 5k, I L = 1mA 1 2 3 4 5 7 8 9 1 INPUT OLTAGE () 39 G13 GND CURRENT (μa) 1 1 1 GND Pin Current vs I LOAD 1.1 IN = 3.8 OUT = 3.3.1.1 1 1 1 LOAD (ma) 39 G14 8 39fd
TYPICAL PERFORMANCE CHARACTERISTICS T A = 25 C, uness otherwise noted. LT39 Series SHDN PIN THRESHOLD OLTAGE () SHDN Pin Threshods SHDN Pin Input Current SHDN Pin Input Current 1.4 1.2 1..8 OFF TO ON..4 ON TO OFF.2 5 25 25 5 75 1 125 15 SHDN PIN INPUT CURRENT (na) 5 45 4 35 3 25 2 15 1 5 2 4 8 1 12 14 1 18 2 SHDN PIN OLTAGE () 1 SHDN = 2 14 12 1 8 4 2 5 25 25 5 75 1 125 15 39 G15 39 G1 39 G17 SHDN PIN INPUT CURRENT (na) CURRENT LIMIT (ma) 7 5 4 3 2 1 Current Limit IN = 2 IN = 1. REERSE OUTPUT CURRENT (μa) 5 45 4 35 3 25 2 15 1 5 Reverse Output Current OUT = ADJ = 1.2 IN = SHDN = GND ADJ OUT INPUT RIPPLE REJECTION (db) 9 8 7 5 4 3 2 1 Input Rippe Rejection IN = 2 + 5 RMS OUT = I LOAD = 2mA 4.7μF 1μF 5 25 25 5 75 1 125 15 5 25 25 5 75 1 125 15 1 1 1k 1k 1k 1M FREQUENCY (Hz) 39 G18 39 G19 39 G2 39fd 9
LT39 Series TYPICAL PERFORMANCE CHARACTERISTICS T A = 25 C, uness otherwise noted. INPUT RIPPLE REJECTION (db) 8 7 5 4 3 2 Input Rippe Rejection Load Reguation Output Noise Spectra Density 1 IN = OUT (NOMINAL) + 1 +.5 P-P RIPPLE AT f = 12Hz I LOAD = 2mA 5 25 25 5 75 1 125 15 39 G21 LOAD REGULATION () 3. 2.5 2. 1.5 1..5.5 1. 5 25 25 5 75 1 125 15 ΔI L = 1μA TO 2mA OUT = IN = 1. 39 G22 OUTPUT NOISE SPECTRAL DENSITY (μ Hz) 1 1 1 5 3.3 2.5 1.8 1.5 1.2 1..1 1 1 1k 1k 1k FREQUENCY (Hz) 39 G23 OUTPUT NOISE (μ RMS ) 7 5 4 3 2 1 RMS Output Noise vs Load Current (1Hz to 1kHz) 5 3.3 2.5 1.8 1.5 1.2 Transient Response I OUT = 1mA TO 2mA IN = 5.5 OUT = 5 C OUT = 1μF OUT 5/DI I OUT 2mA/DI 5μs/DI 39 G25 Transient Response I OUT = 1mA TO 2mA IN = 5.5 OUT = 5 C OUT = 4.7μF OUT 5/DI I OUT 2mA/DI 5μs/DI 39 G2.1.1.1 1 1 1 I LOAD (ma) 39 G24 1 39fd
LT39 Series PIN FUNCTIONS (SC7/DFN) SHDN (Pin 1/Pin 5): Shutdown. Puing the SHDN pin ow puts the LT39 into a ow power state and turns the output off. If unused, tie the SHDN pin to IN. The LT39 does not function if the SHDN pin is not connected. The SHDN pin cannot be driven beow GND uness tied to the IN pin. If the SHDN pin is driven beow GND whie IN is powered, the output wi turn on. SHDN pin ogic cannot be referenced to a negative rai. GND (Pins 2, 3, 4/Pin ): Ground. Connect the bottom of the resistor divider that sets output votage directy to GND for the best reguation. IN (Pin 5/Pin 4): Input. The IN pin suppies power to the device. The LT39 requires a bypass capacitor at IN if the device is more than six inches away from the main input fi ter capacitor. In genera, the output impedance of a battery rises with frequency, so it is advisabe to incude a bypass capacitor in battery-powered circuits. A bypass capacitor in the range of.1μf to 1μF wi suffice. The LT39 withstands reverse votages on the IN pin with respect to ground and the OUT pin. In the case of a reversed input, which occurs with a battery pugged in backwards, the LT39 acts as if a arge resistor is in series with its input. Limited reverse current f ows into the LT39 and no reverse votage appears at the oad. The device protects both itsef and the oad. OUT (Pin /Pins 2, 3): Output. This pin suppies power to the oad. Use a minimum output capacitor of 1μF to prevent osciations. Large oad transient appications require arger output capacitors to imit peak votage transients. See the Appications Information section for more information on output capacitance and reverse output characteristics. ADJ (Pin 7/Pin 1): Adjust. This pin is the error ampifier s inverting termina. Its 3pA typica input bias current fows out of the pin (see curve of ADJ Pin Bias Current vs Temperature in the Typica Performance Characteristics section). The ADJ pin votage is referenced to GND and the output votage range is to 19.5. This pin is not connected in the fixed output votage versions. NC (Pins 7, 8/Pin 1): No Connect. For the adjustabe votage version, Pin 8 is an NC pin in the SC7 package. For the fixed votage versions, Pin 7 and Pin 8 are NC pins in the SC7 package, and Pin 1 is an NC pin in the DFN package. NC pins are not tied to any interna circuitry. They may be foated, tied to IN or tied to GND. Exposed Pad (Pin 7, DFN Package Ony): Ground. The Exposed Pad (backside) of the DFN package is an eectrica connection to GND. To ensure optimum performance, soder Pin 7 to the PCB and tie directy to Pin. 39fd 11
LT39 Series APPLICATIONS INFORMATION The LT39 is a ow dropout inear reguator with utraow quiescent current and shutdown. Quiescent current is extremey ow at 3μA and drops we beow 1μA in shutdown. The device suppies up to 2mA of output current. Dropout votage at 2mA is typicay 28. The LT39 incorporates severa protection features, making it idea for use in battery-powered systems. The device protects itsef against both reverse-input and reverse-output votages. In battery backup appications, where a backup battery hods up the output when the input is pued to ground, the LT39 acts as if a bocking diode is in series with its output and prevents reverse current f ow. In appications where the reguator oad returns to a negative suppy, the output can be pued beow ground by as much as 22 without affecting startup or norma operation. Adjustabe Operation The LT39 has an output votage range of. to 19.5. Figure 1 shows that output votage is set by the ratio of two externa resistors. The IC reguates the output to maintain the ADJ pin votage at referenced to ground. The current in R1 equas /R1 and the current in R2 is the current in R1 minus the ADJ pin bias current. The ADJ pin bias current, typicay 3pA at 25 C, fows out of the pin. Cacuate the output votage using the formua in Figure 1. An R1 vaue of 19k sets the divider current to.97μa. Do not make R1 s vaue any greater than 19k to minimize output votage errors due to the ADJ pin bias current and to insure stabiity under minimum oad conditions. In shutdown, the output turns off and the divider current is zero. Curves of ADJ Pin otage vs Temperature and ADJ Pin Bias Current vs Temperature appear in the Typica Performance Characteristics. Specifi cations for output votages greater than. are proportiona to the ratio of the desired output votage to.: OUT /.. For exampe, oad reguation for an output current change of 1μA to 2mA is.7 typica at OUT =.. At OUT = 5, oad reguation is: 5 (.7)= 5.83. Tabe 1 shows resistor divider vaues for some common output votages with a resistor divider current of about 1μA. Tabe 1. Output otage Resistor Divider aues OUT R1 R2 1 4k 42k 1.2 4k 4k 1.5 59k 887k 1.8 59k 1.18M 2.5 59k 1.87M 3 59k 2.37M 3.3 19k 2.8M 5 59k 4.32M Because the ADJ pin is reativey high impedance (depending on the resistor divider used), stray capacitances at this pin shoud be minimized. Specia attention shoud be given to any stray capacitances that can coupe externa signas onto the ADJ pin producing undesirabe output transients or rippe. Extra care shoud be taken in assemby when using high vaued resistors. Sma amounts of board contamination can ead to significant shifts in output votage. Appropriate post-assemby board ceaning measures shoud OUT = * (1 + R2/R1) (I ADJ R2) ADJ = I ADJ =.3nA at 25 C OUTPUT RANGE =. to 19.5 IN IN OUT LT39 SHDN ADJ GND R2 R1 OUT 39 F Figure 1. Adjustabe Operation 12 39fd
APPLICATIONS INFORMATION be impemented to prevent board contamination. If the board is to be subjected to humidity cycing or if board ceaning measures cannot be guaranteed, consideration shoud be given to using resistors an order of magnitude smaer than in Tabe 1 to prevent contamination from causing unwanted shifts in the output votage. Output Capacitance and Transient Response The LT39 is stabe with a wide range of output capacitors. The ESR of the output capacitor affects stabiity, most notaby with sma capacitors. Use a minimum output capacitor of 1μF with an ESR of 3 or ess to prevent osciations. The LT39 is a micropower device and output oad transient response is a function of output capacitance. Larger vaues of output capacitance decrease the peak deviations and provide improved transient response for arger oad current changes. Give extra consideration to the use of ceramic capacitors. Manufacturers make ceramic capacitors with a variety of dieectrics, each with different behavior across temperature and appied votage. The most common dieectrics LT39 Series are specified with EIA temperature characteristic codes of Z5U, Y5, X5R and X7R. The Z5U and Y5 dieectrics provide high C- products in a sma package at ow cost, but exhibit strong votage and temperature coefficients as shown in Figures 2 and 3. When used with a 5 reguator, a 1 1μF Y5 capacitor can exhibit an effective vaue as ow as 1μF to 2μF for the DC bias votage appied and over the operating temperature range. The X5R and X7R dieectrics yied more stabe characteristics and are more suitabe for use as the output capacitor. The X7R type has better stabiity across temperature, whie the X5R is ess expensive and is avaiabe in higher vaues. One must sti exercise care when using X5R and X7R capacitors; the X5R and X7R codes ony specify operating temperature range and maximum capacitance change over temperature. Capacitance change due to DC bias with X5R and X7R capacitors is better than Y5 and Z5U capacitors, but can sti be significant enough to drop capacitor vaues beow appropriate eves. Capacitor DC bias characteristics tend to improve as component case size increases, but expected capacitance at operating votage shoud be verified. CHANGE IN ALUE (%) 2 2 4 8 BOTH CAPACITORS ARE 1, 121 CASE SIZE, 1μF X5R Y5 1 2 4 8 1 12 14 DC BIAS OLTAGE () 1 39 F2 CHANGE IN ALUE (%) 4 2 2 4 8 1 5 Y5 BOTH CAPACITORS ARE 1, 121 CASE SIZE, 1μF X5R 25 25 5 75 1 125 39 F3 Figure 2. Ceramic Capacitor DC Bias Characteristics Figure 3. Ceramic Capacitor Temperature Characteristics 39fd 13
LT39 Series APPLICATIONS INFORMATION otage and temperature coeffi cients are not the ony sources of probems. Some ceramic capacitors have a piezoeectric response. A piezoeectric device generates votage across its terminas due to mechanica stress, simiar to the way a piezoeectric acceerometer or microphone works. For a ceramic capacitor, the stress can be induced by vibrations in the system or therma transients. The resuting votages produced can cause appreciabe amounts of noise, especiay when a ceramic capacitor is used for noise bypassing. A ceramic capacitor produced Figure 4 s trace in response to ight tapping from a penci. Simiar vibration induced behavior can masquerade as increased output votage noise. OUT 5μ/DI OUT =. C OUT = 22μF I LOAD = 1μA 1ms/DI 39 F4 Figure 4. Noise Resuting from Tapping on a Ceramic Capacitor Therma Considerations The LT39 s maximum rated junction temperature of 125 C imits its power-handing capabiity. Two components comprise the power dissipated by the device: 1. Output current mutipied by the input/output votage differentia: I OUT ( IN OUT ) 2. GND pin current mutipied by the input votage: I GND IN GND pin current is found by examining the GND Pin Current curves in the Typica Performance Characteristics section. Power dissipation equas the sum of the two components isted prior. The LT39 reguator has interna therma imiting designed to protect the device during overoad conditions. For continuous norma conditions, do not exceed the maximum junction temperature rating of 125 C. Carefuy consider a sources of therma resistance from junction to ambient incuding other heat sources mounted in proximity to the LT39. For surface mount devices, heat sinking is accompished by using the heat spreading capabiities of the PC board and its copper traces. Copper board stiffeners and pated through-hoes can aso be used to spread the heat generated by power devices. 14 39fd
LT39 Series APPLICATIONS INFORMATION The foowing tabes ist therma resistance for severa different board sizes and copper areas. A measurements were taken in sti air on 3/32" FR-4 board with one ounce copper. Tabe 2: Measured Therma Resistance for DC Package COPPER AREA BOARD THERMAL RESISTANCE TOPSIDE* BACKSIDE AREA (JUNCTION-TO-AMBIENT) 25mm 2 25mm 2 25mm 2 5 C/W 1mm 2 25mm 2 25mm 2 7 C/W 225mm 2 25mm 2 25mm 2 75 C/W 1mm 2 25mm 2 25mm 2 8 C/W 5mm 2 25mm 2 25mm 2 85 C/W *Device is mounted on the topside. Tabe 3: Measured Therma Resistance for SC7 Package COPPER AREA BOARD THERMAL RESISTANCE TOPSIDE* BACKSIDE AREA (JUNCTION-TO-AMBIENT) 25mm 2 25mm 2 25mm 2 75 C/W 1mm 2 25mm 2 25mm 2 8 C/W 225mm 2 25mm 2 25mm 2 85 C/W 1mm 2 25mm 2 25mm 2 9 C/W 5mm 2 25mm 2 25mm 2 95 C/W *Device is mounted on the topside. Cacuating Junction Temperature Exampe: Given an output votage of 3.3, an input votage range of 12 ±5%, an output current range of ma to 2mA and a maximum ambient temperature of 85 C, what wi the maximum junction temperature be for an appication using the DC package? The power dissipated by the device is equa to: I OUT(MAX) ( IN(MAX) OUT ) + I GND ( IN(MAX) ) where, I OUT(MAX) = 2mA IN(MAX) = 12. I GND at (I OUT = 2mA, IN = 12.) =.45mA So, P = 2mA(12. 3.3) +.45mA(12.) = 191.7mW The therma resistance wi be in the range of 5 C/W to 85 C/W depending on the copper area. So the junction temperature rise above ambient wi be approximatey equa to:.1917w(75 C/W) = 14.4 C The maximum junction temperature equas the maximum junction temperature rise above ambient pus the maximum ambient temperature or: T J(MAX) = 85 C + 14.4 C = 99.4 C 39fd 15
LT39 Series APPLICATIONS INFORMATION Protection Features The LT39 incorporates severa protection features that make it idea for use in battery-powered circuits. In addition to the norma protection features associated with monoithic reguators, such as current imiting and therma imiting, the device aso protects against reverse-input votages, reverse-output votages and reverse output-toinput votages. Current imit protection and therma overoad protection protect the device against current overoad conditions at the output of the device. For norma operation, do not exceed a junction temperature of 125 C. The LT39 IN pin withstands reverse votages of 22. The device imits current f ow to ess than 1mA (typicay ess than 22μA) and no negative votage appears at OUT. The device protects both itsef and the oad against batteries that are pugged in backwards. The SHDN pin cannot be driven beow GND uness tied to the IN pin. If the SHDN pin is driven beow GND whie IN is powered, the output wi turn on. SHDN pin ogic cannot be referenced to a negative rai. The LT39 incurs no damage if OUT is pued beow ground. If IN is eft open circuit or grounded, OUT can be pued beow ground by 22. No current f ows from the pass transistor connected to OUT. However, current fows in (but is imited by) the resistor divider that sets output votage. Current fows from the bottom resistor in the divider and from the ADJ pin s interna camp through the top resistor in the divider to the externa circuitry puing OUT beow ground. If IN is powered by a votage source, OUT sources current equa to its current imit capabiity and the LT39 protects itsef by therma imiting if necessary. In this case, grounding the SHDN pin turns off the LT39 and stops OUT from sourcing current. The LT39 incurs no damage if the ADJ pin is pued above or beow ground by 22. If IN is eft open circuit or grounded, ADJ acts ike a 1k resistor in series with a diode when pued above or beow ground. In circuits where a backup battery is required, severa different input/output conditions can occur. The output votage may be hed up whie the input is either pued to ground, pued to some intermediate votage or is eft open circuit. Current fow back into the output foows the curve shown in Figure 5. If the LT39 IN pin is forced beow the OUT pin or the OUT pin is pued above the IN pin, input current typicay drops to ess than 1μA. This occurs if the LT39 input is connected to a discharged (ow votage) battery and either a backup battery or a second reguator circuit hods up the output. The state of the SHDN pin has no effect in the reverse current if OUT is pued above IN. REERSE CURRENT (μa) 1 9 8 7 5 4 3 2 1 ADJ CURRENT OUT CURRENT 1 2 3 4 5 7 8 9 1 OUTPUT AND ADJ OLTAGE () 39 F5 Figure 5. Reverse Output Current 1 39fd
TYPICAL APPLICATIONS Keep-Aive Power Suppy LT39 Series NO PROTECTION DIODES NEEDED! IN 12 1μF IN LT39-3.3 SHDN GND OUT 3.3 1μF LOAD: SYSTEM MONITOR, OLATILE MEMORY, ETC. 39 TA2 Last-Gasp Circuit LINE 12 TO 15 LINE POWER SENSE SUPERCAP D CHARGE R LIMIT 1μF IN OUT LT39-5 5 1μF LINE INTERRUPT DETECT PWR GND FAULT 39 TA3 TO MONITORING CENTER SHDN GND PACKAGE DESCRIPTION DC Package -Lead Pastic DFN (2mm 2mm) (Reference LTC DWG # 5-8-173 Rev B).7 ±.5 R =.125 TYP.5 ±.5 (2 SIDES) 4.4 ±.1 2.55 ±.5 1.15 ±.5.1 ±.5 (2 SIDES) PACKAGE OUTLINE.25 ±.5.5 BSC 1.42 ±.5 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS PIN 1 BAR TOP MARK (SEE NOTE ).2 REF 2. ±.1 (4 SIDES) PIN 1 NOTCH R =.2 OR.25 45 CHAMFER (DC) DFN RE B 139 R =.5 TYP 3 1.25 ±.5.75 ±.5.5 BSC 1.37 ±.5 (2 SIDES)..5 BOTTOM IEW EXPOSED PAD NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M-229 ARIATION OF (WCCD-2) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 5. EXPOSED PAD SHALL BE SOLDER PLATED. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 39fd 17
LT39 Series PACKAGE DESCRIPTION SC8 Package 8-Lead Pastic SC7 (Reference LTC DWG # 5-8-139 Rev Ø).3 MAX.5 REF PIN 8 1.8 2.2 (NOTE 4) 1. REF 2.8 BSC 1.8 REF 1.8 2.4 1.15 1.35 (NOTE 4) INDEX AREA (NOTE ) PIN 1 GAUGE PLANE.15 BSC RECOMMENDED SOLDER PAD LAYOUT PER IPC CALCULATOR.1.4 1. MAX.5 BSC.8 1..15.27 8 PLCS (NOTE 3)..1 REF.2.4.1.18 (NOTE 3) NOTE: 1. DIMENSIONS ARE IN MILLIMETERS 2. DRAWING NOT TO SCALE 3. DIMENSIONS ARE INCLUSIE OF PLATING 4. DIMENSIONS ARE EXCLUSIE OF MOLD FLASH AND METAL BURR 5. MOLD FLASH SHALL NOT EXCEED.254mm. DETAILS OF THE PIN 1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE INDEX AREA 7. EIAJ PACKAGE REFERENCE IS EIAJ SC-7 AND JEDEC MO-23 ARIATION BA SC8 SC7 95 RE Ø 18 39fd
LT39 Series REISION HISTORY (Revision history begins at Rev D) RE DATE DESCRIPTION PAGE NUMBER D 4/12 Carified E-Grade Operating Temperature 5 Information furnished by Linear Technoogy Corporation is beieved to be accurate and reiabe. However, no responsibiity is assumed for its use. Linear Technoogy Corporation makes no representation that the interconnection of its circuits as described herein wi not infringe on existing patent rights. 39fd 19
LT39 Series RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT171 1mA, Low Noise Micropower LDO IN : 1.8 to 2, OUT = 1.22, DO =.3, I Q = 2μA, I SD < 1μA, Low Noise < 2μ RMS, Stabe with 1μF Ceramic Capacitors, ThinSOT TM Package LT172 15mA, Low Noise Micropower LDO IN : 1.8 to 2, OUT = 1.22, DO =.3, I Q = 25μA, I SD < 1μA, Low Noise < 2μ RMS, MS8 Package LT173 5mA, Low Noise Micropower LDO IN : 1.8 to 2, OUT = 1.22, DO =.3, I Q = 3μA, I SD < 1μA, Low Noise < 2μ RMS, S8 Package LT174/LT174A 3A, Low Noise, Fast Transient Response LDOs IN : 2.7 to 2, OUT = 1.21, DO =.34, I Q = 1mA, I SD < 1μA, Low Noise < 4μ RMS, A ersion Stabe with Ceramic Capacitors, DD and TO22-5 Packages LTC1844 15mA, Low Noise Micropower LDO IN : 1. to.5, OUT(MIN) = 1.25, DO =.9, I Q = 35μA, I SD < 1μA, Low Noise: < 3μ RMS, ThinSOT Package LT192 3mA, Low Noise Micropower LDO IN : 1.8 to 2, OUT(MIN) = 1.22, DO =.27, I Q = 3μA, I SD < 1μA, Low Noise: < 2μ RMS, MS8 Package LT193/LT193A LT194 1.5A, Low Noise, Fast Transient Response LDOs 2mA, Low Noise Micropower, Negative LDO IN : 2.1 to 2, OUT(MIN) = 1.21, DO =.34, I Q = 1mA, I SD < 1μA, Low Noise: < 4μ RMS, A ersion Stabe with Ceramic Capacitors, DD, TO22-5, SOT223 and S8 Packages IN : 2.2 to 2, OUT(MIN) = 1.21, DO =.34, I Q = 3μA, I SD = 3μA, Low Noise: < 3μ RMS, Stabe with Ceramic Capacitors,ThinSOT Package LT31 5mA, High otage, Micropower LDO IN : 3 to 8, OUT(MIN) = 1.275, DO =.3, I Q = 3μA, I SD < 1μA, Low Noise: < 1μ RMS, Stabe with 1μF Output Capacitor, MS8E Package LT312/LT312B LT313/LT313B 25mA, High otage, Micropower LDOs IN : 4 to 8, OUT(MIN) = 1.24, DO =.4, I Q = 4μA, I SD < 1μA, Low Noise: <1μ RMS, Stabe with 3.3μF Output Capacitor, 12-Lead 4mm 3mm DFN and 1-Lead FE Packages 25mA, High otage, Micropower LDOs with PWRGD IN : 4 to 8, OUT(MIN) = 1.22, DO =.4, I Q = 4μA, I SD < 1μA, Low Noise: < 1μ RMS, Stabe with 3.3μF Output Capacitor, 12-Lead 4mm 3mm DFN and 1-Lead FE Packages LT314/LT314B 2mA, High otage, Micropower LDO IN : 3 to 8, OUT(MIN) = 1.2, DO =.35, I Q = 7μA, I SD < 1μA, Low Noise: < 1μ RMS, Stabe with.47μf Output Capacitor, SOT23-5 and 3mm 3mm DFN Packages LT32 1mA, Low otage LDO IN :.9 to 1, OUT(MIN) =.2, DO =.15, I Q = 12μA, I SD < 1μA, 3mm 3mm DFN and MS8 Packages LT321 5mA, Low otage LDO IN :.9 to 1, OUT(MIN) =.2, DO =.1, I Q = 12μA, I SD < 3μA, 5mm 5mm DFN and SO8 Packages LT323 LT324 Dua 1mA, Low Noise, Micropower LDO Dua 1mA/5mA, Low Noise, Micropower LDO IN : 1.8 to 2, OUT(MIN) = 1.22, DO =.3, I Q = 4μA, I SD < 1μA, DFN and MS1 Packages IN : 1.8 to 2, OUT(MIN) = 1.22, DO =.3, I Q = μa, I SD < 1μA, DFN and TSSOP- 1E Packages LTC325 3mA, Low otage Micropower LDO 45 Dropout otage, Low Noise 11μ RMS, IN = 1.14 to 5.5, Low I Q : 54μA, -Lead 2mm 2mm DFN Package LTC32 1.5A, Low Input otage LDO 1 Dropout otage, Low Noise 8μ RMS, IN =.9 to 5.5, Low I Q : 95μA, 1-Lead 3mm 3mm DFN and MS1E Packages LT327 Dua 1mA, Low Noise, Micropower LDO with Independent Inputs LT328 Dua 1mA/5mA, Low Noise, Micropower LDO with Independent Inputs ThinSOT is a trademark of Linear Technoogy Corporation. IN : 1.8 to 2, OUT(MIN) = 1.22, DO =.3, I Q = 4μA, I SD < 1μA, DFN and MS1E Packages IN : 1.8 to 2, OUT(MIN) = 1.22, DO =.3, I Q = μa, I SD < 1μA, DFN and TSSOP-1E Packages 2 LT 412 RE D PRINTED IN USA Linear Technoogy Corporation 13 McCarthy Bvd., Mipitas, CA 9535-7417 (48) 432-19 FAX: (48) 434-57 www.inear.com LINEAR TECHNOLOGY CORPORATION 27 39fd