WHEN A CMOS technology approaches to a nanometer

250 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO. 2, FEBRUARY 2013 A Wide-Range PLL Using Self-Healing Prescaler/VCO in 65-nm CMOS I-Ting Lee, Yun-Ta Tsai, and Shen-Iuan Liu, Fellow, IEEE Abstract The variability and leakage current in nanoscale CMOS technology may degrade the circuit performances significantly. To accommodate the above issues in a wide-range phase-locked loop (PLL), a self-healing prescaler, a self-healing voltage-controlled oscillator (VCO), and a calibrated charge pump (CP) are presented. This PLL is fabricated in a 65-nm CMOS technology and its active area is 0.0182 mm.forthe self-healing VCO, its measured frequency range is from 60 to 1489 MHz. When this PLL operates at 855 MHz, the measured rms and peak-to-peak jitters are 8.03 and 55.6 ps, respectively. The measured reference spur is -52.89 dbc. This PLL consumes 4.3 mw from 1.2 V supply without buffers. Index Terms Leakage current, nanoscale CMOS technology, phased-locked loop (PLL). I. INTRODUCTION WHEN A CMOS technology approaches to a nanometer scale, the non-idealities [1], [2], such as variability and leakage current, may significantly affect the circuit performances. The process variability leads to the large variations to degrade the device matching and performances. It may result in only a few dies on a wafer to meet the target performance specifications. The undesired leakage currents also degrade the accuracy and resolution of analog circuits and make digital dynamic circuits not to work properly [3], [4]. For a pmos transistor with 8 m 0.06 m in a 65-nm process, its source and gate are connected to the supply voltage of 1.2 V. Fig. 1(a) shows its simulated drain current versus the drain voltage under different corners. The drain current, i.e., leakage current, is 687 na, 0.12 ua, and 21 ua for the typical, slow-slow, and fast-fast corners, respectively, and 40 C. The leakage current is highly dependent upon the process variations. Fig. 1(b) shows the simulated drain current under different corners and the temperatures with a constant 1.2 V. The leakage current grows very fast in a high temperature environment. A phase-locked loop (PLL) is widely employed in wireline and wireless communication systems. The poor device matching and leakage current vary the common-mode voltage of a ring-based voltage-controlled oscillator (VCO) [5] over a Manuscript received July 29, 2011; revised November 01, 2011; accepted November 10, 2011. Date of publication March 05, 2012; date of current version January 17, 2013. This work was supported in part by NTU-MTK Laboratory andinpartbynsc,taiwan. The authors are with the Graduate Institute of Electronics Engineering and Department of Electrical Engineering National Taiwan University, Taipei 10617, Taiwan (e-mail: lsi@cc.ee.ntu.edu.tw). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TVLSI.2012.2186990 Fig. 1. The simulated drain current versus (a) the drain voltage and (b) temperature for a PMOS with its source and gate connected to 1.2 V. wide frequency range. It may limit the oscillation frequency range of a VCO and causes a VCO not to oscillate in a worst case. To realize a wide-range PLL, the divider following a VCO should operate between the highest and lowest frequencies. When a PLL works at a higher frequency which the static circuits cannot operate, dynamic circuits are needed. A true-single-phase-clocking (TSPC) divider is widely used to realize a prescaler for this PLL. A TSPC prescaler must work over a wide frequency range to cover the process and temperature variations. For a TSPC prescaler, the undesired leakage currents may limit its frequency range or alter the original states of the floating nodes to have a malfunction. The 1063-8210/$31.00 2012 IEEE

LEE et al.: WIDE-RANGE PLL USING SELF-HEALING PRESCALER/VCO IN 65-nm CMOS 251 Fig. 2. (a) Conventional divide-by4/5 dual-modulus prescaler using TSPC DFFs [7]. (b) Two kinds of malfunctions occurred at A. (c) The malfunction occurred at. leakage current and current mismatch in a charge pump (CP) will degrade the reference spur and jitter significantly. To mitigate the above problems, a self-healing divide-by-4/5 prescaler and a self-healing VCO are presented in this paper. A time-to-digital converter (TDC) and a 4-bit encoder are used to quantize the phase error and digitally calibrate the CP. This paper is organized as follows. Section II introduces these techniques. Section III describes the performance analysis of these techniques. The experimental results are given in Section IV and the conclusion is given in Section V. II. CIRCUIT DESCRIPTION A. Self-Healing Divide-by-4/5 Dual-Modulus Prescaler Fig. 2(a) shows a conventional divide-by-4/5 dual-modulus prescaler [7] using TSPC DFFs. The undesired leakage current may charge or discharge to alter the states of the nodes A, B, and in this TSPC DFF as shown in Fig. 2(a). For example, two kinds of the malfunctions may occur at the node A as shown in Fig. 2(b), respectively. The first case is that the initial state of the node A is high; however, a leakage current discharges it to ground. The second one is that the initial state of the node A is low, but a leakage current charges it to high. To consider the node B in Fig. 2(a), assume that the leakage current charges the node B to be high when CK is high. It will not affect the original state of the node. Thus, the leakage problem occurred at the node B is not considered here. For a malfunction occurred at the node,thesimplified circuit is shown in Fig. 2(c). Assume the transistor M1 is turned off, CK is low, and the initial state of the node is low. Since the node is floating, the leakage current from M1 may charge the node to high and a malfunction occurs. Note that the leakage current through M2 and M3 is smaller than that from M1. It is because the cascode transistors, M2 and M3, induce a lower leakage current [3], [4]. To detect and heal the above issues occurred at the nodes A and, the proposed self-healing circuit is shown in Fig. 3(a). This self-healing circuit consists of a detector and three compensators. By using a self-healing circuit, the timing diagrams of a TPSC DFF with and without a malfunction are shown Fig. 3(b), respectively. Assume the signal Enable in the self-healing circuit is low to disable the latch in Fig. 3(a). For a case that the malfunction is detected, the timing diagram is shown in the left side of Fig. 3(b). When the clock CK goes high, the pulse generator outputs a short pulse at the gate of M2A, which goes high to clear. When the input D of the DFF is high, the rising edge of the clock CK triggers the DFF s output Q to go high (or goes low) to turn off M3A. The pulse generator outputs a low pulse at the gate of M1A to turn off M4A. Before the next rising edge of CK arrives, isassumedtobecharged to high due to the undesired leakage current. In the meantime, Q goes low to turn on M3A and enables. It indicates that the malfunction of this TSPC DFF occurs. The size ratio of M4A and M3A is 5 to ensure,whenbothm3aand M4A are turned on. It has been simulated and verified for all corners and a supply voltage variation of 10% and the temperature of C C. For a case that the malfunction is fixed, the timing diagram is shown in the right-hand side of Fig. 3(b) where is always low. In Fig. 3(a), when the signal Enable is high and the malfunction is detected, is latched by a latch and the compensator is active. For example, assume the initial state of is low and the leakage current is charging the node.since is low and, the transistors, M5A M8A, in a compensator will be turned on. A minimum-sized transistor M7A is used to counteract the leakage current and repair the state of the node to be low finally. The leakage current is much smaller than that a minimum-size MOS can provide. These circuits have been simulated and verified for all corners and a supply voltage variation of 10% at the temperature of C C. Similarly, when a malfunction is detected, the compensators will turn on M7B or M7C to counteract the leakage current and repair the state at the node A. B. Self-Healing VCO A self-healing VCO is realized by four gain stages, a bottomlevel detector, and a current compensator. Fig. 4(a) shows a bottom-level detector, a current compensator, and a gain stage. This gain stage consists of a differential amplifier with active loads and a cross-coupled pair with digitally-controlled current sources. In the differential amplifier, the transistors, and, realize the input stage, and the transistors, and, act as a variable resistor controlled by. The cross-coupled pair, and, enhances the output swing of this VCO. The output common-mode voltage and the output swing of the VCO are al-

252 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO. 2, FEBRUARY 2013 Fig. 3. (a) Self-healing circuit and (b) timing diagrams of a TPSC DFF with and without a malfunction by using a self-healing circuit. tered by the leakage currents, the total tail currents, and the resistances of and. They are dependent upon the process variations. For example, when the resistances of and are decreased, the oscillation frequency of this VCO is increased. It will result in the output swing decreased and the bottom level is increased. It also leads to a limited oscillation frequency range. If a larger biasing current and the cross-coupled pair with larger dimensions are selected for this VCO, the output swing can be increased. However, it may waste the power when the operation frequency of this PLL is low. In this work, the self-healing VCO using a bottom-level detector can achieve a wide tuning range and low power. The bottom-level detector is shown in Fig. 4(b) and it detects the bottom level of the VCO s output swing. A self-biased buffer enlarges the output of a VCO into a rail-to-rail swing. So, the output,, of this self-biased buffer and have the same polarity. When goes high and is high, the NOR gate will enable and disable, respectively. The current of the transistor will charge the capacitor,, to increase. When goes low and is low, two cases will be discussed. In Fig. 4(b), if the bottom level of is larger than, the comparator s output goes high and the NOR gate goes low to enable and disable, respectively. The transistor will charge the capacitor,, to increase.for the other case, if the bottom level of is lower than, the comparator s output goes low and the NOR gate goes high to disable and enable, respectively. The transistor will discharge the capacitor,, to decrease.inthe steady state, the voltage on the capacitor,, will track the bottom level of the VCO s swing. For the current compensator in Fig. 4(a), a reference voltage represents the target bottom level of the VCO s swing and it is compared with, by a comparator. When the VCO s bottom level is smaller than the target one or the output common-mode voltage of this VCO is high enough, is larger than. Then, the output of the comparator goes high and enables Q1. The current compensator enables the auxiliary tail current to lower the output common-mode voltage. The timing diagram is shown in Fig. 4(b). Then, it reduces the VCO s bottom level to be lower than. If the above case is not true, Q2 will be enabled and turn on the auxiliary tail current. It further lowers the VCO s bottom level. C. Phase-Locked Loop Fig. 5 shows the proposed PLL. This PLL is composed of a phase-frequency detector (PFD), a digital-controlled CP, a lock detector (LD), a time-to-digital converter (TDC) [8] with a 4-bit encoder, a self-healing VCO, a programmable divider, and a second-order passive loop filter. The programmable divider is

LEE et al.: WIDE-RANGE PLL USING SELF-HEALING PRESCALER/VCO IN 65-nm CMOS 253 TABLE I PARAMETERS OF THE PROPOSED PLL Fig. 6. 4-bit digitally-controlled charge pump. Fig. 4. (a) Gain stage, a bottom-level detector, and a current compensator, and (b) the bottom-level detector. Fig. 7. Die photo. Table I. Since the phase error of a PLL is highly dependent upon thecurrentmismatchofacp.thestaticphaseerrorofapfd is given as (1) Fig. 5. Proposed PLL. composed of a 5-bit counter, a 3-bit swallow counter, a modulus control, and a self-healing divide-by-4/5 prescaler. The division ratio is from 4 to 131. The parameters of this PLL are listed in where is the current difference between the pull-up and pull-down currents, and, is the turn-on time of a PFD, is the averaging current of the pull-up and pull-down currents. When this PLL locks, the LD is enabled to turn on the TDC and an encoder. A 4-bit TDC digitizes this static phase error to reflect the amount of the current mismatching. Then, the digital code of this TDC is used to calibrate the charge pump. The simulated power of this TDC is 0.24 mw. Its timing resolution is 0.3 ns and the dynamic range is 4.8 ns. A 4-bit digitally-controlled CP is shown in Fig. 6. The up current has a nominal value of 200 A and the down current

254 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO. 2, FEBRUARY 2013 Fig. 8. Measured divide-by-5 output for a divide-by-4/5 prescaler with an input clock of 150 MHz at 100 C, when (a) the self-healing circuit disabled, and (b) the self-healing circuit enabled. (Upper trace: Input; Lower trace: Output). Fig. 9. Measured frequency range of this divide-by-4/5 prescaler under different temperatures. is digitally controlled within 180 and 210 A. The minimum current step is chosen as 2 A to relieve the worst-case current mismatch to 1% in this digitally-controlled CP. The traditional replica-biased CP needs an operational amplifier which needs a high gain and its stability must be concerned. In addition, this operational amplifier may consume a static power. The CP calibration can be finished quickly due to this digital calibration. Once the calibration is completed, the digital code is fixed and the TDC is power-downed to save a power. III. DESIGN CONSIDERATIONS A. Self-Healing Prescaler The lowest operation frequency of a TSPC DFF due to a leakage current may limit the frequency range of a TSPC prescaler. For a TSPC DFF of Fig. 2(a), a malfunction occurs as shown in Fig. 2(c). The clock frequency of this TSPC DFF is and let the data D be high. When the rising edge of the clock goes high, goes low as shown in Fig. 2(c). When the clock goes low, the leakage current is charging the parasitic capacitance,,and increases. Since the initial state of Fig. 10. (a) Simulated tuning ranges of a VCO with and without the self-healing technique at different temperature and (b) the measured transfer curve of a VCO with and without the self-healing technique at a room temperature. is low, the leakage current will alter the voltage on the parasitic capacitance,,duringatime interval of as (2)

LEE et al.: WIDE-RANGE PLL USING SELF-HEALING PRESCALER/VCO IN 65-nm CMOS 255 Fig. 11. Measured spectrum and jitter at 855 MHz (a) without and (b) with the self-healing rescaler/vco and the TDC/encoder. To avoid the malfunction, should be lower the threshold voltage of the subsequent stage as By (2) and (3), the lowest clock frequency of this TSPC DFF is (3) (4) For example, 400 na at 25 C, 15 ff, and 0.6 V, the calculated lowest frequency is 22.2 MHz. Note that the leakage current is proportional to the temperature. When the temperature increases, the lowest frequency of (3) is increased, too. The highest frequency of this TSPC DFF is determined by the resistance of the series transistors and the parasitic capacitance. Based on our simulation results, the highest frequency of this TSPC is more than 10 GHz. B. Bottom-Level Detector In the bottom-level detector of Fig. 4(b), a capacitor is used to storage the bottom-level voltage of a VCO. In Fig. 4(b), the transistor is regarded as a resistor. When, the transistor charges toward. During the charging intervals, the voltage is expressed as where, is the equivalent resistance of the transistor,and is the initial voltage during the charging interval. When,and is low, the transistor discharges and the voltage is expressed as (5) (6)

256 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO. 2, FEBRUARY 2013 Fig. 12. (a) Measured spectrum and jitter @ 120 MHz and 100 C, and (b) The measured spectrum and jitter @ 1320 MHz and 100 C. where, is the equivalent resistance of the transistor,and is the initial voltage during the discharging interval. For the timing diagram in Fig. 4(b), the voltage changes from the voltage 0 V to the reference voltage. Assume,therequired time is approximated as Then the required capacitor In this work, the minimum frequency step of this PLL is equal to the reference frequency. For a frequency step of, the voltage step of the control voltage of a VCO is given as is (7) (8) (9) is approx- The required time for this PLL to reach imated as (10) where and are the capacitors of the loop filter and is the CP current. The required frequency acquisition of this PLL to change the frequency of is much longer than.sothe required time should be less than the minimum hopping time of the PLL; i.e.,. By (8) (10), the required capacitor is calculated as (11) Let 16.4 nf, 1.3 nf, 200 ua, 500 k, 1.2 V, 15 MHz, 1.5 GHz/V, and 1 V, the calculated is 1 pf. Note that although the output swing of the VCO is 0.2 V, a full swing output is obtained by a self-biased buffer. A common-mode detector can be used to detect the common-mode voltage of a

LEE et al.: WIDE-RANGE PLL USING SELF-HEALING PRESCALER/VCO IN 65-nm CMOS 257 TABLE II SUMMARY AND COMPARISON VCO instead of this bottom-level one. However, a commonmode detector needs the additional analog buffers with a wide input swing and the large passive resistors and capacitors; i.e., it may increase the power and area. In this work, the proposed bottom-level detector is simple and needs only a 1 pf capacitor. IV. EXPERIMENTAL RESULTS This chip is fabricated in a 65-nm CMOS technology. The die photo is shown in Fig. 8. The active area occupies 0.0182 mm. External capacitors are adopted in the loop filter for this work. The measurement results are discussed as follows. A. Self-Healing Divide-by-4/5 Prescaler An additional self-healing divide-by-4/5 prescaler is configured as a divde-by-5 divider. When the self-healing function is disabled, this divide-by-5 divider works incorrectly for an input clock of 150 MHz at 100 C as shown in Fig. 8(a). With the self-healing function is enabled, this divide-by-5 divider works correctly for an input clock of 150 MHz at 100 C as shown in Fig. 8(b). The operation frequency ranges of this divde-by-5 divider versus temperature are summarized in Fig. 9 with and without the self-healing function, respectively. B. Self-Healing VCO Fig. 10(a) shows the simulated tuning ranges of a VCO with and without the self-healing technique at different temperatures. The self-healing VCO achieves a wide tuning range. Fig. 10(b) shows the measured VCO S transfer curves with and without the self-healing technique, respectively, at a room temperature. Without the self-healing function, the measured frequency range of this VCO is from 105 to 950 MHz. With the self-healing function, the measured frequency range of this VCO is improved and it is from 60 to 1489 MHz. To extend the tuning range of a VCO, a higher gain of the VCO is adopted. However, the phase noise or jitter will be degraded. Assume the current of a VCO is increased to achieve the same tuning range 60 1489 MHz of a self-healing one. The power difference for these two VCOs with and without the self-healing technique is 1.152 mw at 60 MHz. Because of this self-healing technique, the active area of the proposed VCO will be increased. Additional active devices lead to a degradation of the jitter performance for a self-healing VCO, compared to a VCO without a self-healing technique. C. Phase-Locked Loop This PLL is configured with the reference frequency of 15 MHz and the output frequency of 855 MHz. When the self-healing prescaler/vco and the TDC/encoder are disabled, the measured spectrum and jitter are shown in Fig. 11(a). The measured reference spur is -33.42 dbc. The measured rms and peak-to-peak jitters are 43.62 and 284.4 ps, respectively. When the self-healing prescaler/vco and the TDC/encoder are enabled, the measured spectrum and jitter are shown in Fig. 11(b). The measured reference spur is -52.89 dbc. The measured rms and peak-to-peak jitters are 8.03 and 55.6 ps, respectively. This PLL consumes 4.3 mw from 1.2 V supply without buffers. Without the proposed self-healing techniques, this PLL did notworkat100 C. When a self-healing prescaler, a self-healing VCO, and a calibrated CP are turned, the measured spectrum and jitter for this PLL operating at 120 and 1320 MHz and at 100 C are shown in Fig. 12(a) and (b), respectively. Fig. 12(a) shows the measured reference spur is -40.97 dbc. The measured rms and peak-to-peak jitters are 57.71 and 422 ps, respectively. Fig. 12(b) shows the measured reference spur is -41.2 dbc. The measured rms and peak-to-peak jitters are 7.02 and 52.4 ps, respectively. Table II gives the performance summary of the proposed PLL and other works in literature. The proposed presents several

258 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO. 2, FEBRUARY 2013 techniques to avoid the circuits to degrade by the process variability and leakage current in nanoscale CMOS technology. Due to additional active devices, the jitter performance of a selfhealing PLL will be degraded, compared to a PLL without a self-healing technique. In addition, the active area and power of this PLL will be increased because of these self-healing circuits. I-Ting Lee was born in Tainan, Taiwan, in 1985. He received the B.S. degree in electrical engineering from National Sun Yat-Sen University (NSYSU), Kaohsiung, Taiwan, in 2007. He is currently pursuing the Ph.D. degree in electronics engineering, National Taiwan University, Taipei, Taiwan. His current research interests include frequency synthesizers and high-speed wireless and wireline transceivers. V. CONCLUSION A wide-range PLL is fabricated in a 65-nm CMOS process. To deal with the process variability and leakage current in nanoscale CMOS process, a self-healing prescaler, a self-healing VCO, and a calibrated CP are presented. Experimental results are given to demonstrate the feasibility. Yun-Ta Tsai wasbornintaipei,taiwan,in1984.he received the B.S. degree in chemistry and the M.S. degree in electronics engineering from National Taiwan University (NTU), Taipei, Taiwan, in 2008 and 2010, respectively. He is currently with PixArt Imaging Inc, Hsinchu, Taiwan. His current research interests include PLLs and ADCs. ACKNOWLEDGMENT The authors would like to thank MediaTek, Taiwan, for chip fabrication. REFERENCES [1] L. L. Lewyn, T. Ytterdal, C. Wulff, and K. Martin, Analog circuit design in nanoscale CMOS technologies, Proc. IEEE, vol. 18, no. 11, pp. 1687 1714, Oct. 2009. [2] J. M. Wang, Y. Cao, M. Chen, J. Sun, and A. Mitev, Capturing device mismatch in analog and mixed-signal designs, IEEE Circuits Syst. Mag., vol. 8, no. 4, pp. 137 144, Dec. 2008. [3] K. Agawa, H. Hara, T. Takayanagi, and T. Kuroda, A bitline leakage compensation scheme for low-voltage SRAMs, IEEE J. Solid-State Circuits, vol. 36, no. 5, pp. 726 734, May 2001. [4] R. Krishnamurthy, A. Alvandpour, G. Balamurugan, N. Shanbhag, K. Soumyanath, and S. Borkar, A 130-nm 6-GHz256 32b leakage-tolerant register file, IEEE J. Solid-State Circuits, vol. 37, no. 5, pp. 624 632, May 2002. [5] R. Holzer, A 1 V CMOS PLL designed in high-leakage CMOS process operating at 10 700 MHz, in Proc. IEEE Int. Solid-State Circuits Conf., 2002, pp. 272 273. [6] J.Maneatis,J.Kim,I.McClatchie,J.Maxey,andM.Shankaradas, Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLL, IEEE J. Solid-State Circuits, vol. 38, no. 11, pp. 1795 1803, Nov. 2003. [7] C. Y. Yang, G. K. Dehng, J. M. Hsu, and S. I. Liu, New dynamic flip-flops for high-speed dual modulus prescaler, IEEE J. Solid-State Circuits, vol. 33, no. 10, pp. 1568 1571, Oct. 1998. [8] P. Dudek, S. Szczepanski, and J. Hatfield, A high-resolution CMOS time-to-digital converter utilizing a vernier delay line, IEEE J. Solid- State Circuits, vol. 35, no. 2, pp. 240 247, Feb. 2000. [9] C.N.ChuangandS.I.Liu, A1Vphaselockedloopwithleakage compensation in 0.13 m CMOS technology, IEICE Trans. Electron., vol. E89-C, pp. 295 299, Mar. 2006. [10] C. C. Hung and S. I. Liu, A leakage-suppression technique for phaselocked systems in 65 nm CMOS technology, in Proc. IEEE Int. Solid- State Circuits Conf., 2009, pp. 400 401. Shen-Iuan Liu (S 88 M 93 SM 03 F 10) was born in Keelung, Taiwan, Republic of China, in 1965. He received the B.S. and Ph.D. degrees in electrical engineering from National Taiwan University (NTU), Taipei, Taiwan, in 1987 and 1991, respectively. During 1991 1993, he served as a second lieutenant in the Chinese Air Force. During 1991 1994, he was an Associate Professor with the Department of Electronic Engineering, National Taiwan Institute of Technology. He joined the Department of Electrical Engineering, NTU, in 1994, where he has been a Professor since 1998 and a distinguished Professor since August 2010. His research interests include analog and digital integrated circuits and systems. Dr. Liu has served as chair of the IEEE SSCS Taipei Chapter in 2004 2008, which achieved the Best Chapter Award in 2009. He has served as general chair of the 15th VLSI Design/CAD Symposium, Taiwan, (2004) and as Program Co-chair of the Fourth IEEE Asia-Pacific Conference on Advanced System Integrated Circuits, Fukuoka, Japan (2004). He was a recipient of the Engineering Paper Award from the Chinese Institute of Engineers in 2003, the Young Professor Teaching Award from MXIC Inc., the Research Achievement Award from NTU, and the Outstanding Research Award from National Science Council in 2004. He has served as a technical program committee member for ISSCC in 2006 2008, IEEE VLSI-DAT in 2008 2012, and A-SSCC in 2005 2011. He also served as the technical program committee co-chair and chair for A-SSCC 2010 and 2011, respectively. He was an Associate Editor for IEEE JOURNAL OF SOLID-STATE CIRCUITS in 2006 2009 and a Guest Editor for IEEE JOURNAL OF SOLID-STATE CIRCUITS Special Issue in 2008 December and 2012 November. He was an Associate Editor for IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS PART II: EXPRESS BRIEFS in 2006 2007. He was an Associate Editor for IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS PART I: REGULAR PAPERS in 2008 2009. He was the Editorial Board of Research Letters in Electronics in 2008 2009. He is also an Associate Editor for the Institute of Electronics, Information and Communication Engineers (IEICE) Transactions on Electronics from 2008. He is an Associate Editor for ETRI Journal, and also an Associate Editor for Journal of Semiconductor Technology and Science, Korea, from 2009. He also joins in Editorial Board for International Scholarly Research Network (ISRN) Electronics from 2011. He is a member of IEICE.