NLOG & TELECOMMUNICTION ELECTONICS LOTOY EXECISE 5 Lab 6: DIGITL TO NLOG ND NLOG TO DIGITL CONVETE Goal nalyze the behavior of a 6-bit D/ converter. Evaluate linear and nonlinear errors, nonmonotonicy and glitches and observe the effects of circuit parameters on these errors. Modify the circuit to obtain a tracking nalog-to-digital converter. Observe the converter behavior and the limits of tracking. Specifications Use the output of CMOS logic circuits as voltage switches, driving a set of weighted resistors or a ladder networks with = 13,5 kω. Use the TL081 Op. mp. and the LM 331 voltage comparator. counter can generate the sequence of digital values to test the DC. Use CD4040 or CD4029 (this last is required to build the DC) The power supply voltage for logic circuits is 8V; this same voltage is used as reference for the weight network. nalog circuits, when required, should use the same 0-8 V supply. The issues marked by a in the following must be specifically addressed in the report. L I C D E F G H I C D E F G H L WNING The clock for the counter should have levels close, but not exceeding, the GND Val range (as for any logic circuit). Usually this requires to set an offset on the signal source. Verify the voltage level before connecting the external clock generator. Most common problems and mistakes - Not considering the scaling factor of scope probes. - Using the scope for direct differential measurements (probe ground not connected to circuit ground). - Wrong connection from the counter to the weight network (the staircase is not continuous). - Faults in the ladder network: verify internal connections in the provided networks; some wires could be broken. - When using multiple CD4029, or the CD4029 and other counters, verify that all subcounters of the counter advance in the same direction (up or down). If direction changes among differente parts, some staircase segments have inverted slope. 1
Design The diagrams in figure 1 represent a 4-bit DC, and are provided only as examples. The actual goal is to design and build a 6-bit DC; the counter must be extended with other devices (dual D-FF CD4013, or another CD4029, or larger counter such as the CD4040). The 4-bit circuit will be used in the last section, since the tracking DC requires a bidirectional counter. Figure 1a shows a 4-bit current output DC, using scaled resistors for the weight network. This is the most basic circuit, and to get the actual circuit used in this experience it must be modified from current to voltage output. CD 4029 Q1 Q2 Q3 Q4 CD 4029 Q1 Q2 Q3 Q4 1 2 3 4 1 2 3 4 a) Iu b) Vu Figure 1 The equivalent output resistance of the weight network ( in figure 1a) is constant, and we can use as output variable the open circuit voltage instead of the short circuit current, as in figure 1b. This is equivalent to a Norton-Thevenin transformation. Figure 2 shows a similar 6-bit circuit. The only difference is the CMOS counter: the CD4029 is 4-bit Up/Down, so can be used to build a tracking DC; the CD4040 is 12-bit, and allows to build DC with higher resolution (smaller steps). Nominal ctual 1 k 820 k 2 k 390 k 3 k 180 k 4 k 100 k 5 k 47 k 6 k 22 k CD 4040 Q1 Q2 Q3 Q4 Q5 Q6 Q7. Q12 1 2 3 4 5 6 Figure 2 Va oth 4-bit and 6-bit circuits use weighted networks, with nominal and actual (standard E12 sequence) values, as in figure 2. The use of standard resistor values brings some nonlinearity in the (D) characteristic; the exact values can be obtained with series/parallel of resistors, taken from the same fabrication batch, to reduce random errors. List the OM, specifying the devices actually used, with reference to the circuit schematic. Draw the schematic diagrams of all the circuits you build and test, with pin numbers of ICs. 2
The set of weighted resistors is then replaced by a ladder network (4-bit in figure 3), which can be easily extended to N bits. 6-bit - ladder with =13.5kΩ and connections as in figure 4 is available in the lab. The 6- bit network must be driven by a 6-bit counter, built with a pair of 4-bit counter CD4029, or a 12- bit counter CD4040. CD 4029 Q1 Q2 Q3 Q4 L I Vu C D E F G H I Figure 3 When using the ladder network, verify carefully the internal wiring (some interconnections may be broken). C D E F G H L Figure 4 The following section requires measurement of D/ characteristic, and comparison of experimental results with nominal values, to evaluate linear and nonlinear errors. Non-linear errors are related with the equivalent ON resistance of the switches ( ON ), which can be evaluated from the output I/V parameters given in the data sheet, or by direct measurement of output voltage with load. Evaluate the ON resistance of the CMOS outputs form Data Sheet information, and define a procedure to measure this resistance. Simulation Using PSPICE (or any other electrical level simulation program), verify the circuit operation, with nominal value weighted resistors and with the ladder network. 3
Measurements s first step wire the counter. emember that with CMOS circuits LL inputs must be connected to GND or Vdd, to get a constant logic state. Draw the schematic diagrams of all the circuits you build and test, with pin numbers of ICs; this makes more easy the wiring, the circuit verification, and the measurements. Topographic diagrams can help in circuit preparation, but do not have functional information and should not be included in the report. efore connecting the external clock generator verify the voltage level. The clock should have levels close, but not exceeding, the GND Val range (as for any logic circuit). Verify the correct operation of the counter without connecting any weight network. Synchronize the scope with lowest frequency signal, and verify frequency and phase of all outputs. Connect the weight network and verify the output voltage. Start with 4 bits, add other two later. The output voltage should be a sawtooth wave; with N-bit counter, the sawtooth is actually a staircase with 2 N discrete levels. Measure the full-scale output voltage and compare with the value evaluated in the Design section. The first step for DC characterization is to measure the output voltage for each input configuration. Use a low-frequency clock, or single manual pulse (with a debouncer circuit) to advance the counter from 0 to full scale. set of LEDs can be connected at the counter output to verify the counting sequence (the LEDs modify the branch currents and the output voltage; verify the changes and discuss the related errors). The following measurement can be carried out with LEDs connected or without the LEDs; evaluate the difference and specify in which condition the measurements are actually carried out. dvance the counter in single steps and measure the DC output for each state. Use the most accurate instrument available, without truncation or rounding: the next step requires computing differences, and this is very sensitive to the measurement errors. If the external clock generator does not allow issuing single pulses, use a manual switch with debouncer circuit (e.g. a S FF built from NND gates, or a CD 4013 D-FF). From the measurements obtain the best approximating straight line (minimize the sum of differences squared least squares method), and from the straight line parameters get the offset and gain errors. Evaluate and plot absolute and differential nonlinearity (using as reference the best approximating straight line). Evaluate (and show in the diagrams) the measurement errors. Compare measurement errors with errors caused by tolerances and on. Modify (by about 10%) the resistor in the branches corresponding to MS, MS-1, MS- 2,, LS (one branch at a time - insert another in series or in parallel). Verify and discuss the effect of each change, and the relation between branch weight and value/position change in the characteristic. Insert on the counter outputs (one at a time) small capacitors (50 pf to 1 nf) to change the switching delay on that bit. Verify and discuss the effects on the DC characteristic. 4
4 Demo experience Visualize on the scope the complete DC characteristic, and verify the effects of errors in the weight network. To introduce errors, modify the values of weighted currents, by placing resistors in series or parallel to the ladder elements. Observe the position and the amount of the errors directly on the full characteristic. Increasing the clock frequency glitches become visible. capacitor at the output increases the switching delay of the specific bit, and can be used to cause glitches. Verify and discuss their position, amount, and sign. Figure 5 shows, for a 4-bit DC, the correspondence between counter outputs and analog output. When errors or delays are introduced, their effects can be seen in the position where the bit changes state. 5 Differential nonlinearity Differential nonlinearity errors are obtained by modifying the weighted currents, as discussed in the previous section. The following figures show the effects of errors introduced in different branches in a 64-step (6-bit) ramp. Here a resistance is connected in parallel to the MS branch, increasing the corresponding current. The weight increment on MS causes a raise in the second half of the characteristic, where MS = 1. If the resistance modifies the MS-1 branch, the fourth 1 and 2 (where MS-1 = 1) are affected. The amount of branch error is always the same, but the effect on output is halved due to the lower branch weight. Here at half of full scale we can see non-monotonicity error. Figure 5 s we move the resistor to the MS-2 branch, the error occurs at (full scale)/8 points, with halved amplitude. Now the transfer function is fully monotone 5
6 Glitches When the MS-1 switching is delayed (by adding a capacitor on the corresponding counter output), glitches appear at half and quartes of the characteristic. The polarity of glitches reflects the direction of MS-1 switching. delay in the 0 to 1 transition introduces the temporary states (0011)-0000- (0100) and (1011)-1000-(1100): glitches towards GND: in the figure; a delay in the 1 to 0 transition introduces the glitch towards Vdd labeled. The CD4040 counter has ripple clock, and outputs do not switch at the same time. Glitches can be sees simply bay expanding the oscilloscope time base, and raising the clock frequency. 6 Evaluation of the best approximating straight line From the measured values y i for each step x i we can evaluate best approximating straight line y = mx + n by minimizing the total square error E evaluated for N points. N 1 E ( y mx n) i0 i i 2 The minimum of error E can be evaluated zeroing the partial derivatives vs m and n. E 2 E mxi -xy i inxi 0 nn-yim xi 0 m n i i i i i Solving for n, m, with N = 64: m 63 1 63 63 63 63 xy i i xi yi 0 64 yi m xi i i0 i0 i0 i0 n 2 63 63 64 2 1 xi xi i0 64 i0 The parameters of the best approximating line y m0x n0 are: n0 0 m0 10V / 63 0.1562 V LS Gain error: Slope change between ideal transfer function and approximating straight line: g m m 0 Offset error: Shift of intesection with y axis from nominal value: off n n 0 Nonlinearity error evaluation The analog values to be used to evaluate the nonlinearity error are obtained from y = m 0 x + n 0, where m and n are the parameters evaluated above. 6
7 - /D converter The circuit can be modified into a 4-bit nalog to Digital tracking converter, using a comparator to control the count direction of the CD4029. Keep only the weight network connected to the CD4029 (weighted resisitors or ladder), and close the loop with the comparator as in the figure. The comparator compares the Vu from the DC with the input signal Vi. Through the U/D command, the counter is incremented if Vu < Vi, and decremented if Vu > Vi. CD 4029 Q1 Q2 Q3 Q4 U/D Vu Vi 6 The voltage comparator can use as power supply +-10 V, with a limiter circuit must be inserted between the comparator and the counter, as shown in the figure (or with diode clamps to GND and Vdd). If the Op mp or comparator allows rail-to-rail input common mode, use 0 and +8V (or the supply voltage used for the logic circuit); in this case no protection is needed. For the comparator use an Op. mp TL081, or LM331. This last has an Open Collector output; use a pullup resistor to Vdd, and no need for protection circuit. To verify the converter operation apply a sine input signal sligthly less than full scale ad low frequency (the signal maximum slew rate must be less than the DC slew rate d/tck. The picture shows Vi and Vu: Vi is the sinewave input, and Vu is the signal rebuit by the DC which changes to approximate Vi. The difference Vi Vu represents the quantization error. 7
With a proper time scale the tracking steps can be visualized: constant amplitude steps (1 LS) with positive or negative sign. When the signal Vi changes less than 1 LS (as in the part within the yellow ellipse) the rebuilt signal Vu is a sequence of + and steps. When the input signal frequency increases, the Vi slew rate cannot be followed by Vu: this represents a (dynamic) overload error. The rebuilt signal Vu becomes a triangular wave, with a slope corresponding to the maximum slew rate of Vu, that is d/tck. The countes status can be visualized by LEDs connected to the outputs. The current sinked by the LEDs introduces an error, higher for MSs. To limit this error, the LED current should less than 1 m (4,7 KΩ series resistances). nalysis of results Compare the specs with simulation results and with measurements on the actual circuit. Discuss any discrepancy. Lab report The report must contain: - (short) summary of the design procedures. - complete schematic diagram, with component labels pointing to the part list, and IC pin numbers (NOT a topographic diagram). - complete part list, with all information for component acquisition (type, value, other parameters, ). - esults of measurements, - Discussion of results, and comparison with expectations The (D) transfer function looks quite good (expecially with the ladder network). To show the difference between ideal and actual behavior, plot differential and integral nonlinearity, NOT the full (D) transfer function. For the other sections follow the instructions of the general lab guide. 8