Intellect Amplifier, Current Clasped and Filled Current Approach Sense Amplifiers Techniques Based Low Power SRAM

Intellect Amplifier, Current Clasped and Filled Current Approach Sense Amplifiers Techniques Based Low Power SRAM V. Karthikeyan 1 1 Department of ECE, SVSCE, Coimbatore, Tamilnadu, India, Karthick77keyan@gmail.com Abstract: Low power static random access memory (SRAM) is crucial since it takes a large fraction of total power in high performance processors. In modern SRAM, sense amplifiers are used to retrieve the stored memory data by amplifying the small signal variations in Bit Lines (BL).Large bit line capacitance and reduced voltage swing makes sense amplifier more power hungry. So new current sensing techniques that are independent of bit line and data line capacitances are needed this paper describes about current conveyor based sense amplifier, current latched sense amplifier and full current mode sense amplifiers. Extensive simulation based on industrial standard 1v/45nm CMOS technology, have verified that full current mode sense amplifier outperforms the other two designs in terms of speed and power. Keywords: Sense amplifiers, low power SRAM, bit line and data line capacitance, voltage swing Introduction Fast low power SRAMs have become a critical component of many VLSI chips. This is especially true for microprocessors, where the on-chip cache sizes are growing with each generation to bridge the increasing divergence in the speeds of the processor and the main memory [1]. Simultaneously, power dissipation has become an important consideration both due to the increased integration and operating speeds, as well as due to the explosive growth of battery operated appliances. As a result, low-voltage operation is inevitable for future ULSI applications [3]. However, reducing the supply voltage results in a serious problem in memory circuits because the time delay to sense the signals from the memory cells increases tremendously. Moreover, scaling the supply voltage, the readout voltage amplitude on the bit-lines is reduced. As a result, sense amplifiers with high sensitivity are required to detect these signals [4],[5],[6].As the size of memories become larger and larger, bit line capacitances rise and hence reduction in bit line voltage swing occurs. Rising bit line capacitances and reduced voltage swings along with the reduction in transistor parameters made the voltage sense amplifiers more power hungry and less reliable. So the voltage mode could not keep up to their performance thereby leading to the need for faster sensing techniques that are not affected by the bit line capacitances. Current mode sense amplifiers are applied to reduce the sense circuit delays as they provide low common input/output impedances[8]. The small input impedance presented to the bit lines result in reduced voltage swings, cross talk and substrate currents. The current mode sense amplifier coverts and amplifies a small current difference into CMOS voltage levels. In this paper three new current sensing techniques, namely current conveyor [4],[5],current latched[9],[10] and full current mode sense amplifier[2] designs are compared. Simulation using SPICE shows that full current mode sense amplifier outperforms others in terms of power and delay. Current Conveyor Based Sense Amplifier The current conveyor has (ideally) zeroed input resistance during sensing [4]. This property makes it insensitive to the bit-line capacitance.the schematic of modified current sense amplifier [5] is depicted in fig 1. It consists of nine PMOS (P3, P4, P5, P6, P7, P8, P9,P10 and P99) devices residing in a common n-well. Unlike the conventional conveyor, the new circuit has the quality of transforming into a latch soon after differential current signals appear at nodes A and B. This 11

characteristic gives the new circuit high-speed, low-power operation. It also includes a conventional CMOS sense amplifier [6].It comprises three current mirrors, namely (N3, N4), (N5, N6), and (P23, P24). Together with an output inverter, INV2, they detect, amplify and convert the differential signals at the data lines to a CMOS logic level output. Transistors P1 and P2 are used to pull the bit lines close to the supply voltage to attain memory cell stability and soft-error immunity. They are biased in the triode region (grounded gate) and configured to operate at low supply voltages. Transistor P99 turns on only when there is no sensing. It forces the voltage at the sources of P9 and P10 to be equal. The bit and data lines capacitances are denoted CBL and CDL, respectively, and RS and CS are the row and column selectors, respectively. Fig.1: Schematic of modified current conveyor based sense amplifier Consider both RS1 and CS2 lines being activated during a read cycle. Differential current signals then appear at the common bit lines. Since no differential capacitor discharging is required to sense the cell data, these signals propagate almost instantaneously to the current conveyor. Sufficient time delay is provided by inverter, INVl, to allow differential currents to appear at nodes A and B before turning off transistors P6 and P7. As soon as transistors P6 and P7 are off, the conveyor transforms into a latch. Since the right-hand leg of the conveyor passes more current than the left-hand leg, the voltage at node B raises faster than that at node A. Owing to small capacitances at nodes A and B, the regenerative effect of the conveyor is very rapid. Because P3 turns off after the flip-flop action, there is only one bit line path that allows the current to flow through the conveyor. Consequently, a large differential voltage is developed across the data lines, thereby enhancing the response speed of the sense amplifier. In addition, with only one branch of current flowing through the conveyor, the power consumption of the circuit is significantly reduced. 12

Fig.2: Voltage at data lines of modified and conventional current conveyor. From fig.2, it is clear that the new conveyor generates a large differential voltage at the data lines and as a result, its sensing speed is much faster than its conventional counterpart. Current Latched Sense Amplifier In current latched sense amplifiers (CLSA) input nodes and output nodes are isolated.fig.3 shows the circuit implementation of modified current latched sense amplifier [10]. Unlike CLSA, modified CLSA has less number of transistor stages and can be used for low voltage applications. The operation of the circuit is in two phases. In pre charge mode data at the output nodes must be cleared and sense amplifier prepares for next sensing stage. As the sensing signal SE=0 and SE#=1 MP1, MP4, MN5, MN6 are turned on and MP5, MP6 are tuned off. Nodes 1 and 2 are pre charged to GND level by MN5, MN6 so MN4, MN3 will be cut off. Outputs are pre charged to VDD by pre charge transistors MP1, MP4. Finally, the cross-coupled amplifier constructed by MP2, MP3, MN1 and MN2 will convert and amplify the current difference to a voltage difference between output nodes O, and O#. For a very short time, the full swing logic value appears on output nodes. Fig 4 shows the simulation waveform of current latched sense amplifier. 13

Fig.3: Schematic of modified current latched sense amplifier. Fig.4: Waveforms at several nodes of current latched sense amplifier Full Current Mode Sense Amplifier This paper proposes a full current mode sense amplifier. Fig 5 depicts the schematic of the full current mode sense amplifier. It consists of two sensing stages: local and global. Cross coupled inverters are utilized to sense both the sensing stages. The local sensing stage is formed by four pmos (P3-P6) and three nmos (N1, N2 and N7) transistors. While P3 and P4 act as a column switch, the rest of the transistors establish the local cross-coupled inverters [7], which are responsible for transferring the BL differential currents to the DLs. The global sensing stage consists of three pmos (P7-P9) and five nmos (N3-N6 and N8) transistors. During the standby period, P3 and P4 are turned off to block any BL currents. The Column Select and Global Enable (CS and GEN) signals turn on N7 and N8 to equalize the nodes A, B and C, D to the same potential respectively. Meanwhile, the two pre-charge transistors N5 and N6 are turned on to pre-charge both DLs to ground. At the same time, P9 is turned off to save power. Since P9 is off and the DLs are pre-charged to ground, C and D are also at low potential during standby. As a result, both the nmos of the output inverters are in the cut-off region and no DC current is dissipated by these output buffers. This topology ensures that the standby current of the circuit is low, and thus the power dissipation is kept at minimum level. Consider both RS1 and CS2 being activated during a read operation. The pre-charge signal (PRE) turns N5 and N6 off, allowing the DL voltages to change freely. The memory cell at the upper row and right column will be selected, resulting in a small current flowing from the complementary bit-line (BLB -read as Bit-line-bar) into the cell and discharges the BLB to allow, P3 and P4 are turned on to transfer the bit-line potentials to the inputs of the local cross-coupled inverter. 14

Fig.5: Schematic of full current mode sense amplifier with a simplified read-cycle only memory system. At the same time, N7 is turned off to activate the local cross-coupled inverters. This building block senses the voltage difference at the source terminals of P5 and P6 and quickly finishes its latching process. Hence, node A is pulled to VDD while node B is discharged to ground. More importantly, during this latching process, the pulsing current flowing from the N2 to the DLB is much higher than that from the N1 to the complementary DL. These currents charge up the CDLs and a voltage difference is established across the DLs, which is subsequently amplified by the global sensing stage. Once the latching process of the local sensing stage is completed, P9 is turned on while N8 is turned off. A similar process as local cross-coupled inverter takes place and the intermediate outputs are obtained at nodes C and D. These two voltages are then fed to the output buffers to get the full CMOS logic levels. It is worth mentioning that the global sensing stage can only be activated after the latching process of the local amplifier finished. 15

Fig.6: Waveform at various nodes full current mode sense amplifier. Fig 6 shows the simulation waveform of full current sense amplifier. After latching, the crosscoupled configuration is in the stable stage and no additional current is consumed and hence the power dissipated on the BLs and DLs is optimized. Furthermore, the new design s sensing delay is essentially equal to twice of the switching time of the cross-coupled inverters. Therefore, the overall performance of the new design is superior when compared to the other circuits, in terms of both sensing delay and power consumption. Power and Sensing Delay Comparison To compare the three sensing techniques, all the three designs were simulated in a 45nm CMOS technology with VDD=1v.They are comparatively evaluated based on the same area in terms of the propagation delay and average power dissipation with different bit line and data line capacitances. 16

Fig.7: Average power and sensing delay versus CBL for the designs in comparison Each memory cell in the SRAM core was alternatively activated by the corresponding column select and row select signals. The order in which the memory cells are activated are identical for all designs in comparison. Behaviour of each design is analyzed by measuring average power consumption and sensing delay against a wide range of CDL and CBL (fig 8 and fig 9). All the three designs are insensitive to bit line capacitance. Table I shows the comparison of three designs under consideration. It depicts that the full current mode sense amplifier is better in terms of speed and power than current conveyor and current latched sense amplifiers Fig. 8: Average power and sensing delay versus CDL for the designs in comparison. TABLE I Designs Full current mode[2] Current conveyor[5] Current latched[10] Sensing delay(ns) Average power(mw) 0.39 0.25 1.05 1.05 1.47 0.59 Conclusion Three new sensing techniques were designed in 45nm CMOS technology. According to the results, as the full current mode sense amplifier utilizes cross coupled inverters for both local and global sensing it outperforms other designs in terms of speed and power by 64% and 45% respectively. It can be concluded that current conveyor can be used for high speed applications and current latched sense amplifiers can be preferred for better power performance. Full current mode sense amplifier is a wise choice was ultra high speed and ultra low power is of major concerns. 17

References [1] E. Grossar, Technolgy-aware design of SRAM circuits, Ph.D. dissertation, Dept. Electron., Katholieke Univ., Leuven, Belgium, 2007 [2] Anh-Tuan Do, Zhi-Hui Kong, Kiat-Seng Yeo, and Jeremy Yung Shern Low, Design and Sensitivity Analysis of a New Current-Mode Sense Amplifier for Low-Power SRAM, IEEE transactions on VLSI systems, VOL. 19, NO. 2, Feb 2011. [3] Manoj Sinha, Steven Hsu, Atila Alvandpour, Wayne Burleson, High-Performance and Low-Voltage Sense-Amplifier Techniques for sub-90nm SRAM [4] K. S. Yeo, W. L. Goh, Z. H. Kong, Q. X. Zhang, and W. G. Yeo, Highperformance,lowpower current sense amplifier using a cross-coupled current-mirror configuration, IEE Proc. Circuits Dev. Syst., vol. 149,no. 5 6, pp. 308 314, Oct./Dec. 2002. [5] H. C. Chowand S. H. Chang, High performance sense amplifier circuit for low power SRAM applications, in Proc. IEEE Int. Symp. Circuits Syst., 2004, vol. 2, pp. 741 744. [6] K. S. Yeo, New current conveyor for high-speed low-power current sensing, IEE Proc. Circuits Dev. Syst., vol. 145, no. 2, pp. 85 89, Apr.1998. [7] A. Hajimiri and R. Heald, Design issues in cross-coupled inverter sense amplifier, in Proc. IEEE Int. Symp Circuits Syst., 1998, vol. 2,pp. 149 152. [8] E. Seevinck, P. J. V. Beers, and H. Ontrop, Current-mode techniques for high-speed VLSI circuits with application to current SA for CMOS SRAM s, IEEE J. Solid-State Circuits, vol. 26, no. 5, pp. 525 536,May 1991. [9] R. Singh and N. Bhat, An offset compensation technique for latch type sense amplifier in high-speed low-power SRAMs, IEEE Trans. Very Large Scale Integr (VLSI) Syst., vol. 12, no. 6, pp. 652 657, Jun. 2004. [10] Hwang-Cherng Chow and Shu-Hsien Chang, High performance Sense Amplifier Circuit for Low Power SRAM Applications 18