NDFNZ N-Channel Power MOSFET V,.7 Features Low ON Resistance Low Gate Charge ESD Diode Protected Gate % Avalanche Tested % R g Tested These Devices are Pb Free, Halogen Free/BFR Free and are RoHS Compliant ABSOLUTE MAXIMUM RATINGS (T C = C unless otherwise noted) Rating Symbol NDF Unit Drain to Source Voltage V DSS V V DSS (@ T Jmax ) R DS(ON) (MAX) @ A V.7 Ω N Channel D () Continuous Drain Current, R JC (Note ) I D A Continuous Drain Current T A = C, R JC (Note ) Pulsed Drain Current, t P = s I D. A I DM A G () Power Dissipation, R JC P D 39 W Gate to Source Voltage V GS ±3 V S (3) Single Pulse Avalanche Energy (L =. mh, I D = A) E AS 3 mj ESD (HBM) (JESD A) V esd 39 V RMS Isolation Voltage (t =.3 sec., R.H. 3%, T A = C) (Figure 3) V ISO V Peak Diode Recovery (Note ) dv/dt. V/ns Continuous Source Current (Body Diode) I S A Maximum Temperature for Soldering Leads Operating Junction and Storage Temperature Range T L C T J, T stg to C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.. Limited by maximum junction temperature.. I S A, di/dt A/ s, V DD = % BV DSS 3 NDFNZG TO FP CASE D 3 NDFNZH TO FP CASE AH ORDERING AND MARKING INFORMATION See detailed ordering, marking and shipping information in the package dimensions section on page of this data sheet. Semiconductor Components Industries, LLC, 3 February, 3 Rev. Publication Order Number: NDFNZ/D
NDFNZ THERMAL RESISTANCE Parameter Symbol NDFNZ Unit Junction to Case (Drain) R JC 3. C/W Junction to Ambient Steady State (Note 3) R JA 3. Insertion mounted ELECTRICAL CHARACTERISTICS (T J = C unless otherwise noted) Characteristic Test Conditions Symbol Min Typ Max Unit OFF CHARACTERISTICS Drain to Source Breakdown Voltage V GS = V, I D = ma BV DSS V Breakdown Voltage Temperature Coefficient Drain to Source Leakage Current Reference to C, I D = ma V DS = V, V GS = V BV DSS /. V/ C T J C I DSS A C Gate to Source Forward Leakage V GS = ± V I GSS ± A ON CHARACTERISTICS (Note ) Static Drain to Source On Resistance V GS = V, I D =. A R DS(on)..7 Gate Threshold Voltage V DS = V GS, I D = A V GS(th) 3. 3.9. V Forward Transconductance V DS = V, I D = A g FS 7.9 S DYNAMIC CHARACTERISTICS Input Capacitance (Note ) C iss 97 373 pf Output Capacitance (Note ) V DS = V, V GS = V, f =. MHz C oss 7 Reverse Transfer Capacitance (Note ) C rss 3 Total Gate Charge (Note ) Q g 3 7 nc Gate to Source Charge (Note ) V DD = 3 V, I D = A, Q gs. 9. Gate to Drain ( Miller ) Charge (Note ) V GS = V Q gd 3 Plateau Voltage V GP. V Gate Resistance R g... RESISTIVE SWITCHING CHARACTERISTICS Turn On Delay Time t d(on) ns Rise Time V DD = 3 V, I D = A, t r 3 Turn Off Delay Time V GS = V, R G = Ω t d(off) Fall Time t f 3 SOURCE DRAIN DIODE CHARACTERISTICS (T C = C unless otherwise noted) Diode Forward Voltage I S = A, V GS = V V SD. V Reverse Recovery Time V GS = V, V DD = 3 V t rr 39 ns Reverse Recovery Charge I S = A, di/dt = A/ s Q rr 3. C. Pulse Width 3 s, Duty Cycle %.. Guaranteed by design.
NDFNZ TYPICAL CHARACTERISTICS I D, DRAIN CURRENT (A) T J = C 7. V V V GS = V. V. V. V. V. V. V. V. V I D, DRAIN CURRENT (A) V DS = 3 V T J = C 3 T J = C T J = C 7 V GS, GATE TO SOURCE VOLTAGE (V) Figure. On Region Characteristics Figure. Transfer Characteristics R DS(on), DRAIN TO SOURCE RESISTANCE ( )..7.7.. T J = C I D = A 7 9 V GS, GATE TO SOURCE VOLTAGE (V) R DS(on), DRAIN TO SOURCE RESISTANCE ( )..7.7... T J = C. 7. I D, DRAIN CURRENT (A) V GS = V. Figure 3. On Resistance vs. Gate Voltage Figure. On Resistance vs. Drain Current and Gate Voltage R DS(on), DRAIN TO SOURCE RES- ISTANCE (NORMALIZED).7..7..7. V GS = V I D = A 7 I DSS, LEAKAGE (na), V GS = V 3 T J = C T J = C T J, JUNCTION TEMPERATURE ( C) Figure. On Resistance Variation with Temperature Figure. Drain to Source Leakage Current vs. Voltage 3
NDFNZ TYPICAL CHARACTERISTICS C, CAPACITANCE (pf) 3 3 C iss C rss C oss 7 V GS = V T J = C f = MHz 7 V GS, GATE TO SOURCE VOLTAGE (V) Q gs V DS Q gd QT V GS I D = A T J = C 3 3 3 Q g, TOTAL GATE CHARGE (nc) Figure 7. Capacitance Variation Figure. Gate to Source and Drain to Source Voltage vs. Total Charge t, TIME (ns) V DD = 3 V I D = A V GS = V t d(off) t r t f t d(on) I S, SOURCE CURRENT (A) V GS = V T J = C R G, GATE RESISTANCE ( ) Figure 9. Resistive Switching Time Variation vs. Gate Resistance I D, DRAIN CURRENT (A)... V GS 3 V Single Pulse T C = C dc R DS(on) Limit Thermal Limit Package Limit ms ms.. s s Figure. Maximum Rated Forward Biased Safe Operating Area for NDFNZ..7..9 V SD, SOURCE TO DRAIN VOLTAGE (V) Figure. Diode Source Current vs. Forward Voltage.
NDFNZ TYPICAL CHARACTERISTICS R(t) ( C/W). Duty Cycle = % % % % % %... Single Pulse..... PULSE TIME (sec) Figure. Thermal Impedance for NDFNZ R JC = 3. C/W Steady State LEADS HEATSINK. MIN Figure 3. Mounting Position for Isolation Test Measurement made between leads and heatsink with all leads shorted together. *For additional mounting information, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
NDFNZ ORDERING INFORMATION NDFNZG NDFNZH Order Number Package Shipping TO FP (Pb Free, Halogen Free) TO FP (Pb Free, Halogen Free) Units / Rail Units / Rail For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD/D. MARKING DIAGRAMS Gate NDFNZG or NDFNZH AYWW Source Drain TO FP A = Location Code Y = Year WW = Work Week G, H = Pb Free, Halogen Free Package
NDFNZ PACKAGE DIMENSIONS TO FULLPAK CASE D 3 ISSUE K A K F Q H B 3 G N L D 3 PL Y U. (.) M B M Y C T SEATING PLANE S J R NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y.M, 9.. CONTROLLING DIMENSION: INCH 3. D- THRU D- OBSOLETE, NEW STANDARD D-3. INCHES MILLIMETERS DIM MIN MAX MIN MAX A.7.3.7. B.39.9 9.9.3 C.77.93..9 D..39.. F..9.9 3. G. BSC. BSC H..3 3. 3.3 J....3 K.3..7 3.73 L...3.7 N. BSC. BSC Q..3 3. 3. R.99.7..9 S.9.3.3.7 U.39.7.. STYLE : PIN. GATE. DRAIN 3. SOURCE 7
NDFNZ PACKAGE DIMENSIONS TO FULLPACK, 3 LEAD CASE AH ISSUE D E/ Q L 3X b e E 3 A P. M B A M D C L 3X b. M B A M C H c A B A NOTE 3 A SEATING PLANE NOTES:. DIMENSIONING AND TOLERANCING PER ASME Y.M, 99.. CONTROLLING DIMENSION: MILLIMETERS. 3. CONTOUR UNCONTROLLED IN THIS AREA.. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH AND GATE PROTRUSIONS. MOLD FLASH AND GATE PROTRUSIONS NOT TO EXCEED.3 PER SIDE. THESE DIMENSIONS ARE TO BE MEASURED AT OUTERMOST EXTREME OF THE PLASTIC BODY.. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. LEAD WIDTH INCLUDING PROTRUSION SHALL NOT EXCEED.. MILLIMETERS DIM MIN MAX A.3.7 A..9 A..7 b.. b.. c.9.79 D.7.3 E 9.7.3 e. BSC H.7 7. L.7.73 L ---. P 3. 3. Q. 3. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 3, Denver, Colorado 7 USA Phone: 33 7 7 or 3 3 Toll Free USA/Canada Fax: 33 7 7 or 3 37 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 9 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 33 79 9 Japan Customer Focus Center Phone: 3 7 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NDFNZ/D