N-channel 30 V, 2.8 mω typ., 80 A STripFET H7 Power MOSFET plus monolithic Schottky in a DPAK package. Features. Description

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Transcription:

N-channel 30 V, 2.8 mω typ., 80 A STripFET H7 Power MOSFET plus monolithic Schottky in a DPAK package Datasheet - production data Features Order code VDS RDS(on) max. ID PTOT STD90NS3LLH7 30 V 3.4 mω 80 A 57 W Very low on-resistance Very low gate charge High avalanche ruggedness Embedded Schottky diode Figure 1: Internal schematic diagram G(1) D(2, TAB) Applications Switching applications Description This device exhibits low on-state resistance and capacitance for improved conduction and switching performance. S(3) NG1D2TS3Sch Table 1: Device summary Order code Marking Package Packing STD90NS3LLH7 90NS3LLH7 DPAK Tape and reel February 2016 DocID025367 Rev 4 1/14 This is information on a product in full production. www.st.com

Contents STD90NS3LLH7 Contents 1 Electrical ratings... 3 2 Electrical characteristics... 4 2.1 Electrical characteristics (curves)... 5 3 Test circuits... 7 4 Package information... 8 4.1 DPAK (TO-252) type A package information... 8 4.2 DPAK (TO-252) packing information... 11 5 Revision history... 13 2/14 DocID025367 Rev 4

Electrical ratings 1 Electrical ratings Table 2: Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage 30 V VGS Gate-source voltage ±20 V ID (1) Drain current (continuous) at TC = 25 C 80 A Drain current (continuous) at TC = 100 C 65 A IDM (1)(2) Drain current (pulsed) 320 A PTOT (1) Total dissipation at TC = 25 C 57 W Tstg Tj Storage temperature -55 to 150 C Operating junction temperature Notes: (1) This value is rated according to Rthj-c and limited by wire bonding (2) Pulse width limited by safe operating area. Table 3: Thermal data Symbol Parameter Value Unit Rthj-pcb (1) Thermal resistance junction-pcb max 50 Rthj-case Thermal resistance junction-case max 2.2 C/W Notes: (1) When mounted on a 1 inch², FR-4 board, 2oz Cu DocID025367 Rev 4 3/14

Electrical characteristics STD90NS3LLH7 2 Electrical characteristics (TC = 25 C unless otherwise specified) Table 4: Static Symbol Parameter Test conditions Min. Typ. Max. Unit V(BR)DSS Drain-source breakdown voltage ID = 1 ma, VGS = 0 V 30 V IDSS Zero gate voltage drain current VGS = 0 V, VDS = 24 V 500 µa IGSS Gate-body leakage current VGS = ±20 V, VDS = 0 V ±100 na VGS(th) Gate threshold voltage VDS = VGS, ID = 1 ma 1.2 V RDS(on) VGS = 10 V, ID = 40 A 2.8 3.4 mω Static drain-source on-resistance VGS = 4.5 V, ID = 40 A 4.1 5.3 mω Table 5: Dynamic Symbol Parameter Test conditions Min. Typ. Max. Unit Ciss Input capacitance - 2110 - Coss Output capacitance VDS = 25 V, f = 1 MHz, VGS = 0 V - 640 - Crss Reverse transfer capacitance - 42 - Qg Total gate charge VDD = 15 V, ID = 80 A, - 13.7 - Qgs Gate-source charge VGS = 4.5 V (see Figure 13: "Test circuit for gate charge - 7.5 - Qgd Gate-drain charge behavior" - 3.3 - Rg Gate input resistance f = 1 MHz, gate DC; Bias = 0, test signal level = 20 mv, ID = 0 A pf nc 0.4 0.7 2 Ω Table 6: Switching times Symbol Parameter Test conditions Min. Typ. Max. Unit td(on) Turn-on delay time VDD = 15 V, ID = 40 A, RG = 4.7 Ω, - 26.4 - VGS = 4.5 V (see Figure 12: "Test tr Rise time - 10.4 - circuit for resistive load switching td(off) Turn-off delay time times" and Figure 17: "Switching - 31.8 - ns tf Fall time time waveform") - 12.5 - Table 7: Source drain diode Symbol Parameter Test conditions Min. Typ. Max. Unit VSD (1) Forward on voltage ISD = 2 A, VGS = 0 V - 0.4 0.7 V trr Qrr IRRM Notes: Reverse recovery time Reverse recovery charge Reverse recovery current (1) Pulsed: pulse duration = 300 µs, duty cycle 1.5% ID = 40 A, di/dt = 100 A/µs, VDD = 20 V (see Figure 14: "Test circuit for inductive load switching and diode recovery times") - 35.2 ns - 26.4 nc - 1.5 A 4/14 DocID025367 Rev 4

2.1 Electrical characteristics (curves) Figure 2: Safe operating area Electrical characteristics Figure 3: Thermal impedance Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance DocID025367 Rev 4 5/14

Electrical characteristics Figure 8: Capacitance variations STD90NS3LLH7 Figure 9: Normalized gate threshold voltage vs temperature Figure 10: Normalized on-resistance vs temperature Figure 11: Normalized V(BR)DSS vs temperature 6/14 DocID025367 Rev 4

Test circuits 3 Test circuits Figure 12: Test circuit for resistive load switching times Figure 13: Test circuit for gate charge behavior Figure 14: Test circuit for inductive load switching and diode recovery times Figure 15: Unclamped inductive load test circuit Figure 16: Unclamped inductive waveform Figure 17: Switching time waveform DocID025367 Rev 4 7/14

Package information STD90NS3LLH7 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 4.1 DPAK (TO-252) type A package information Figure 18: DPAK (TO-252) type A package outline 0068772_A_21 8/14 DocID025367 Rev 4

Package information Table 8: DPAK (TO-252) type A mechanical data mm Dim. Min. Typ. Max. A 2.20 2.40 A1 0.90 1.10 A2 0.03 0.23 b 0.64 0.90 b4 5.20 5.40 c 0.45 0.60 c2 0.48 0.60 D 6.00 6.20 D1 4.95 5.10 5.25 E 6.40 6.60 E1 4.60 4.70 4.80 e 2.16 2.28 2.40 e1 4.40 4.60 H 9.35 10.10 L 1.00 1.50 (L1) 2.60 2.80 3.00 L2 0.65 0.80 0.95 L4 0.60 1.00 R 0.20 V2 0 8 DocID025367 Rev 4 9/14

Package information Figure 19: DPAK (TO-252) recommended footprint (dimensions are in mm) STD90NS3LLH7 FP_0068772_21 10/14 DocID025367 Rev 4

4.2 DPAK (TO-252) packing information Figure 20: DPAK (TO-252) tape outline Package information DocID025367 Rev 4 11/14

Package information Figure 21: DPAK (TO-252) reel outline STD90NS3LLH7 Table 9: DPAK (TO-252) tape and reel mechanical data Tape Reel Dim. mm mm Dim. Min. Max. Min. Max. A0 6.8 7 A 330 B0 10.4 10.6 B 1.5 B1 12.1 C 12.8 13.2 D 1.5 1.6 D 20.2 D1 1.5 G 16.4 18.4 E 1.65 1.85 N 50 F 7.4 7.6 T 22.4 K0 2.55 2.75 P0 3.9 4.1 Base qty. 2500 P1 7.9 8.1 Bulk qty. 2500 P2 1.9 2.1 R 40 T 0.25 0.35 W 15.7 16.3 12/14 DocID025367 Rev 4

Revision history 5 Revision history Table 10: Document revision history Date Revision Changes 17-Apr-2014 1 First release. 07-Sep-2015 2 29-Oct-2015 3 Text and formatting changes throughout document Removed all TO-220 (STP90NS3LLH7) package references and data On cover page: - updated title and Features In section Electrical ratings updated table Absolute maximum ratings In section Electrical characteristics - updated and renamed table Static (was On /off states) - updated tables Dynamic and Source drain diode Added section Electrical characteristics (curves) Updated and renamed section Package information (was Package mechanical data) Updated title and features in cover page. Updated Table 2: "Absolute maximum ratings", Table 5: "Dynamic" and Figure 2: "Safe operating area". Minor text changes. 10-Feb-2016 4 Document status promoted from preliminary to production data. DocID025367 Rev 4 13/14

IMPORTANT NOTICE PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ( ST ) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. 2016 STMicroelectronics All rights reserved 14/14 DocID025367 Rev 4

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