A SOFTWARE RE-CONFIGURABLE ARCHITECTURE FOR 3G AND WIRELESS SYSTEMS

A SOFTWARE RE-CONFIGURABLE ARCHITECTURE FOR 3G AND WIRELESS SYSTEMS E. Sereni 1, G. Baruffa 1, F. Frescura 1, P. Antognoni 2 1 DIEI - University of Perugia, Perugia, ITALY 2 Digilab2000 - Foligno (PG) ITALY Abstract Software radio systems are potentially the next main improvement in mobile and wireless communications. The software radio techniques in handset design are facilitated thanks to technology evolution. The capability of such systems to support re-configuration in response to operator requirements is essential if the true potential of mobile communications has to be perceived. Moreover, customer expectations for new applications can be economically fulfilled by terminal and service reconfiguration. This paper will investigate a way to provide a flexible mobile computing and communication environment, where a user can choose between a WLAN network and a GPRS or a UMTS network, according to his current preference. Recently, a lot of IT industries and customers increased their demand for an always on elaboration system (computer, cellular, and even household appliances connected to a communication network). UMTS is a standard conceived for satisfying such demand with a proper trade-off. The delay that UMTS has accumulated clearly advantages the standards currently present in the market, such as IEEE802.11/b, Bluetooth and GPRS. An integration of these standards into a single terminal is necessary to avoid the multiplication of appliances predestinated to a short market lifetime and to a limited and uncertain success. This paper also concerns some issues about the reconfigurable terminal for these standards and will provide a possible hardware solution that uses the software radio technology. Introduction to software radio The challenge of third generation (3G) mobile communications has considerably pushed the research towards the Software Radio. The presence of various standards for wireless communications and the great difference of services offered by mobile communication providers has led to the planning of a universal connection, that adapts itself to different requirements. The software radio terminals must be auto re-configurable, in order to match the different telecommunication standards [1]. Software Radio (SWR) defines a radio system which has an operating range, bandwidth, level of power, type of modulation, channel coding and so on, all of them configurable by software without changing the hardware. Main rewards of a Software Radio terminal are: The marketing of a single product able to satisfy different customers through a software update. The support to the products can be simplified, and the hardware repair made easier. With the great variety of services that will be offered with 3G, the distribution will assume a remarkable role to interpret customer moods. For the customer, probably, it will be both a benediction and a curse: the strong dependence of the products from the software obliges the user to frequent updates, to always be able to utilize new services available from the provider. An exact definition of the SWR concept doesn't yet exist, even if the need to precisely clarify what is intended for SWR has been claimed from many people. In this framework, an approach has been developed for the implementation of different standards on a reprogrammable platform for the systems, at the baseband. Nevertheless, for the implementation of a complete transceiver, which supports all these standards, there are other parameters that have to be considered: the frequency band and the bandwidth of the radio channel; the management protocols of the different standards; different applications for the users [2]. The ideal scheme of a software radio terminal is shown in figure 1. RF Figure 1 - Ideal Software Radio system DAC DSP The Analog to Digital conversion () is moved as near as possible to the antenna, so to make filtering in digital

processing. SWR arrangement capability to support different standards is mainly due to: The range of frequencies and bandwidth of the RF stage; The greatest bandwidth assigned to a signal; The sampling frequency of the s; The maximum dynamic range; The computational capability of the digital processors (DSP in general). Software Radio Transceiver, in its widest meaning, defines a general TX/RX architecture that can be completely reconfigured, directly operating on an RF digitised information stream. Analog processing is limited at the RF front-end, where a pass-band image-rejection filter selects a large spectrum portion containing the desired services. After a, an converts the signal with the precision required by the system specifications. The digital RF stream is then fed to a RF-BB physical layer DSP subsystem that [3]: Centres the received signal spectrum to the band of services of interest; Lowers the sampling frequency of the digital stream down to the minimum rate required by the standard specifications; Operates the necessary filtering in order to reject the unwanted adjacent signals; Demodulates, channel- and source-decodes the symbol flow and supplies the information bit-stream, for subsequent processing, to higher layers hardware and software. services also provide new business opportunities for service providers and its combination into a comprehensive solution with GPRS and UMTS networks will provide flexibility and portability to the users. The standards currently in the market are GPRS, IEEE802.11/b and Bluetooth. These standards could easily be integrated in a re-configurable terminal. In the next years, third generation standards will also be marketed, providing high data rate access and allowing new and more complex services. These standards are UMTS and IEEE802.11/a. From a digital point of view, the complexity of reconfigurable systems will depend on the possibility to implement an appropriate software library. It is obvious that the reprogramming ability of the hardware platform (i.e. DSP/FPGA) will guarantee the system reconfiguration. It means that all the functional blocks of the different systems can be instantiated simply implementing a suitable software library. Figure 3 shows the different operating frequencies of the above referenced standards. It is clear that a wide spectrum has to be considered. GPRS ~ GPRS UMTS ~ BlueTooth IEEE 802.11\b IEEE 802.11\a 0.8/0.9 1.8/1.9 1.9/2.1 2.4/2.5 5/5.8 Frequency GHz Figure 3 - The range of frequencies. ~ RF Filter RF-BB Physical Layer Processing Figure 2 Architecture of an ideal SDR receiver. Higher Layers However, this architecture is unfeasible for nowadays technology. First of all, the analog RF stage ( and ) should operate in a range varying from hundreds of MHz to tens of GHz. Secondly, the high precision and sampling rate required impose severe constraints on characteristics, still not satisfied by high end devices. Thus, the generally adopted solution is that of a hybrid architecture. 3G and Wireless-LAN scenario. The advantages of the current Wireless scenario include high-rate data transmission and easy network connections, further facilitated by SIM cards. In this framework, WLAN Software Radio Transceiver Architecture In the following we propose a re-configurable platform able to implement the different standards, with currently available technology. In figure 4 it is shown a block diagram of a possible complete transceiver that uses a DSP based hardware for the implementation of the different baseband and IF stage systems. The most significant difference among this transceiver (figure 4) and the ideal transceiver (figure 1) is the RF stage. Nowadays, the technology does not allow having a digital RF stage (Digital Front-End), so the SWR transceiver uses different analog RF stages, one for each considered standard. If a SWR approach is followed, the implementation of the different telecommunication standards can be reduced to the implementation and optimisation of some basic processing blocks.

BB stage Digital IF stage RF stage User/Network Interface Digital BaseBand Rx I Q Controller Clock Clock Generation Selection Digital BaseBand Tx I Q Digital Base- Band Downconversion DAC Digital IF Upconversion Programmable Downconversion Programmable Up-conversion Figure 4 - Re- configurable platform block diagram. Although transmission parameters are different, due to the great variation in terms of useful throughput and bit stream protection, common algorithms are adopted for tasks such as, for example, mapping, channel coding and interleaving. Thus, thinking about a modular design architecture implemented by means of DSP devices, the physical layer of each standard can be segmented into some basic processing units capable to supply the required computational power for that item, in terms, for example, of Million Instruction Per Second (MIPS). Fig. 5 depicts a comparison among the physical layers of IEEE 802.11\a, UMTS, and GPRS, at the transmitter side. An a priori examination permitted to estimate the computational requirements and to split the transmission chain in several pieces, each one implemented by a single DSP unit. Some remarks can be pointed out, for each standard: IEEE 802.11\a: because of the high throughput of this WLAN standard (up to 54 Mbps), a dedicated unit has to realise OFDM modulation (i.e. an IFFT operation) and Viterbi decoding. This is the most computationally demanding standard. Estimated computational complexity for an IEEE 802.11 transceiver is 4500 MIPS [4]. UMTS: according to 3GPP drafts, the spreading requires an ASIC/FPGA device or a very powerful DSP (such as, for example, TMS320C64x), while encoding, interleaving and rate matching are carried out by a less performing DSP. Estimated computational complexity: 3500 MIPS [5]. GPRS: a single DSP unit is sufficient. Similarities with GSM are exploitable to implement it. Estimated computational complexity: 400 MIPS [6].

Higher Layers Interface Convolutional Mapping Puncturing Scrambling Encoder BPSK, QPSK, rate 2/3, 3/4 rate 1/2, K = 7 (16/64)-QAM IEEE 802.11 Convolutional CRC + Rate Segmentation Encoder Segmentation Matching + Multiplexing rate 1/2, 1/3 UMTS Convolutional Encoder Puncturing Block Encoder Precoding and Tail rate 1/2, K = 4 rate 2/3, 3/4 IFFT + Guard Symbol Band Addition Shaping Spreading Amplification Scrambling Block BB - IF Interface GPRS Figure 5 - Splitting of TX algorithms into several basic processing blocks, for the selected standards. Software Radio Hardware Testbed Software Radio architecture requires the development of a number of communication systems at the same time. Thus, it is necessary a powerful hardware platform for a rapid system prototyping [7]. For the referred systems (IEEE 802.11\a, UMTS, GPRS), a PCI hardware testbed has been selected, based on two DSPs and one Forward Error Correction device. This board can provide high computational capability, straightforward utilization and trouble-free modularity. Main hardware features are: Two fixed-point 250 MHz TMS320C6202 DSPs One Reed-Solomon and Viterbi decoder (AHA4210) 1 Mbit,125 MHz, Dual Port SRAM 32 Mbit, 125 MHz, SBSRAM One PCI Bridge (IOP480), with 66 MHz 32-Bit PowerPC RISC CPU Core 128 Mbit external SDRAM PCI Daughter board standard expansion connectors. Figure 6 - Software Radio Hardware Testbed block diagram.

The hardware platform, shown in figure 6, allows the implementation of the referred standards [8]; moreover, it allows to study and to develop even more complex systems, thanks to the following characteristics: Two powerful DSPs and one Viterbi decoder; PCI interface that allows simultaneous use of several of these platforms; PowerPC core inside the PCI Bridge that allows a Real-Time Operating System to run, thus simplifying real time data routing; Expansion capability that allows the integration of air interfaces with properly designed radio modules. For the referred standards, a proprietary software functions library for the respective baseband algorithms is being implemented. This library provides a fast and simple implementation of the modulation and demodulation operations, because it is hardware independent and it is written in a high level language. The performance of the library algorithms gives an exact indication of the computational complexity needed for the Software Radio transceiver implementation. Conclusions In this paper we have described a hardware testbed used for a multistandard software radio architecture implementation. This system will be capable of interfacing with several standards from RF down to baseband, such as GPRS, UMTS and IEEE 802.11. The PCI architecture it is based on will allow an easier integration of existing and future algorithms for mo-demodulation, source and channel coding, IF processing, and so on, by simply programming it with functions selected from an highly versatile software library. Future work will be focused on a thorough testing of this piece of hardware and on the full optimization of the algorithms library. References [1] J. Mitola, "The software radio architecture," IEEE Commun. Mag., vol. 33, no. 5, May 1995. [2] E. Buracchini, The software radio concept, IEEE Commun. Mag., vol. 38, no. 9, September 2000. [3] T. Turletti, H. Bentzen, and D. L. Tennenhouse, "Towards the Software Realization of a GSM Base Station," IEEE JSAC, April 1999. [4] IEEE, IEEE Std 802.11, IEEE Std 802.11-a, IEEE Std 802.11-b, 1997/1999. [5] 3GPP, TS 25.212 V 3.2.0, March 2000. [6] C. Bettstetter, H. Vögel, and J Eberspächer, "GSM Phase 2+ - General Packet Radio Service GPRS: Architecture, Protocols, and Air Interface," IEEE Commun. Surveys, vol. 2, no. 3, 3 rd quart. 1999. [7] V. Bose, M. Ismert, M. Welborn, and J. Guttag, "Virtual Radios," IEEE JSAC, vol. 17, no. 4, April 1999. [8] C. Gnudi, P. Antognoni, S. Cacopardi, F. Frescura, and M. Vagheggini, A Software Radio Development System for Wireless Multimedia Systems, ICSPAT 2000, Dallas, October 2000.