Semiconductor Process Diagnosis and Prognosis for DSfM Department of Electronic Engineering Prof. Sang Jeen Hong Nov. 19, 2014 1/2
Agenda 1. Semiconductor Manufacturing Industry 2. Roles of Semiconductor AEC/APC Technology Sectors 3. 3D-ICs and Wafer Level Packaging (WLP) 4. Call for a Collaboration 2/2
Semiconductor Manufacturing Industry Semiconductor Infra-Structure INFRASTRUCTURE Industry Standards (SIA, SEMI, NIST, etc.) Production Tools Utilities Materials & Chemicals Metrology Tools Analytical Laboratories Technical Workforce Colleges & Universities Chip Manufacturer PRODUCT APPLICATIONS Consumers: Computers Automotive Aerospace Medical other industries Customer Service Original Equipment Manufacturers Printed Circuit Board Industry
Semiconductor Manufacturing Industry Circuit Integration 1.The developmental roots of the semiconductor industry - Triode vacuum tube - Solid state material - Planar transistors Circuit Integration Semiconductor Industry Time Period Number of Compone nts per Chip No integration (discrete components) Prior to 1960 1 Small scale integration (SSI) Early 1960s 2 to 50 Medium scale integration (MSI) 1960s to Early 1970s 50 to 5,000 Large scale integration (LSI) Early 1970s to Late 1970s 5,000 to 100,000 Very large scale integration (VLSI) Late 1970s to Late 1980s 100,000 to 1,000,000 Ultra large scale integration (ULSI) 1990s to present > 1,000,000
Semiconductor Manufacturing Industry Circuit Integration 2. Evolution of wafer size A single integrated circuit, also known as a die, chip, and microchip 2000 1992 1975 1981 1987 1965a 50, 100, 125, 150, 200, 300 mm
Semiconductor Manufacturing Industry Scope and projection 1. Stage of IC fabrication 1. 2. Wafer Preparation includes crystal growing, rounding, slicing and polishing. Wafer Fabrication includes cleaning, layering, patterning, etching and doping. Single crystal silicon Wafers sliced from ingot 4. Assembly and Packaging: The wafer is cut along scribe lines to separate each die. Metal connections are made and the chip is encapsulated. Scribe line A single die Assembly Packaging 3. Test/Sort includes probing, testing and sorting of each die on the wafer. Defective die 5. Final Test ensures IC passes electrical and environmental testing.
Semiconductor Manufacturing Industry Scope and projection 1. Increase in Chip Performance 2. Era of Industry development Critical Dimension (CD) 1950s: Transistor technology Components per Chip 1960s: Process technology Moore s Law 1970s: Competition Power Consumption 1980s: Automation Line Width Space Contact Hole 1990s: Volume production 2000s: Miniaturization 2010s: FDC/APC Year 1988 1997 1999 2001 2002 2005 2007 2009 2011 2014 2017 CD ( m) CD (nm) 1.0 0.25 0.18 0.15 0.13 0.09 0.065 0.045 0.032 0.022 0.016 90 65 45 32 22 16
Semiconductor Manufacturing Industry Scope and projection
Semiconductor Manufacturing Industry Fabrication process flow
Semiconductor Manufacturing Industry Front-end-of-line (FEOL) Wafer Fabrication (front-end) Wafer Start Unpatterned Wafer Thin Films Polish Completed Wafer Diffusion Photo Etch Test/Sort Implant
Semiconductor Manufacturing Industry CMOS Logic Device Passivation layer ILD-6 Bonding pad metal M-4 ILD-5 ILD-4 M-3 ILD-3 M-2 LI metal Via M-1 Poly gate ILD-2 ILD-1 LI oxide n + p + p + STI n + n + n-well p-well p + p - Epitaxial layer p + Silicon substrate
Semiconductor Manufacturing Industry Requirement from a unit process Equipment Parameters: Equipment design Source power Source frequency Pressure Temperature Gas-flow rate Vacuum conditions Process recipe Other Contributing Factors: Cleanroom protocol Operating procedures Maintenance procedures Preventive maintenance schedule Plasma-etching a wafer Plasma-surface interaction : Surface material Material stack of different layers Surface temperature Surface charge Surface topography Chemical and physical requirements Time Quality Measures: Etch rate Selectivity Uniformity Feature profile Critical dimensions Residue
Role of Semiconductor AEC/APC Technology Sectors Chip Manufacturing Sector Fab-wide infrastructures and distributed application frameworks Multi-process, hierarchical control applications using numerous information Framework Sector Integrated engineering analysis, yield management, production data mining Off-line system to diagnose control problems and target their APC investments Fab automation solution including SPC/MES/ERP Equipment Sector Detection, identification and correction of process and equipment faults The economic benefits and ROI in terms of increased yield, less test wafers, less scrap wafers, and enhanced CoO. Controller Sector The control algorithm for low-running devices using production data Standard sensor/tool communication and fast data handling capability Sensor Sector Automated system that monitor the behavior of the APC applications Converting physical properties to process information
Role of Semiconductor AEC/APC Technology Sectors Sensor based-apc Scheme Disturbance to Plasma Probe Type Sensor -> Electron Temperature, Density, EEDF LPF Matcher Gas Chambe r MFC OES -> Monitoring Chemical State PSD -> Ion Saturation current, Probe Bias voltage VI Probe -> Monitoring RF Power Delivery State Difficulty to Install HPF Matcher PU MP Disturbance to Chamber
Role of Semiconductor AEC/APC Technology Sectors Sensor based-apc Process state regulator Process state generation Real Time Monitoring Process Product Processing 1. Notify the operator Real-time Sensor FD Real Time Data Acquisition Diagnostic Sensor OES QMS VI-Probe Ion flux probe SEERS DB 2. Investigate the root cause of the fault from sensory database Requirements 1.No perturbation to plasma Non-invasive and ease of installation 2. High sensitivity 16 bits A/D and 10kHz sampling rate 3. FAB automation friendly Apparatus condition friendly Detecting tool parameter change Things To Do Detecting plasma process change Human computer interface btw. tool and operator Improved FDC/AEC/APC capability
Role of Semiconductor AEC/APC Technology Sectors Sensor based-apc Example Date & Time: 2011/10/14, from 19h 02m 46sec to 22h 49m 21sec Tool: Aluminum reactive sputtering with oxygen augment 19 experimental runs EPD? Or Process Change? Plasma Oscillation? 구간 A 구간 B 구간 C 슬라이드 4 슬라이드 5 슬라이드 6 Trigger: Red > 15000 이상저장 Blue signal 이 Saturation 됨 (Intensity 의조절이필요할것으로판단됨 ) Plasma Oscillation 의 Pattern 이보임
Role of Semiconductor AEC/APC Technology Sectors Equipment based FDC Scheme A B C MFC Miscalibration Fault in Gas Flow Fault in Splitter Total Flow
Role of Semiconductor AEC/APC Technology Sectors Equipment based FDC Scheme
Role of Semiconductor AEC/APC Technology Sectors Equipment based FDC Scheme
3D-ICs and Wafer Level Packaging Technical trend of 3D packaging Samsung s WLP image sensor ( 삼성전기, 2008)
3D-ICs and Wafer Level Packaging Technical trend of 3D packaging 과거의패키징 : 칩을하나하나패키징하는방법 최근의패키징 : 웨이퍼전체를한꺼번에공정하는반도체패키징 기술 웨이퍼레벨패키징 WLP (Wafer Level Packaging) : - 각각의다이를잘라내지않은웨이퍼상태로패키징을진행 - 필요에따라패키징과전기적테스트, Burn-in test 를수행 - 반도체에있어서조립공정이획기적으로개선 Wafer Level Chip Scale Package (WLCSP) Vertical structure -Die: 0.2-0.3 mm -Solder bump: 0.1-0.3mm -Total thickness: 0.4-0.6 mm Source: Samsung What s next? Wafer Level Chip Scale Packaging (WLCSP) with Fan-out. Molding & Bumping 4-mask CSP 1. Polymer coating 2. RDL 3. Polymer coating 4. UBM 5. Ball place 3-mask CSP 1. Polymer coating 2. RDL/UBM 3. Polymer coating 4. Ball place Molding & Bumping 2-mask CSP No polymer coating 1. RDL/UBM 2. Polymer coating 3. Ball place
3D-ICs and Wafer Level Packaging Technical trend of 3D packaging Wafer Level Packaging : All packaging and interconnection must be fabricated on the wafer prior to dicing. - High I/O micro pitches and ASICs: Chips are mounted on chip carriers before surface mount attachment. Not WLP - Diced and packaged high I/O dies with high I/O are directly mounted directly on the final substrate. Not WLP - Small die and/or die with low I/O, after molding, balling, and dicing, can be mounted directly on the final substrate. WLP Wafer level package (Molding Soldering Dicing) Barriers and Challenges Infrastructure is not quite established Wafer bumping is still too costly High cost for poor yield wafers High cost for lower wafer bumping yields Who should manufacture the WLCSP? (IC maker, Bumping house, or Packaging) Die shrink strategy Solder joint reliability Underfill Users of WLCSP Korea - AMKOR, Hynix, Samsung, NEPES Japan - IEP/Oki/Casio/Fujitsu/Shinko - Hitachi (WPP-2; Wafer Process Package) Taiwan - Apack, Unitive Taiwan, ASE, SPIL - Chipbond, Xintec Europe - TU Berlin, IMEC, CS2 USA - National Semiconductor, Atmel, TI - Alpine Micro Systems,
3D-ICs and Wafer Level Packaging Technical trend of 3D packaging
Call for a Collaboration