Customized probe card for on-wafer testing of AlGaN/GaN power transistors R. Venegas 1, K. Armendariz 2, N. Ronchi 1 1 imec, 2 Celadon Systems Inc.
Outline Introduction GaN for power switching applications DC Characterization of GaN power devices CELADON probe cards Setup Measurements Trapping effects in GaN HEMT Pulsed I-V Setup Measurements Conclusions 2
Power switching applications Power switching applications are a common presence in our daily-life. Circuit designers and device manufacturers are constantly challenged to improve the present technology, in particular to achieve: Higher efficiency Smaller dimensions Lower costs PFC, PSU, UPS pv inverter automotive wind turbine 3
R DS-ON Q g [mω * nc] Figure of Merit Devices with better R DS-ON Q g and higher breakdown are needed to improve the circuit performance. 1.E+06 1.E+05 1.E+04 1.E+03 1.E+02 1.E+01 infineon (Si and SJ-Si) IR (Si) Vishay (Si) Fairchild EPC (GaN) (Si) CREE (SiC) Fairchild (Si) microgan (GaN) Transphorm (GaN) GaN-System (GaN) Fujitsu imec (GaN) Silicon has reached its theoretical physical limits. New technologies, such as GaN and SiC, will soon replace Si-based devices in power switching circuit. 1.E+00 1 10 100 1000 10000 Breakdown Voltage [V] 4
GaN-based devices AlGaN/GaN High Electron Mobility Transistors (HEMTs) are attractive for power-switching applications due to their excellent properties: wide energy band-gap (high breakdown) high electron mobility (fast switching speed) good heat conductivity high density electron gas 2DEG (10 13 cm -2 ) Property Units Si GaAs 4-SiC GaN Bandgap ev 1.1 1.42 3.26 3.39 Relative dielectric constant - 11.8 13.1 10 9 Electron mobility cm 2 /Vs 1350 8500 700 1200-2000 Breakdown field 10 6 V/cm 0.3 0.4 3 3.3 Saturation electron velocity - 1 1 2 2.5 Thermal conductivity K 1.5 0.43 3-3-4.5 1.3 5
Depletion mode S AlGaN G D E F E 2DEG GaN 2DEG buffer Intrinsic normally-on operation (depletion-mode): Polarization-induced 2DEG Normally-off operation (enhanced-mode): Fail-safe simpler gate control circuit 6
From d-mode to e-mode S AlGaN p-gan J-FET G p-gan D S Recessed MISFET AlGaN G D 2DEG GaN 2DEG GaN A p-gan layer below the gate lifts-up the band diagram below the gate to realize e-mode operation. The AlGaN layer is recessed below the gate, to locally interrupt the 2DEG to realize e-mode operation. 7
imec Imec s R&D program on GaN devices-on-si is meant to develop a GaN-on-Si process and bring GaN technology towards industrialization. Imec R&D program highlights: High current, high V BD devices E-mode operation 200mm (8 inch) epi-wafers CMOS compatible process Diodes co-integration Gold free ohmic contacts Advanced substrates 8
A new challenge for characterization High switching speed, high power and the electrical behavior of the AlGaN/GaN power transistors call for specific characterization techniques in the power domain. Traditional approaches: Limited current (for DC needles) Poor signal integrity required (for μs pulses) Low reliability at high temperature Short life time New techniques are necessary for onwafer power transistor characterization! 9
Customized probe cards CELADON Element Series 45E CELADON VC20 VersaCore Our solution employs a CELADON VC20 VersaCore with multiple needles mounted on a 45E probe card adaptor. High current measurements Low leakage (for breakdown measurements) less than 5fA s Easy to swap between different probe card cores using Celadon s insertion tool High temperatures (ceramic core) up to 200C 10
Different cores for different layouts The cores are designed to satisfy the device specifications (layout, position of bond-pads, maximum current expected). The large number of needles guarantees: S D lower contact resistance lower inductance higher maximum current S D G S S D G G 11
Internal wiring Coaxial cables are used to contact the instrumentations Signal integrity is guaranteed by bringing the cable shield as close as possible to the needles Two isolated needles are reserved for the SENSE connections of drain and source Input (drain) and output (source) of the current are on distinct cables. 12
DC-measurement setup Keysight B1505A Connector panel Coaxial cables CELADON Element Series 45E CASCADE probe station 13
DC-measurements: I D -V DS Output current of an e-mode power devices Long-pulses (1ms pulse width, duty cycle 100%) Smooth shape of the measured curves I D (A) 18 V 16 GS = 7 V 14 V GS = 6 V 12 10 V GS = 5 V 8 V GS = 4 V 6 4 V GS = 3 V 2 V GS = 2 V 0 0 2 4 6 8 10 V DS (V) V D (A) 12 10 8 6 4 2 0 0-0.5 0.0 0.5 1.0 1.5 2.0 2.5 Time (ms) 12 10 8 6 4 2 I D (A) 14
DC-measurement: leakage I D (A) 1E-5 1E-6 1E-7 1E-8 1E-9 needles probecard 1E-5 1E-6 1E-7 1E-8 1E-9 I GS (A) The probe card does not introduce additional leakage in the measurement 1E-10 1E-10 1E-11 1E-11 0 100 200 300 400 500 V DS (V) 15
I DS [A] Trapping effect in GaN-HEMT GaN technology is not immune to trapping effects. The most detrimental effect of traps for the device behavior is the decrease of the output current (increase of dynamic R DS-ON ). Traps in GaN-HEMT can be at the surface and in the buffer. DC RF OFF-state 16 14 12 10 8 6 4 2 0 0 5 10 15 20 25 100 V DS [V] The effects of a higher R DS-ON in a switching application are: Higher dissipative power on the transistor Higher T j Increased power loss (lower efficiency) Distortion of the V out 16
Virtual gate effect The effect of surface traps is often compared to the presence of a virtual gate in series with the real gate. The complete turn-on of the device is linked to the release of the trapped charge. Vetury, R.; The impact of surface states on the DC and RF characteristics of AlGaN/GaN HFETs ; IEEE Transactions on Electron Devices 2001 17
Avoid trapping in AlGaN/GaN HEMT For a low dynamic R DS-ON dispersion, the following points have to be addressed: Improve the epitaxial layer quality (buffer-dispersion) Decrease the number of trapping states at the surface (passivation/surface cleaning) Decrease the intensity of the electric field peak (field plate) The dynamic R DS-ON must be measured in a reliable way and in a bias condition similar to the device targeted application. 18
Dynamic R DS-ON dispersion Ids [A] Ids [A] The dynamic R DS-ON is measured from the I D -V DS characteristic by means of pulsed measurements (with high drain bias applied during the off-state). V GS V DS t on t off V GS_nq V GS =1V REFERENCE CONDITION (Trap-free) t V GS_q = (V GS_q, V DS_q ) V GS Vds [V] V DS t on t off t V DS_q V DS_nq V GS =1V TRAPPING CONDITION Vds [V] 19
Auriga P-IV system Drain HEAD Gate HEAD AURIGA AU4850 mainframe Short coax cables System monitor 20
Probe card connections For fast switching measurements long current paths and ground loops must be avoided. Source connections are removed No sense terminals are needed The return of the current is through the shield of the drain cable 21
P-IV measurements Output current of a d-mode power devices Short-pulses (10 μs pulse width, duty cycle 10%) Limited amplitude of spikes (mainly due to the d- mode operation) I D (A) 20 18 16 14 12 10 8 6 4 2 V GS_q = 0 V V DS_q = 0 V 0 0 2 4 6 8 10 12 V DS (V) V GS_nq = 1 V V GS_nq = -1 V V GS_nq = -3 V V DS, V GS (V) 20 18 16 14 12 10 8 6 4 2 0-2 V DS V GS 20 18 16 14 12 10 8 6 4 2 0-2 5.0x10-6 1.0x10-5 1.5x10-5 Time (s) I D I D (A) 22
R DS-ON dispersion Dynamic R DS-ON degradation for high V DS_q Limited amplitude of current spikes I D (A) 9 8 7 6 5 4 3 V GS_nq = 1 V (0,0) (-7,50) (-7,100) (-7,150) I D (A) 6 4 2 (0,0) (-7,50) (-7,100) (-7,150) 10 8 2 1 0 0 0 1 2 3 4 5 V DS (V) 5.0x10-6 1.0x10-5 1.5x10-5 Time (s) 23
Conclusions In this presentation we have demonstrated how the CELADON VC20 VersaCore and the 45E probe card holder are successfully used for testing GaN power devices for switching applications. In particular, we have shown: On-wafer high voltage and high current measurements Versatility of the interchangeable cores to match the device layout Smooth shape of the measured waveforms Reliable measurements of fast high-current pulses Limited spikes Easy to use and reproducible measurement setup 24
R. Venegas rvenegas32@gmail.com K. Armendariz karen.armendariz@celadonsystems.com N. Ronchi nicolo.ronchi@imec.be