SanDisk uch2j, TWDS2M, and uch32005 Memory Controllers Process Comparative Analysis For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call Sales at Chipworks. 3685 Richmond Road, Suite 500, Ottawa, ON K2H 5B7, Canada Tel: 613.829.0414 Fax: 613.829.0515 www.chipworks.com
Comparative Analysis Some of the information is this report may be covered by patents, mask and/or copyright protection. This report should not be taken as an inducement to infringe on these rights. 2007 Chipworks Incorporated This report is provided exclusively for the use of the purchasing organization. It can be freely copied and distributed within the purchasing organization, conditional upon the accompanying Chipworks accreditation remaining attached. Distribution of the entire report outside of the purchasing organization is strictly forbidden. The use of portions of the document for the support of the purchasing organization s corporate interest (e.g., licensing or marketing activities) is permitted, as defined by the fair use provisions of the copyright act. Accreditation to Chipworks must be attached to any portion of the reproduced information. CWR-0705-201 11527WSHG Revision 1.0 Published: June 8, 2007
Comparative Analysis 1-1 Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Company Profiles 1.4 Introduction 1.5 Device Summary 1.6 Process Summary 2 Device Overview 2.1 Package and Die 3 Process Analysis 3.1 General Device Structure 3.2 Dielectrics 3.3 Metallization 3.4 Vias and Contacts 3.5 Transistors and Poly 3.6 Substrate, Isolation, and Wells 4 Critical Dimensions 4.1 Package and Die Dimensions 4.2 Dielectric Vertical Dimensions 4.3 Metal Horizontal and Vertical Dimensions 4.4 Contact and Via Dimentions 4.5 Peripheral Transistor Horizontal Dimensions 4.6 Peripheral Transistor Vertical Dimensions 4.7 Die and Well Vertical Dimensions 5 Statement of Measurement Uncertainty and Scope Variation Report Evaluation
Overview 1-1 1 Overview 1.1 List of Figures 2 Device Overview 2.1.1 uch32005 Package (From SD Card) Top View 2.1.2 uch32005 Package (From MP3 Player) Top View 2.1.3 uch2j Package Top View 2.1.4 TWDS2M Package Top View 2.1.5 uch32005 Die Photograph 2.1.6 uch2j Die Photograph 2.1.7 TWDS2M Die Photograph 2.1.8 uch32005 Die Markings 2.1.9 uch2j Die Markings 2.1.10 TWDS2M Die Markings 2.1.11 uch32005 Annotated Die Photograph 2.1.12 uch2j Annotated Die Photograph 2.1.13 TWDS2M Annotated Die Photograph 3 Process Analysis 3.1.1 General View of uch32005 3.1.2 General View of uch2j 3.1.3 General View of TWDS2M 3.2.1 uch32005 ILD Stack 3.2.2 uch2j ILD Stack 3.2.3 TWDS2M ILD Stack 3.2.4 uch32005 ILD 4 3.2.5 uch2j ILD 3 3.2.6 TWDS2M ILD 2 3.2.7 Oxynitride Layer in TWDS2M ILD 1 3.2.8 uch32005 PMD 3.2.9 uch2j PMD 3.2.10 TWDS2M PMD 3.3.1 UcH32005 Metal 6 3.3.2 Uch2J Metal 5 3.3.3 TWDS2M Metal 5 3.3.4 UcH32005 Minimum Pitch Metal 2 3.3.5 uch2j Minimum Pitch Metal 3 3.3.6 TWDS2M Minimum Pitch Metal 4 3.3.7 Barrier Metal of Metal 1 in uch32005 3.3.8 ARC Layer of Metal 4 in uch2j 3.3.9 Barrier Metal of Metal 4 in uch2j 3.3.10 uch32005 Minimum Pitch Metal 1 3.3.11 uch2j Minimum Pitch Metal 1 3.3.12 TWDS2M Minimum Pitch Metal 1 3.4.1 Minimum Pitch Via 2s in uch32005 3.4.2 Minimum Pitch Via 3s in uch2j
Overview 1-2 3.4.3 Minimum Pitch Via 3s in TWDS2M 3.4.4 Contact to Diffusion uch32005 3.4.5 Contacts to Diffusion and Poly uch2j 3.4.6 Contacts to Diffusion TWDS2M 3.5.1 TEM uch32005 SRAM Transistor 3.5.2 TEM uch2j Transistor 3.5.3 TEM TWDS2M Transistor 3.5.4 TEM uch32005 Gate Oxide 3.5.5 TEM uch2j Gate Oxide 3.5.6 TEM TWDS2M Gate Oxide 3.6.1 SCM uch32005 Wells 3.6.2 SCM uch2j Wells 3.6.3 SCM TWDS2M Wells 3.6.4 STI Structure of uch32005 3.6.5 STI Structure of uch2j 3.6.6 STI Structure of TWDS2M 1.2 List of Tables 1 Overview 1.4.1 Device Identification 1.5.1 Device Summary 1.6.1 Process Summary 3 Process Analysis 3.2.1 Observed Dielectric Thicknesses 3.3.1 Observed Metal Dimensions 3.4.1 Observed Via and Contact Dimensions 3.5.1 Observed Transistor and Polycide Horizontal Dimensions 3.5.2 Observed Transistor and Polycide Vertical Dimensions 3.6.1 Die Thickness and Well Depths 4 Critical Dimensions 4.1.1 Die Dimensions 4.2.1 Dielectric Vertical Dimensions 4.3.1 Metal Horizontal and Vertical Dimensions 4.4.1 Contact and Via Dimensions 4.5.1 Peripheral Transistor Horizontal Dimensions 4.6.1 Peripheral Transistor Vertical Dimensions 4.7.1 Die and Well Vertical Dimensions
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