NEW microprocessor technologies demand lower and lower

IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 41, NO. 5, SEPTEMBER/OCTOBER 2005 1307 New Self-Driven Synchronous Rectification System for Converters With a Symmetrically Driven Transformer Arturo Fernández, Member, IEEE, Javier Sebastián, Member, IEEE, Marta María Hernando, Member, IEEE, Pedro José Villegas, Member, IEEE, and Jorge García, Member, IEEE Abstract Synchronous rectification (SR) is mandatory to achieve good efficiencies with low output voltages. If the transformer is driven asymmetrically without dead times, self-driven SR (SDSR) is a very interesting solution. However, if the transformer is driven symmetrically, the synchronous rectifiers are off during the dead times and, as a consequence, the efficiency is lowered. This paper deals with a new SDSR system that keeps the rectifiers on even during the dead times. Thus, it can be used to obtain very low output voltages, such as 1.5 V, with quite good efficiency. Moreover, it can be used over a wide input voltage range. The new system is implemented in a prototype in order to measure the real efficiency that can be achieved with the proposed scheme. Index Terms Low output voltage, power supplies, self-driven synchronous rectification (SDSR). I. INTRODUCTION NEW microprocessor technologies demand lower and lower supply voltages (3.3 V, 1.5 V, 1.2 V, etc.) and, hence, there is an increasing demand of power supplies delivering such low voltages. Obviously, traditional rectification techniques are useless in this type of application because the voltage drop across a Schottky diode is almost half the desired output voltage. Thus, the efficiency would be very much penalized. Synchronous rectification (SR) is then mandatory to achieve good efficiencies in these low output voltage converters [1]. The most widely used topology for this application is nowadays the synchronous buck converter. It is a very simple topology, the dynamic response is very fast, and it has no transformer. However, this last characteristic may also be a drawback in some cases: if the input voltage is high, the duty cycle should be quite narrow and the performance of the converter would not be so good. Moreover, sometimes galvanic isolation is even mandatory. In those cases, topologies with a transformer are needed. Paper IPCSD-05-049, presented at the 2003 IEEE Applied Power Electronics Conference and Exposition, Miami Beach, FL, February 9 13, and approved for publication in the IEEE TRANSACTIONS ONINDUSTRY APPLICATIONS by the Industrial Power Converter Committee of the IEEE Industry Applications Society. Manuscript submitted for review January 24, 2003 and released for publication June 9, 2005. This work was supported by the Comisión Interministerial de Ciencia y Tecnología (CICYT) under Project TIC2003-03491. The authors are with the Grupo de Electrónica Industrial, Universidad de Oviedo, 33204 Gijón, Spain (e-mail: arturo@ate.uniovi.es; sebas@ate.uniovi.es; marta@ate.uniovi.es; pedroj@ate.uniovi.es; jorge@ate. uniovi.es). Digital Object Identifier 10.1109/TIA.2005.853385 At this point, we can talk about two main synchronous rectification methods: self-driven rectification and externally driven rectification. The latter needs a specific circuit to generate the gate pulses and a driver to charge the gate capacitance of the MOSFETs. It should be noted that this capacitance is generally quite large as a very low is required. Thus, quite a lot of energy is required to drive these transistors. On the other hand, the voltage with which they are driven is generally regulated and the input voltage range can be quite large. Moreover, the transformer design is not so critical. The other method is self-driven SR (SDSR). In this case, the energy to drive the MOSFETs is obtained from the transformer and no driver is needed. Thus, it is a very simple and reliable system. Nevertheless, it also has some drawbacks. The voltage with which the transistors are driven is variable and it depends on the input voltage. The design of the transformer is generally quite critical because a very low leakage inductance is required to correctly drive the transistors. Finally, there are not too many topologies suitable for SDSR. The basic concept of SR is the use of a MOSFET as a rectifier instead of a diode. The advantage is that the of new transistors is very low and the voltage drop across it is smaller than the voltage drop across a Schottky diode. Then, the losses are also smaller and the efficiency higher. However, to really achieve this improvement the MOSFETs need to be driven during all their conduction period. In other words, dead times and transition times should be as short as possible. Then, the most suitable topologies for using SDSR are topologies that drive the transformer asymmetrically with no dead times at all: flyback, forward with active clamp, half bridge with complementary control, etc. [2] [6]. Very popular topologies such as the half-bridge converter and the push pull converter are not really suitable because of the dead times in the transformer waveforms. Some solutions have been already presented [7], [8] but they are very dependent on the transformer design because the leakage inductance and the coupling between windings is absolutely critical. This paper presents a new SDSR system that keeps both MOSFETs on even during the dead times, thus making the abovementioned topologies suitable for achieving very low output voltages. Moreover, the system is not so dependent on the transformer design as other methods, although a good coupling between primary and secondary windings is also necessary. With the new method, the input voltage range can 0093-9994/$20.00 2005 IEEE

1308 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 41, NO. 5, SEPTEMBER/OCTOBER 2005 Fig. 1. (a) HBCC converter. (b) Forward with active clamp. (c) Conventional half-bridge converter. be large. A 1.5-V prototype has been tested in order to validate the performance of the new driving system. II. CONVENTIONAL DRIVING SYSTEM Conventional SDSR method just drives the MOSFETs directly with the transformer waveforms. As has been mentioned, topologies with an asymmetrically driven transformer and no dead times are the most suitable for this method (flyback, half bridge with complementary control (HBCC), forward with active clamp, etc.). If a very good dynamic response is needed, the flyback converter is the least likely because of its poor dynamics. A halfbridge converter with complementary control also has an important dynamic problem due to a double pole zero on its transfer function [9]. It should be noted that this problem can be solved by means of a voltage feedforward control technique [10]. However, if the input voltage range is large, the control of the converter becomes quite complicated. Fig. 1(a) shows the main waveforms of an HBCC converter. Forward with active clamp is also likely for this application. Fig. 1(b) shows the main waveforms of this converter and, as can be seen, there are no dead times and the MOSFETs are driven during the whole conduction period. In addition, the dynamics of this converter are very good as they are similar to the buck converter dynamics. If the input voltage range is narrow, another option can also be used. If a conventional half-bridge converter is designed to operate with a large duty cycle, the dead times will be very narrow. Then, the body diodes will only conduct during a short period of time and, hence, the efficiency will not be penalized too much [11]. Moreover, a Schottky diode can be used in parallel with the MOSFET in order to improve the efficiency [Fig. 1(c)]. In all these cases, the coupling between the windings should be very good in order to minimize the voltage ringings at the gate of the synchronous rectifiers. If not, an overvoltage can damage the gate of the MOSFET and, hence, the converter. Another possibility is that the gate voltage goes below the gate threshold voltage and then, the MOSFET will be off and the body diode will start conducting increasing the losses. If the leakage inductance is large, the system will be more underdamped and the gate waveforms will be worse. Then, coupling between windings should be improved as much as possible. If the output voltage is very low, additional windings should be added in order to have a voltage high enough to drive the transistors. In this case, the coupling of these windings should also be as good as possible. Another interesting issue with conventional SDSR is that, in some cases, when the MOSFETs are off, the gate voltage can be negative instead of zero. This means that the energy required to turn it off is higher than if that voltage was zero during the off period. All in all, if the input voltage range is large, a conventional half-bridge, or a push pull converter cannot be used with SDSR. As will now be shown, the newly proposed method overcomes most of these problems. III. NEW DRIVING SYSTEM Half-bridge converters or push pull converters are very popular topologies because of their interesting features. The transformer size is quite small, the dynamics of these converters are very good because they are derived from the buck converter, and the control methods are very well known. There are many commercial pulsewidth-modulation (PWM) circuits and drivers for these topologies and, as they are commonly used, their price is low. In addition, very high efficiencies can be achieved with these topologies when conventional rectification systems are used and the output voltage is not very low. However, as has already been mentioned, SDSR is not easily implemented on these topologies and, hence, they are not generally used to obtain very low output voltages. This paper presents a new method that avoids this drawback, allowing these topologies to be used with low output voltages. The basic idea of the new system is to extend the conduction period of the MOSFETs also to the dead times (Fig. 2). This

FERNÁNDEZ et al.: NEW SELF-DRIVEN SYNCHRONOUS RECTIFICATION SYSTEM FOR CONVERTERS 1309 Fig. 3. (a) Losses on the diode and on the MOSFETs for different rectification systems when the duty cycle is 0.4. (b) Losses when the output current is 25 A and the duty cycle changes from 0.1 to 0.5. Fig. 2. SDSR. Basic idea to improve the efficiency of a half-bridge converter with way, as the transistors are on, their body diode will not conduct during those periods. As a consequence, conduction losses are minimized. Obviously, the body diodes can still conduct during the switching transients. In fact, the advantages of this system are just related to the reduction of the conduction losses. Switching losses are kept more or less the same. The theoretical improvements can be easily calculated assuming that the inductor current has no ripple. In the case of using Schottky diodes, conduction losses on each diode are where is the forward voltage drop on the diode and the output current. If a conventional SDSR system is used, the MOSFET will conduct while there is some voltage across the transformer and the body diode will conduct during the dead times. Hence, losses on the MOSFET will be as follows: with being the forward voltage of the body diode and being the resistance of the MOSFET when the transistor is on. Finally, if the MOSFET conduction is extended during the whole period, the losses on the MOSFET will be (1) (2) (3) Fig. 3(a) shows the theoretical losses of the three systems for different output current values when V, V, m, and. As can be seen, the worst method is the conventional SDSR system because the body diode of the MOSFET has a very large forward voltage drop. As can be seen, the conduction extension system achieves the best behavior. It should be noted that the MOSFET driving losses have been included in the graph of Fig. 3 in order to make a fair comparison. If the output voltage is 1.5 V, the expected efficiency improvement is around 6% in comparison with a Schottky diode rectification system. Furthermore, MOSFET losses depend also on the duty cycle. This is a very important issue when the input voltage range is large because the duty cycle will also have a large variation. Fig. 3(b) shows the theoretical losses for the maximum output current and for different duty cycle values. As can be seen, the worst method is again the conventional SDSR system. Losses are much higher at low duty cycle values because the MOSFET body diode conducts during a longer period of time. Hence, the expected efficiency improvement due to the extension of the conduction time of the MOSFETs is large enough to justify the use of the proposed system. Obviously, the additional circuitry should be as simple as possible in order to not increase the complexity of the system nor the cost. The extension of the conduction time during the dead times on the transformer can be easily achieved if a voltage source is added as seen in Fig. 4(a). Thus, the voltage waveforms at the gate of the MOSFETs will be as shown in Fig. 4(b). As can be seen, while the voltage across the transformer is zero, the gate voltage of the MOSFETS is instead of zero as in the conventional approach. Then, the MOSFET will be always on and the body diode will not conduct. Moreover, the input voltage range can be large because, even if the duty cycle is small, the voltage keeps the transistors on during all the dead time.

1310 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 41, NO. 5, SEPTEMBER/OCTOBER 2005 Fig. 6. Proposed method to obtain the voltage V. Fig. 4. (a) New SDSR system for converters with a symmetrically driven transformer. (b) Main waveforms of the system. Fig. 5. Final scheme of the proposed SDSR system. The voltage source does not deliver any power in steady state and it only operates during a very short period of time. In fact, it only operates during the gate charge and discharge. Moreover, the energy supplied during the gate charge will be recovered during the discharge and, hence, its average value is zero. In the scheme shown in Fig. 4(a), two voltage sources are needed. However, the method can also be implemented using a single voltage source. Fig. 5 shows the proposed circuit in which only one voltage source is used. The implementation of is very simple because a regulated voltage can be obtained from the output filter inductor or from an additional winding of the transformer. Fig. 6 shows a possible implementation of. As can be seen, a flyback-type output is connected to a winding placed on the output filter inductor. The voltage will be controlled by cross-regulation. However, due to the different operating conditions and due to the leakage inductance of the transformer, the output voltage will not be perfectly regulated. Even though some deviation in the voltage is not important, it can be completely regulated by means of a simple linear regulator as shown in Fig. 6. It should be mentioned that this regulator can be a very small one because the average current passing through it is also small. However, a capacitor must be placed at the output in order to supply the peak current due to the charge of the gate capacitor. In fact, the capacitor will be the real power supply for the gate charge and, hence, a good capacitor with a low equivalent series resistance (ESR) should be used. Concerning the transformer design, the auxiliary windings should be very well coupled to the primary and the secondary in order to minimize any ringing at the gate voltage. This is important because an overvoltage at the gate can damage the MOSFET and, on the other hand, if the ringing makes the gate voltage go below the threshold voltage, the MOSFET will be off and the body diode will conduct, thus penalizing the performance of the SDSR system. The coupling of the gate windings is not especially critical. It simply needs the same coupling as any other SDSR winding although it is obvious that, the better the coupling, the better the performance. With this new method, the voltage across the gate during the on time is where is the input voltage and the turns ratio of the auxiliary winding. While there is zero voltage across the transformer, the gate voltage is During the off time, the voltage across the gate is Expressions (4) (6) impose some conditions necessary to design this new driving approach. The maximum gate voltage should be lower than the gate breakdown voltage, generally 20 V. (4) (5) (6)

FERNÁNDEZ et al.: NEW SELF-DRIVEN SYNCHRONOUS RECTIFICATION SYSTEM FOR CONVERTERS 1311 TABLE I INPUT VOLTAGE RANGE AS A FUNCTION OF THE MOSFET THRESHOLD VOLTAGE The minimum gate voltage should be higher than the threshold voltage (between 3 5 V). The voltage during the off period should be lower or equal to zero. Assuming a maximum gate voltage of 20 V and a threshold voltage equal to 5 V, the following expression is obtained from (5) (7): where is the maximum input voltage and the minimum input voltage (both of them are expressed in volts). In addition, the maximum variation of the input voltage can be obtained from these expressions. As can be deduced, the input voltage range depends on the threshold voltage of the MOSFET. Table I shows the input voltage range as a function of the MOSFET threshold voltage. As can be seen, a 3 : 1 range can be easily obtained with the current MOSFET technology. It should be noted that universal input voltage range (85 265 Vrms) converters have more or less this range. IV. EXPERIMENTAL RESULTS Two prototypes have been built in order to test the performance of the new driving system. The main specifications of the prototypes are the following: input voltage 36 72 V; output voltage 1.5 V; maximum output current 25 A; switching frequency 100 khz. Both prototypes have the same specifications. However, the first prototype has been built with a conventional wound transformer in order to check the influence of the transformer leakage inductance. In this case, an ETD 29 core has been used. It is important that the system can also operate with not so tightly coupled transformers in order to allow for wide industrial use. However, as has been mentioned, the better the coupling, the better is the performance achieved. The second prototype has been built with a planar transformer specifically designed for this application. The windings have been integrated in an eight-layer printed circuit board (PCB) and the core used was a planar E22 core. Table II shows some experimental results with some measurements of both transformers. As can be seen, the leakage inductance of the conventional transformer when the secondary is short circuited almost doubles the leakage inductance of the planar transformer. Fig. 7 shows the construction system of both prototypes. Interleaving techniques have been used in both cases. However, the planar one is much more compact. Furthermore, a planar winding on a PCB layer can face the winding of the following layer in a very effective way. Hence, (7) the planar transformer usually has a much better coupling than a conventional one. In our case, the relationship between the magnetizing inductance and the leakage inductance is 400 : 1 for the planar transformer and 220 : 1 for the other one. The effect of the leakage inductance is very important in SDSR systems. Fig. 8(a) shows a very simple equivalent circuit of the driving system. is the leakage inductance reflected on the auxiliary winding, is the input capacitance of the SR, and is a resistor used to damp the voltage waveform. A large inductance gives place to very large oscillations on the voltage waveforms. As far as these waveforms are driving the SR, the MOSFETs can be on or off at unexpected moments as can be seen in Fig. 8(b). Hence, the efficiency will be penalized. The circuit is a conventional second-order circuit and its behavior is very well known (8) (9) (10) (11) As can be seen, the voltage steps always have the same amplitude:. This is very interesting since the circuit always has a constant dc level because of the voltage source. This issue is important because the amplitude of the voltage step and the leakage inductance of the circuit are critical in determining the amplitude of the oscillations. One of the advantages of this method is that, as the voltage step is smaller than in other cases, the amplitude of the oscillations is inherently smaller. It should be noted that a conventional SDSR system would be designed with the same peak gate voltage (e.g., 10 15 V) in order not to damage the gate. Hence, in that case, the voltage step will go from zero to the peak voltage, which is twice the value of the voltage step in the proposed system. Regarding the leakage inductance, a better coupled transformer will always have better performance. However, the dc level allows the use of quite large values of. In fact, the maximum allowable oscillation is as can be seen in Fig. 8(b), being the gate threshold voltage of the MOSFET. The most restrictive transient is the second one (when changes from to ) because, in this case, the first peak is the one that is near. In the first transient, the first peak is not a problem because it resonates above and the peak value is far from the gate breakdown voltage. However, the second transient is really critical because the first peak, which is the higher one, can easily resonate below. Obviously, the resonance depends on and. This second parameter depends directly on the MOSFETs used for SR. Hence, the designer has almost no control of it apart from choosing a transistor with a good tradeoff between and. Finally, the series resistor damps the oscillations. However, a high resistance value may delay the waveforms too much, causing different kinds of problems. In our case, the resistor used was 2.9. Fig. 8(c) shows the gate voltage obtained using the simplified model and the measured leakage

1312 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 41, NO. 5, SEPTEMBER/OCTOBER 2005 TABLE II EXPERIMENTAL MEASUREMENTS ON BOTH TRANSFORMERS AT 100 khz Fig. 7. Construction method of both transformers. The planar one is on the left and the conventional one on the right. Fig. 9. Voltage at the gate of the SR as a function of the input voltage. The main characteristics of the MOSFET used for SR are: m ; V; and nf. As can be seen, 4 V at the gate guarantees the on state of the transistor. However, a 5-V value was selected for in order to have a smaller on resistance. Thus, from (7) (12) As the primary number of turns was ten, could be 2.5 (four turns on the auxiliary winding) or 3.3 (three turns on the auxiliary winding). In our case, was chosen. Thus, the values of the voltage across the gate of the rectifiers as a function of the input voltage are as shown in Fig. 9. As can be seen, the peak voltage at the gate is always kept below 20 V in order to avoid any problem due to a possible overvoltage caused by the leakage inductance of the windings. Regarding the gate drive losses, they depend on the MOSFET input capacitance and on the voltage step value. Although the peak gate voltage is reached after two steps (first to and then to ), the energy used to charge the capacitor depends on the final voltage. As can be seen in Fig. 9, the worse situation occurs at high input voltage Fig. 8. (a) Equivalent circuit of the SR gate driver. b) Gate voltage waveform. (c) Oscillations obtained using the equivalent circuit for different L values. values of both transformers. As can be seen, the oscillation obtained using the conventional transformer goes below and, hence, the body diode may start conducting. The converter will continue operating with no damage at all. However, the losses will be higher. (13) Fig. 10 shows the waveforms of the gate-to-source voltage of the synchronous rectifiers when the conventional transformer is used. As can be seen, the transistors are on even when the transformer has zero voltage. However, although the coupling was not too bad, some oscillations can be seen in the waveforms and in some cases, the MOSFET could be turned off for a few nanoseconds. The amplitude of the ringings is greater when

FERNÁNDEZ et al.: NEW SELF-DRIVEN SYNCHRONOUS RECTIFICATION SYSTEM FOR CONVERTERS 1313 Fig. 10. Waveforms of the voltage at the gate of the SR for different input voltages. (a) V =36V. (b) V =48V. (c) V =72V. Fig. 12. Waveforms of the drain source voltage (upper) and the gate voltage (lower) of the SR for different input voltages obtained with the prototype built with the planar transformer. (a) V =36V. (b) V =48V. (c) V =72V. Fig. 11. Efficiency obtained with the conventional transformer. the input voltage is higher [Fig. 10(c)]. In fact, when the input voltage is 72 V, the gate voltage even becomes negative for a short period of time. This is because more energy is stored on the gate capacitor during turn-off as the voltage is higher. Then, the voltage step at turn-on is higher, and so are the oscillations. Nevertheless, despite the wound transformer, the performance of the converter was quite good. Fig. 11 shows the efficiency achieved and, as can be seen, it is always higher than 82% at nominal conditions. Moreover, a maximum efficiency of 88% has also been obtained at a lower input voltage (36 V). As has been mentioned, the overall efficiency can be improved with a better transformer coupling. For that purpose, a planar transformer has been built in order to improve the performance of the driving system. Fig. 12 shows the gate voltage of the SDSR MOSFETs as well as the drain-to-source voltage of the primary MOSFETs for different input voltages (36, 48, and 72 V). As can be seen, the ringings are much smaller than in the previous case. In fact, the MOSFETs are always kept on because the gate voltage is never lower than the threshold voltage. In general, the efficiency of the second prototype is between 2% 3% higher than the efficiency of the first prototype. Fig. 13 shows the efficiency of the prototype when the planar transformer is used. As can be seen, the efficiency at nominal conditions (48 V) is higher than 80% and, in some cases, reaches 84%. The efficiency is higher for lower input voltages. This prototype has an 89% efficiency when the input voltage is 36 V and the output current is around 10 A. On the other hand, the efficiency decreases when the input voltage is higher. This is due to two main reasons: at high input voltages, the duty cycle is lower and, hence, the gate voltage is during a longer period

1314 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 41, NO. 5, SEPTEMBER/OCTOBER 2005 Fig. 13. Efficiency of the prototype built with the planar transformer. Fig. 15. core. Planar transformer built with an eight-layer PCB and an E22 planar Fig. 14. Efficiency comparison between three different systems: Schottky diodes, conventional SDSR, and proposed SDSR systems when the input voltage is 36 V. of time. Although the MOSFET is on, the losses would be lower if the gate voltage was higher. Moreover, the negative turn-off voltage is higher and, hence, more energy is needed to drive the transistors. In our case, the converter was designed to operate over a large input voltage range. Although this is a very interesting feature, the efficiency cannot be optimized for the whole range of operating conditions because the duty cycle variation is wide. Thus, if the input voltage range was narrower, the efficiency could be optimized at the nominal operating conditions. In order to see the real improvements achieved by this SDSR method, the system was also removed and the efficiency was tested both with Schottky diodes and with MOSFETs driven by the conventional SDSR system (the body diodes conduct during the dead times). Fig. 14 shows the efficiency measured when the input voltage was 36 V. As can be seen, the best efficiency is achieved with the proposed system. In fact, at maximum output current (25 A) the efficiency is around six points higher than in the case of using Schottky diodes. As was already mentioned, the worst case occurs when the conventional SDSR is used. Finally, Fig. 15 shows the planar transformer built with an eight-layer PCB and an E22 planar core. The structure of the internal layers is as shown in Fig. 7. V. CONCLUSION The conventional SDSR approach is generally used in converters that drive the transformer asymmetrically with no dead times. However, if the transformer voltage waveform has dead times, this system does not perform well. Therefore, popular converters such as the half bridge or the push pull that drive the transformer symmetrically (and, hence, have dead times) cannot be used with this system. This paper has presented a new and very simple driving method that keeps the synchronous rectifiers on during the dead times. Thus, very low voltages can be achieved with high efficiencies. The prototype designed achieved more than 82% efficiency at nominal conditions for a 1.5-V output voltage. Moreover, the dynamic performance of these converters is very good because they are based on the buck converter and, hence, they can even be used in applications with high output current slew rates. The proposed system is not too dependent on the transformer parasitics, although a proper transformer design with low leakage inductance will achieve better performance. In our case, the prototype using a planar transformer had an efficiency around 2% higher than the prototype using a conventional transformer. In addition, the system can operate over a quite large input voltage range, allowing its use in a large number of applications. However, if the input voltage range is large, the efficiency is not easily optimized for the whole operating range. In general, the wider the duty cycle, the higher the efficiency. REFERENCES [1] C. Blake, D. Kinzer, and P. Wood, Synchronous rectifiers versus Schottky diodes: a comparison of the losses of a Schottky diode rectifier, in Proc. IEEE APEC 94, vol. I, 1994, pp. 17 23.

FERNÁNDEZ et al.: NEW SELF-DRIVEN SYNCHRONOUS RECTIFICATION SYSTEM FOR CONVERTERS 1315 [2] W. A. Tabisz, F. C. Lee, and D. Y. Chen, A MOSFET resonant synchronous rectifier for high-frequency DC/DC converters, in Proc. IEEE PESC 90, 1990, pp. 769 779. [3] N. Murakami, H. Namiki, and K. Sakakibara, A simple and efficient synchronous rectifier for forward DC/DC converters, in Proc. IEEE APEC 93, 1993, pp. 463 468. [4] J. A. Cobos, O. García, J. Sebastián, and J. Uceda, Active clamp PWM forward converter with self-driven synchronous rectification, in Proc. IEEE INTELEC 93, vol. 2, 1993, pp. 200 206. [5] M. M. Jovanovic, J. C. Lin, C. Zhou, M. Zhang, and F. C. Lee, Design considerations for forward converter with synchronous rectifiers, in Proc. VPEC Seminar, 1993, pp. 340 359. [6] J. A. Cobos, O. García, J. Uceda, and F. Aldana, Optimized synchronous rectification stage for low output voltage (3.3 V) DC/DC conversion, in Proc. IEEE PESC 94, vol. 2, 1994, pp. 902 908. [7] P. Alou, J. A. Cobos, J. Uceda, M. Rascón, and E. de la Cruz, Design of a low output voltage DC/DC converter for telecom application with a new scheme for self driven synchronous rectification, in Proc. IEEE APEC 99, 1999, pp. 866 872. [8] P. Alou, J. A. Cobos, O. García, R. Prieto, and J. Uceda, A new driving scheme for synchronous rectifiers: single winding self-driven synchronous rectification, IEEE Trans. Power Electron., vol. 16, no. 6, pp. 803 811, Nov. 2001. [9] F. F. Linera, J. Sebastián, M. A. Pérez, J. Díaz, and A. Fontán, Closing the feedback loop in the half-bridge complementary-control DC-to-DC converter, in Proc. IEEE APEC 97, 1997, pp. 977 982. [10] F. F. Linera, J. Sebastián, J. Díaz, and F. Nuño, A novel feedforward loop implementation for the half-bridge complementary-control converter, in Proc. IEEE APEC 98, vol. 1, 1998, pp. 363 368. [11] A. Ferreres, J. Cardesin, P. Villegas, A. Fernández, and M. M. Hernando, Universal input voltage AC/DC converter with low output voltage and compliance with IEC 1000-3-2, in Proc. IEEE PESC 01, vol. 2, 2001, pp. 678 682. Javier Sebastián (M 86) was born in Madrid, Spain, in 1958. He received the M.Sc. degree from the Polytechnic University of Madrid, Madrid, Spain, in 1981, and the Ph.D. degree from the University of Oviedo, Gijón, Spain, in 1985. He was an Assistant Professor and an Associate Professor at both the Polytechnic University of Madrid and the University of Oviedo. Since 1992, he has been with the University of Oviedo, where he is currently a Professor. His research interests are switching-mode power supplies, modeling of dc-to-dc converters, low-output-voltage dc-to-dc converters and high-power-factor rectifiers. Marta María Hernando (M 95) was born in Gijón, Spain, in 1964. She received M.Sc. and Ph.D. degrees in electrical engineering from the University of Oviedo, Gijón, Spain, in 1988 and 1992, respectively. She is currently an Associate Professor at the University of Oviedo. Her main interests are switching-mode power supplies and high-power-factor rectifiers. Pedro José Villegas (M 96) was born in Suances, Spain, in 1965. He received the M.Sc. degree and the Ph.D. degree in electrical engineering from the University of Oviedo, Gijón, Spain, in 1991 and 2000, respectively. Since 1994, he has been an Assistant Professor at the University of Oviedo. His research interests are switching-mode power supplies, converter modeling, and high-power-factor rectifiers. Arturo Fernández (M 98) was born in Oviedo, Spain, in 1972. He received the M.Sc. degree and the Ph.D. degree in electrical engineering from the University of Oviedo, Gijón, Spain, in 1997 and 2000, respectively. In 1998, he became an Assistant Professor at the University of Oviedo, where, since 2003, he has been an Associate Professor. He has been involved in about 20 power electronics research and development projects since 1997, and he has authored over 60 published technical papers. His research interests are switching-mode power supplies, low output voltage, converter modeling, and high-power-factor rectifiers. Jorge García (S 01 M 04) was born in Madrid, Spain, in 1975. He received the M.Sc. and Ph. D. degrees in electrical engineering from the University of Oviedo, Gijón, Spain, in 2000 and 2003, respectively. In December 1999, he joined the Electrical and Electronic Engineering Department, University of Oviedo. He is currently a Researcher working on the development of electronic systems for lighting and electronic switching power supplies. Since 2002, he is also an Assistant Professor of Electronics. His research interests include dc/dc converters and PFC stages, switching power supplies, HF inverters for discharge lamps, and electronic starters for HID lamps.