Proceedings of Interntionl Joint Conference on Neurl Networks, Orlndo, Florid, USA, August 12-17, 2007 A Self-tuning for Rel-time Voltge Regultion Weiming Li, Xio-Hu Yu Abstrct In this reserch, self-tuning controller bsed on multi-lyer feed-forwrd neurl network is developed for reltime output voltge regultion of clss of DC power supplies. The neurl network bsed controller hs the dvntge of dptive lerning bility, nd cn work under the situtions when the input voltge nd lod current fluctute. Levenberg- Mrqurdt bck-propgtion trining lgorithm is used in computer simultion. The neurl network controller is implemented nd tested on hrdwre using DSP (digitl signl processor). Experimentl results show tht this neurl network bsed pproch outperforms the conventionl nlog controller, in terms of both line regultion nd lod regultion. I. INTRODUCTION OWADAYS DC-DC converters cn be found in lmost Nevery electronic device, since ll the semiconductor components re powered by DC source. PWM (pulse-width modultion) technique is used in mny voltge regultors. It chnges the verge vlue (i.e., dc component) of squre wveform by modulting its duty cycle. One of the design objectives for electronic engineers is to improve the efficiency of power conversion. In PWM converters, switching network is employed for squre wveform modultion. Idelly, the power dissipted by the switch network is zero; however in prctice, the power efficiency of typicl DC-DC converter could be s low s 70%. Mny different kinds of topologies ([1], [2], [3]) hve been investigted in the pst to reduce the switching loss. Unfortuntely, those topologies either need dditionl components for the power circuit, which my introduce some unstble fctors to the circuit; or operte t vrible frequency, which mkes the filter design t output stge very difficult. Phse-shifted zero-voltge switching full-bridge converters overcome the bove problems nd thus hve been received more nd more ttention recently. It employs zerovoltge-switching (ZVS) technique which llows the voltges cross the trnsistors to swing to zero just before the strt of the next conduction cycle ([4], [5], [6]). The conventionl pproch ssumes tht the circuit is operted round its equilibrium stte, nd then derives set This work ws supported in prt by the Deprtment of the Nvy, Office of Nvl Reserch, under Awrd # N00014-05-1-0855. Weiming Li ws with the Deprtment of Electricl Engineering, Cliforni Polytechnic Stte University, Sn Luis Obispo, USA. He is now with St. Jude Medicl, Sylmr, CA, USA. Xio-Hu Yu is with the Deprtment of Electricl Engineering, Cliforni Polytechnic Stte University, Sn Luis Obispo, CA 93407, USA (e-mil: xhyu@ee.clpoly.edu). of liner equtions bsed on this ssumption [9] [10]. However, in prctice, the supply voltge nd lod current my hve wide rnge of vrition; so the controller hs to be designed to work under such conditions. Artificil neurl networks (ANN) hve been widely used in the field of system identifiction, dptive control, nd sttistic modeling in recent yers. A neurl network is composed of mny non-liner dptive processing elements nd is cpble of pproximting ny mesurble function under certin conditions. Recently, rtificil neurl network bsed controller hs been chosen s n lterntive to clssic methods ([7], [8]) to improve the performnce of DC power supply to dynmicl system chnges, due to the dptive lerning bility of the neurl network controller. However, no prior work hs been done to control PSFB (Phse-Shifted Full-Bridge) converter using the neurl network pproch yet. In this reserch, n pproch bsed on multi-lyer feed-forwrd neurl network controller is investigted. A Mtlb Simulink model is developed first to generte the dt set; then the neurl network is trined by Levenberg-Mrqurdt bck-propgtion lgorithm. Finlly, the neurl controller is implemented on DSP evlution bord ezdsp F2812 (with digitl processor TMS320F2812) nd phse-shifted zero-voltge-switching circuit bord UCC3895EVM. Stisfctory experimentl results with the neurl network controller re obtined nd compred with the conventionl nlog controller, in terms of both line regultion nd lod regultion. Vdc G3 G2 Q3 Q2 D3 D2 II. MODELING AND SIMULATION C3 C2 C1 C4 D1 D4 G1 G4 Q1 Q4 Lr 1 2 Lp TX1 Fig 1. PSFB DC-DC Converter Ls1 Ls2 D11 D12 1 2 The circuit digrm of PSFB (Phse-Shifted Full- Bridge) DC-DC converter is shown in Fig. 1. Bsed on circuit nlysis, the control scheme to drive the switching MOSFET (Q1, Q2, Q3 nd Q4) is very complicted [6]. The circuit is operted in one of the following modes: 2 1 1-4244-1380-X/07/$25.00 2007 IEEE
Mode 1: The digonl MOSFET Q3 & Q4 re conducting nd power is delivered through the trnsformer to the lod. The primry lod current is flowing through the lekge inductnce of the trnsformer. The totl primry current is equl to the lod current plus incresing mgnetizing current of the trnsformer. Mode 2: With Q4 on, the cpcitnce cross Q1 is chrged to +V. When Q4 turns OFF the current through the trnsformer inductnce strts to chrge the drin source cpcitnce of Q4, while t the sme time dischrges the cpcitnce of Q1. This ction continues until the body diode of Q1 turns ON to clmp the voltge cross Q1 t pproximtely 0.7V. The current through the trnsformer is sustined in the upper hlf of the power circuit. Mode 3: When the voltge cross Q1 reches pproximtely 0V, Q1 turns ON. The time tht is required for the cpcitnce of Q4 nd Q1 to rech the desired voltge is determined by the chrcteristics of hrdwre. The current in this mode circultes through the conduction chnnels of Q3 nd Q1. Mode 4: Q3 turns off. The trnsformer current now strts to chrge nd dischrge the cpcitnce of Q3 nd Q2 respectively. It gin requires finite mount of time for the drin voltge of Q2 to rech "0 volt" t which point Q2 is llowed to be switched on. Tht mens non-dissipte turn ON switching is ccomplished. Mode 5: With the complete dischrge of its drin source cpcitnce Q2 is now redy to turn ON. Power is delivered to the lod through the conduction pth of Q1 nd Q2 for n mount of time tht is determined by the control circuit. Twice the product of this time, times the operting frequency of the oscilltor gives the duty cycle of the converter s in regulr PWM converter; i.e., duty cycle D = 2 T on F s. Mode 6: Following the power trnsfer by the bove digonl pir, Q1 turns OFF. The voltge cross Q4 strts to decrese, nd when this voltge reches 0 volts the next mode strts. Mode 7: In this mode, Q4 turns on nd primry current circultes in the conduction chnnels of the lower pir. switching period constnt, nd Φ is the duty cycle. T 1 nd T 2 cn be obtined from the following equtions [11]: ( ni + I c )L r T1 = (2) V in V ( C Q3 + C Q4 ) T 2 = in (3) ni where I is the lod current; C Q3 nd C Q4 re the cpcitnce of the two intrinsic cpcitors of Q3 nd Q4, respectively; L r is the resonnt inductnce. I c cn be clculted s follows: I c = V in ( C Q1 + C Q2 )( J 2 1) L r where ni L J = r (5) Vin ( C Q1 + C Q2 ) The controller determines the duty cycle bsed on the input voltge nd lod current to chieve the desired output voltge. As shown in the bove equtions, the control lw is highly nonliner nd s the result, it leds to very complicted design for conventionl pproch. Bsed on the bove the nlysis, the Simulink model for trining the neurl network controller is developed. It is well-known tht rtificil neurl networks cn pproximte ny nonliner function to the desired ccurcy, fter it is fully trined. A feedforwrd neurl network with six neurons in the hidden lyer nd one neuron in the output lyer is employed. The ctivtion function for ech neuron is: 1 f ( x ) = (6) x 1+ e The weights of the neurl network re initilized t rndom, nd then updted by bck-propgtion lgorithm. To speed up the trining, Levenberg-Mrqurdt lgorithm is employed: W( k +1) = W( k ) + W (7) Mode 8: Q2 turns OFF nd current strts to chrge nd dischrge the cpcitnce of Q2 nd Q3 respectively. When where T the voltge cross Q3 hs reched 0 volts then Q3 turns ON 1 T W = ( J J + µi ) J e (8) non-dissiptive nd the complete cycle repets itself from Mode 1. where J is the first order derivtive of the error function respect to the neurl network weight (lso clled the The reltionship between the input/output voltge nd the Jcobin mtrix), e is the output error (i.e., the difference duty cycle cn be described s: between the neurl network output nd the desired output), 2nV T T µ is lerning prmeter, nd k is the number of itertions. V 0 = T (1) in s 2 Φ 1 T s 2 2 The computer simultion results re shown in the where V is the output voltge, V is the input voltge, following figures. Fig. 2 shows the trining error is reduced 0 in to the desired ccurcy fter bout 100 itertions (the both in RMS vlue; n is the trnsformer rtio, T is the percentge of RMS error is bout 0.01%). Fig. 3 s demonstrtes the duty cycle estimtion of the neurl network (4)
nd the desired vlue, where plnt is the desired vlue of duty cycle while network is the output of the neurl network. It is shown tht once the neurl network is trined, it is ble to chnge the duty cycle bsed on the chnge of the output voltge. Fig. 4. The System Block Digrm Fig 2. Neurl Network Trining Error Fig. 3. Duty Cycle Estimtion III. EXPERIMENTAL RESULTS The overll system block digrm is shown in Fig. 4. The inputs to the neurl network include input voltge, lod current, nd the chnge of output voltge. The control objective is to keep the output voltge stble (t the nominl vlue of 3.3V in this cse) under the conditions of different input voltges nd lod currents. In order to investigte the performnce of the neurl network controller from experimentl dt, DSP (Digitl Signl Processor) evlution module ezdsp F2812 nd phse-shifted zero-voltge-switching evlution bord UCC3895EVM re used to implement the neurl controller nd the power circuit, respectively. The on-bord digitl signl processor TMS320F2812 is 32-bit CPU with 150 MIPS (million instructions per second) operting speed. The phse-shifted full-bridge converter is operted on 48V (nominl input) nd it provides n output of 3.3V. The neurl controller is developed in C lnguge. In Fig. 4, the PWM genertor nd the power circuit blocks re implemented on bord UCC3895EVM nd the rest of the blocks (i.e., the neurl network controller nd the switching dely clcultion module) re implemented with DSP TMS320F2812. First, the nlog signls from the power circuit re digitized nd processed before being fed into the neurl network s inputs. Since the power circuit is driven by 400 khz high frequency PWM signls, the rw output voltge signl is quite noisy during the switch turn-on nd turn-off time. To solve this problem, multiple smples re tken to obtin the verge vlue over certin period of time. Next, the processed dt is fed into the neurl network to estimte the desired duty cycle. The new estimted duty cycle is then pplied to the power circuit, nd the output voltge is monitored. The computtionl flow chrt is shown in Fig. 5. At nominl input voltge 48V, the converter s output voltge in stedy-stte is mesured under different lod conditions nd the result is shown in Figure 6, where the curve on top is the output controlled by neurl network controller nd the other one is the output controlled by conventionl nlog controller (UCC3895). The desired nominl output voltge is 3.3V by design. As shown in the plot, the mximum output (by the neurl network controller) is 3.38V, which results in only 2.4% error rte. The overll neurl network controller outperforms the conventionl nlog controller.
mesure, the percentge of line regultion between 48V nd 72V input voltge (i.e., Line_Reg ) is clculted using the following formul: V 0( hi _ in ) V0( lo _ in ) Line _ Re g = 100% (10) V 0( no min l ) where V 0( hi _in ) is the output voltge under the highest input voltge which cn be llowed (72V in this cse), nd V 0( lo _in ) is the output voltge with the lowest input voltge (48V in this cse). The neurl controller chieves better line regultion (0.9%) thn the nlog controller (3.9%). Fig. 5. The Flow Chrt 3.25 The percentge of lod regultion gives us n indiction of how much the output voltge chnges over rnge of lod 3.2 resistnce vlues. In constnt voltge mode, vritions in the lod result in chnges in the lod current. Here, we define the percentge of lod regultion between 0% nd 100% of the full lod s: V V 0 ( no lod ) 0( full lod ) Lod _ Re g = 100% (9) V 0 ( no min l ) where Lod_Reg represents the percentge of line regultion, V 0( no lod ) represents the output voltge when the lod current is 0, nd V 0( full lod ) represents the output voltge when full lod is presented, nd V 0( no minl ) represents the idel (nominl) output voltge. Experimentl results show tht the percentge of lod regultion is only bout 2.1%, which concludes tht the neurl controller provides excellent lod regultion (compring to the lod regultion of 4.5% using the conventionl controller). Ouput Voltge (V) 3.4 3.35 3.3 48 58 68 Input Voltge (V) Fig. 7. Line Regultion t Full Lod 15A IV. CONCLUSION Neurl A nlog A neurl controller s n lterntive to clssic controller for PSFB DC-DC converter is proposed in this pper. Both simultion nd experimentl results show tht the neurl network controller is ble to estimte the desired duty cycle under severl dynmic conditions. In terms of both line regultion nd lod regultion, the neurl network bsed pproch outperforms the conventionl nlog controller. More reserch works will be done to optimize the softwre to speed up the neurl controller for rel-time pplictions. Output Voltge (V) 3.40 3.35 3.30 3.25 3.20 3.15 0 5 10 Lod Current (A) 15 Neurl Anlog Fig. 6. Lod Regultion t 48V Nominl Input Voltge At full lod condition, the converter s output voltge is mesured t different input voltges, nd the result is shown in Fig. 7. The mximum output error is only 0.04V, which is less thn 2% of the nominl vlue. Another performnce ACKNOWLEDGEMENT The uthors would like to thnk Dr. Tufik for providing the hrdwre. REFERENCES [1] P. R. Chetty, Resonnt power supplies: Their history nd sttus, IEEE Aerosp. Electron. Syst. Mg., vol. 7, no. 4, pp. 23 29, Apr. 1992. [2] M. G. Kim nd M. J. Youn, An energy feedbck control of series resonnt converters, IEEE Trns. Power Electron., vol. 6, no. 4, pp. 338 345, Jul. 1991. [3] J. M. Crrsco, E. Glván, G. E. Vlderrm, R. Orteg, nd A. Stnkovic, Anlysis nd experimenttion of nonliner dptive controllers for the series resonnt converter, IEEE Trns. Power Electron., vol. 15, no. 3, pp. 536 544, My 2000. [4] H.-S. Choi nd B. H. Cho, Novel zero-current-switching (ZCS) PWM switch cell minimizing dditionl conduction loss, IEEE Trns. On Industril Electronics, Vol. 49, No. 1, P. 165-172, Februry 2002.
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