A 2.4 3.6-GHz Wideband Sub-harmonically Injection- Locked PLL with Adaptive Injection Timing Alignment Technique Abstract: This paper proposes a wideband sub harmonically injection-locked PLL (SILPLL) with adaptive injection timing alignment technique. The SILPLL includes three main circuit blocks: oneoscillator-period constant-delay (OOPCD) divider, timing-adjusted phase detector (TPD), and pulse generator (PG). The proposed injection timing alignment technique can align the injection timing adaptively in a wide range of the output clock frequency using the two blocks (OOPCD and TPD) and a falling edge locking scheme of pulses. It can avoid the risk that SILPLL may lock to the wrong frequency or even fail to lock. The PG block is used for half-integral injection to relax the tradeoff between the phase noise of SILPLL and the output frequency resolution. The OOPCD circuit occupies a negligible area. After the injection timing alignment is finished, the OOPCD is powered off so that no extra power is consumed. The SILPLL is implemented in the 65-nm 1P9M CMOS process. It consumes 8.6 mw at 1.2 V supply and occupies an active core area of 1 0.6mm2. The measured output frequency range is 2.4 3.6 GHz with an output frequency resolution of 200 MHz and the phase noise is 127.6 dbc/hz at an offset of 1 MHz from a carrier frequency of 3.4 GHz. The rms jitter integrated from 1 khz to 30 MHz is less than 112 fs for all the covered frequency points. Under the supply voltage range from 1.1 to 1.3 V and the temperature range from 20 C to 70 C, the rms jitter variation of all the covered frequency points is less than 27 fs, which shows good robustness over environmental variation. The proposed architecture of this paper analysis the logic size, area and power consumption using Tanner tool. Existing System: The integer-n PLLs are widely used for clock generation due to its simplicity. To decrease clock jitter, it is necessary to lower the in-band phase noise by increasing the charge pump (CP) current in the analog PLL or by adopting a high resolution time-to-digital converter in the all-digital PLL(ADPLL). In addition, low-phase-noise oscillators are needed to achieve the low out-band phase noise. As a result, the power consumption or the design complexity may be increased
much. Although the bang-bang phase detector (BBPD)-based ADPLL can achieve low in-band noise and thus low jitter with a simplified architecture and low power consumption due to the high gain of BBPD, it is difficult to control the loop band width to get the optimum jitter performance, because the gain of BBPD varies much with the reference jitter. An alternate way to implement ultralow jitter clock generation circuits is to adopt the injectionlocked frequency multiplier (ILFM). The phase noise of ILFM can be suppressed considerably by injecting a clean low frequency pulse into the voltage controlled oscillator (VCO) to reduce both the in-band phase noise and the out-band phase noise. Thus, the clock generation circuits with a low jitter of sub-200 fsrm scan be realized by the ILFM with reasonable power. However, ILFM has one critical issue of narrow locking range. If the difference between the frequency of the free running oscillator and the target frequency is not sufficiently small, the phase noise and reference spur will get worse. In the worst case, the ILFM even fails to lock if the target frequency is not in the locking range of the oscillator. To solve such a problem, there are mainly two kinds of approaches. One kind is the open-loop calibrationbased ILFM (OLC-ILFM) and the other kind is the sub harmonically injection-locked PLL (SILPILL).In OLC-ILFM, there is a problem that the in band phase noise contributed by the flicker noise of oscillator cannot be suppressed well due to the elimination of the PLL. Although the technique presented can solve such a problem, it is not PVT tolerable because the free running frequency of the oscillator must be manually adjusted. The ILFM uses digital continuous frequency tracking loop to track the central frequency of the oscillator, it suffers from reduced lock-in range due to the gated injection scheme, and thus the phase noise of the oscillator may not be suppressed well. In the SILPLLs, the free running frequency of oscillator can be tracked simultaneously by the PLL and thus the in-band phase noise contributed by the flicker noise of oscillator can be suppressed. However, the injection timing of the clean low frequency pulse must be controlled carefully, otherwise large spur will be induced or even the SILPLLs fail to lock. In addition, the injection timing should be readjusted if the output frequency is changed, which makes the SILPLL difficult to generate wideband clock. To solve these problems, several methods were presented as illustrated below. In the first approach, the injection timing is adjusted manually by the digital-control delay line (DCDL) or the voltage control delay line. The main drawback of this approach is the poor PVT tolerance. Moreover, it is not suitable for wideband clock generation because the injection timing
must be readjusted manually. The second approach adoptsa digital calibration method to control the DCDL to injection timing automatically. However, these two approaches also do not tolerate PVT well because such approaches adopteda foreground calibration method. The third approach adopts the self-aligned injection timing method with the help of the timing-adjusted phase detector (TPD), which has good PVT tolerance. However, the narrow capture range of TPD may lead to lose lock when changing the output frequency and so it does not support the wideband clock generation. The fourth approach adopts the dual-loop calibration method to calibrate the frequency of the main oscillator by the frequency locked loop and a replica oscillator. Compared with the other three approaches above, this approach is both PVT tolerable and suitable to wideband clock generation. However, because there are two VCOs in PLL, it is nota good choice for the LC-VCO-based SILPLL due to the large area of two LC-VCOs. The last approach continuously adjusts the injection timing by means of one delay-locked loop (DLL) with good PVT tolerance, and can also be used for wide band clock generation. However, the highfrequency DLL is much power consuming and the delay time induced by the divider in the SILPLL worsens the reference spur level(only 28 db) Disadvantages: Worst performance Proposed System: We propose a wideband SILPLL with adaptive injection timing alignment technique. The proposed adaptive injection timing alignment technique uses a one-oscillator period constantdelay (OOPCD) divider and a falling edge locking scheme of pulses to overcome the issue of the narrow capture range of TPD. Thus, SILPLL can adaptively adjust the injection timing correctly and generate the low jitter clock in a wide frequency range with robust PVT variation tolerance, negligible extra area, and no extra power. A proposed pulse generator (PG) is used for halfintegral injection to relax the tradeoff between the phase noise of SILPLL and the output frequency resolution.
Figure 1: Architecture of proposed wideband SILPLL. Fig. 1 shows the architecture of the proposed wideband SILPLL with adaptively aligned injection timing. It consists of a type-ii PLL, an injection PG, a TPD, and an output buffer. The type-ii PLL includes a phase/frequency detector (PFD), a phase detector buffer (PDBUF), a CP,a fully differential loop filter (LPF), an auto frequency calibration (AFC) circuit, a wideband injection-locked LC-VCO, and an OOPCD divider. The divider consists of a truly single phaseclock multi-modules divider (TSPC MMD) and retiming D flip-flop (DFF). In order to broaden the tuning range and increase power-signal-rejection ratio (PSRR) performance, the CP, loop filter, LC-VCO, and output buffer are implemented in fully differential structures. The OOPCD divider, PG, and TPD are the key building blocks to implement the proposed adaptive injection timing alignment.
Figure 2: Operation procedure of the proposed SILPLL. (a) First phase. (b) Second phase. (c) Third phase. (d) Fourth phase Operation Procedure: The SILPLL mainly operates in four phases to achieve injection locking, as shown in Fig. 2. The four phases perform AFC,PLL output frequency locking, injection timing alignment, and injection locking operations, respectively. The first phase is the AFC phase of the SILPLL to select the optimal control word of digital-control capacitor control array (DCCA) automatically. In the phase, only LC-VCO and AFC circuits are enabled. The AFC done is 0 at this phase. The S1/S2 is open and S3/S4is closed, so the loop at this phase is cut off and the control voltage of LPF is set to be half of the supply voltage VDD. After the AFC phase, AFC_done goes to 1 and then the PLL loop is closed. At this phase, the PFD, CP, LC-VCO, and OOPCD divider are turned on so that the SILPLL goes in to the second phase to track the phase/frequency and locks to the desired frequency as a conventional PLL. At the same time, the falling edges of the PG
output Pulse_PD and the divider output FDIV are aligned. When locking to the correct frequency, PLL enters into the third phase of the injection timing alignment. In such a phase, the injection timing is adjusted by the PG and TPD. The injection timing can be adaptively aligned without the risk of failing to lock when the output frequency changes, as mentioned in Section I. The PFD and OOPCD divider are turned OFF to save power during this phase. After the injection timing alignment in phase three, the injection pulse Pulse_INJ is enabled and the PLL starts to be injection locked in phase four. Since the TPD keeps on working in the background, the SIL PLL can tolerate the PVT variation. Linear Phase Noise Model of Proposed SILPLL: Fig. 3 presents the linear model of the proposed SIL PLL.It is modified from the linear model. The θ PUL_INJ(s),θ CP(s),and θ VCO(s) are the phase noise of injection pulse, CP noise, and VCO phase noise, respectively. Advantages: Figure 3: Linear mode of the proposed SILPLL. Better performance Software implementation: Tanner tool