Wideband Synthesizer with Integrated VCO ADF4351

Data Sheet Wideband Synthesizer with Integrated VCO FEATURES Output frequency range: 35 MHz to 4400 MHz Fractional-N synthesizer and integer-n synthesizer Low phase noise VCO Programmable divide-by-/-2/-4/-8/-6/-32/-64 output Typical jitter: 03 ps rms Typical EVM at 2 GHz: 04% Power supply: 30 V to 36 V Logic compatibility: 8 V Programmable dual-modulus prescaler of 4/5 or 8/9 Programmable output power level RF output mute function 3-wire serial interface Analog and digital lock detect Switched bandwidth fast lock mode Cycle slip reduction APPLICATIONS Wireless infrastructure (W-CDMA, TD-SCDMA, WiMAX, GSM, PCS, DCS, DECT) Test equipment Wireless LANs, CATV equipment Clock generation FUNCTIONAL BLOCK DIAGRAM SDV DD AV DD DV DD V P GENERAL DESCRIPTION The allows implementation of fractional-n or integer-n phase-locked loop (PLL) frequency synthesizers when used with an external loop filter and external reference frequency The has an integrated voltage controlled oscillator (VCO) with a fundamental output frequency ranging from 2200 MHz to 4400 MHz In addition, divide-by-/-2/-4/-8/-6/-32/-64 circuits allow the user to generate RF output frequencies as low as 35 MHz For applications that require isolation, the RF output stage can be muted The mute function is both pin- and software-controllable An auxiliary RF output is also available, which can be powered down when not in use Control of all on-chip registers is through a simple 3-wire interface The device operates with a power supply ranging from 30 V to 36 V and can be powered down when not in use R SET V VCO REF IN 2 DOUBLER 0-BIT R COUNTER 2 DIVIDER LOCK DETECT MULTIPLEXER FAST LOCK SWITCH MUXOUT SW CLK DATA LE DATA REGISTER FUNCTION LATCH CHARGE PUMP LD CP OUT PHASE COMPARATOR V TUNE V REF INTEGER VALUE FRACTION VALUE MODULUS VALUE VCO CORE V COM TEMP THIRD-ORDER FRACTIONAL INTERPOLATOR /2/4/8/6/ 32/64 OUTPUT STAGE RF OUT A+ RF OUT A N COUNTER MULTIPLEXER OUTPUT STAGE PDB RF RF OUT B+ RF OUT B AGND CE DGND CP GND SD GND A GNDVCO Rev 0 Information furnished by Analog Devices is believed to be accurate and reliable However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners Figure MULTIPLEXER One Technology Way, PO Box 906, Norwood, MA 02062-906, USA Tel: 783294700 wwwanalogcom Fax: 784633 202 Analog Devices, Inc All rights reserved 09800-00

TABLE OF CONTENTS Features Applications General Description Functional Block Diagram Revision History 2 Specifications 3 Timing Characteristics 5 Absolute Maximum Ratings 6 Transistor Count 6 Thermal Resistance 6 ESD Caution 6 Pin Configuration and Function Descriptions 7 Typical Performance Characteristics 9 Circuit Description Reference Input Section RF N Divider Phase Frequency Detector (PFD) and Charge Pump MUXOUT and Lock Detect 2 Input Shift Registers 2 Program Modes 2 VCO 2 Output Stage 3 Register Maps 4 Register 0 8 Data Sheet Register 8 Register 2 8 Register 3 9 Register 4 20 Register 5 20 Register Initialization Sequence 20 RF Synthesizer A Worked Example 2 Reference Doubler and Reference Divider 2 2-Bit Programmable Modulus 2 Cycle Slip Reduction for Faster Lock Times 22 Spurious Optimization and Fast Lock 22 Fast Lock Timer and Register Sequences 22 Fast Lock Example 22 Fast Lock Loop Filter Topology 23 Spur Mechanisms 23 Spur Consistency and Fractional Spur Optimization 24 Phase Resync 24 Applications Information 25 Direct Conversion Modulator 25 Interfacing to the ADuC70xx and the ADSP-BF527 26 PCB Design Guidelines for a Chip Scale Package 26 Output Matching 27 Outline Dimensions 28 Ordering Guide 28 REVISION HISTORY 5/2 Revision 0: Initial Version Rev 0 Page 2 of 28

Data Sheet SPECIFICATIONS AV DD = DV DD = V VCO = SDV DD = V P = 33 V ± 0%; AGND = DGND = 0 V; T A = T MIN to T MAX, unless otherwise noted Operating temperature range is 40 C to +85 C Table Parameter Min Typ Max Unit Test Conditions/Comments REF IN CHARACTERISTICS Input Frequency 0 250 MHz For f < 0 MHz, ensure slew rate > 2 V/µs Input Sensitivity 07 AV DD V p-p Biased at AV DD /2; ac coupling ensures AV DD /2 bias Input Capacitance 0 pf Input Current ±60 µa PHASE FREQUENCY DETECTOR (PFD) Phase Detector Frequency 32 MHz Fractional-N 45 MHz Integer-N (band select enabled) 90 MHz Integer-N (band select disabled) CHARGE PUMP I CP Sink/Source R SET = 5 kω High Value 5 ma Low Value 032 ma R SET Range 39 0 kω Sink and Source Current Matching 2 % 05 V V CP 25 V I CP vs V CP 5 % 05 V V CP 25 V I CP vs Temperature 2 % V CP = 20 V LOGIC INPUTS Input High Voltage, V INH 5 V Input Low Voltage, V INL 06 V Input Current, I INH /I INL ± µa Input Capacitance, C IN 30 pf LOGIC OUTPUTS Output High Voltage, V OH DV DD 04 V CMOS output selected Output High Current, I OH 500 µa Output Low Voltage, V OL 04 V I OL = 500 µa POWER SUPPLIES AV DD 30 36 V DV DD, V VCO, SDV DD, V P AV DD These voltages must equal AV DD 2 DI DD + AI DD 2 27 ma Output Dividers 6 to 36 ma Each output divide-by-2 consumes 6 ma 2 I VCO 70 80 ma 2 I RFOUT 2 26 ma RF output stage is programmable Low Power Sleep Mode 7 0 µa RF OUTPUT CHARACTERISTICS VCO Output Frequency 2200 4400 MHz Fundamental VCO mode Minimum VCO Output Frequency Using Dividers 34375 MHz 2200 MHz fundamental output and divide-by-64 selected VCO Sensitivity, K V 40 MHz/V Frequency Pushing (Open-Loop) MHz/V Frequency Pulling (Open-Loop) 90 khz Into 200 VSWR load Harmonic Content (Second) 9 dbc Fundamental VCO output 20 dbc Divided VCO output Harmonic Content (Third) 3 dbc Fundamental VCO output 0 dbc Divided VCO output Rev 0 Page 3 of 28

Data Sheet Parameter Min Typ Max Unit Test Conditions/Comments Minimum RF Output Power 3 4 dbm Programmable in 3 db steps Maximum RF Output Power 3 5 dbm Output Power Variation ± db Minimum VCO Tuning Voltage 05 V Maximum VCO Tuning Voltage 25 V NOISE CHARACTERISTICS VCO Phase Noise Performance Normalized Phase Noise Floor (PN SYNTH ) 4 VCO noise is measured in open-loop conditions 89 dbc/hz 0 khz offset from 22 GHz carrier 4 dbc/hz 00 khz offset from 22 GHz carrier 34 dbc/hz MHz offset from 22 GHz carrier 48 dbc/hz 5 MHz offset from 22 GHz carrier 86 dbc/hz 0 khz offset from 33 GHz carrier dbc/hz 00 khz offset from 33 GHz carrier 34 dbc/hz MHz offset from 33 GHz carrier 45 dbc/hz 5 MHz offset from 33 GHz carrier 83 dbc/hz 0 khz offset from 44 GHz carrier 0 dbc/hz 00 khz offset from 44 GHz carrier 3 dbc/hz MHz offset from 44 GHz carrier 45 dbc/hz 5 MHz offset from 44 GHz carrier PLL loop BW = 500 khz 220 dbc/hz ABP = 6 ns 22 dbc/hz ABP = 3 ns Normalized /f Noise (PN _f ) 5 0 khz offset; normalized to GHz 6 dbc/hz ABP = 6 ns 8 dbc/hz ABP = 3 ns In-Band Phase Noise 00 dbc/hz 3 khz from 228 MHz carrier Integrated RMS Jitter 6 027 ps Spurious Signals Due to PFD 80 dbc Frequency Level of Signal with RF Mute Enabled 40 dbm I CP is internally modified to maintain constant loop gain over the frequency range 2 T A = 25 C; AV DD = DV DD = V VCO = 33 V; prescaler = 8/9; f REFIN = 00 MHz; f PFD = 25 MHz; f RF = 44 GHz 3 Using 50 Ω resistors to V VCO, into a 50 Ω load Power measured with auxiliary RF output disabled The current consumption of the auxiliary output is the same as for the main output 4 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider value) and 0 log f PFD To calculate in-band phase noise performance as seen at the VCO output, use the following formula: PN SYNTH = PN TOT 0 log(f PFD ) 20 log N 5 The PLL phase noise is composed of flicker (/f) noise plus the normalized PLL noise floor The formula for calculating the /f noise contribution at an RF frequency (f RF ) and at a frequency offset (f) is given by PN = PN _f + 0 log(0 khz/f) + 20 log(f RF / GHz) Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL 6 f REFIN = 2288 MHz; f PFD = 3072 MHz; VCO frequency = 422256 MHz; RF OUT = 228 MHz; N = 37; loop BW = 60 khz; I CP = 25 ma; low noise mode The noise was measured with an EVAL-EBZ and the Rohde & Schwarz FSUP signal source analyzer Rev 0 Page 4 of 28

Data Sheet TIMING CHARACTERISTICS AV DD = DV DD = V VCO = SDV DD = V P = 33 V ± 0%; AGND = DGND = 0 V; 8 V and 3 V logic levels used; T A = T MIN to T MAX, unless otherwise noted Table 2 Parameter Limit Unit Description t 20 ns min LE setup time t 2 0 ns min DATA to CLK setup time t 3 0 ns min DATA to CLK hold time t 4 25 ns min CLK high duration t 5 25 ns min CLK low duration t 6 0 ns min CLK to LE setup time t 7 20 ns min LE pulse width Timing Diagram CLK t 4 t 5 t 2 t 3 DATA DB3 (MSB) DB30 DB2 (CONTROL BIT C3) DB (CONTROL BIT C2) DB0 (LSB) (CONTROL BIT C) t 7 LE t t 6 LE Figure 2 Timing Diagram 09800-002 Rev 0 Page 5 of 28

ABSOLUTE MAXIMUM RATINGS T A = 25 C, unless otherwise noted Table 3 Parameter Rating AV DD to GND 03 V to +39 V AV DD to DV DD 03 V to +03 V V VCO to GND 03 V to +39 V V VCO to AV DD 03 V to +03 V Digital I/O Voltage to GND 03 V to V DD + 03 V Analog I/O Voltage to GND 03 V to V DD + 03 V REF IN to GND 03 V to V DD + 03 V Operating Temperature Range 40 C to +85 C Storage Temperature Range 65 C to +25 C Maximum Junction Temperature 50 C Reflow Soldering Peak Temperature 260 C Time at Peak Temperature 40 sec Data Sheet This device is a high performance RF integrated circuit with an ESD rating of <5 kv and is ESD sensitive Proper precautions should be taken for handling and assembly TRANSISTOR COUNT The transistor count for the is 36,955 (CMOS) and 986 (bipolar) THERMAL RESISTANCE Thermal impedance (θ JA ) is specified for a device with the exposed pad soldered to GND Table 4 Thermal Resistance Package Type θ JA Unit 32-Lead LFCSP (CP-32-2) 273 C/W ESD CAUTION GND = AGND = DGND = CP GND = SD GND = A GNDVCO = 0 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability Rev 0 Page 6 of 28

Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS CLK DATA 2 LE 3 CE 4 SW 5 V P 6 CP OUT 7 CP GND 8 AGND 9 32 SDV DD AV DD 0 3 SD GND A GNDVCO 30 MUXOUT RF OUT A+ 2 29 REF IN 3 28 DV DD DGND PIN INDICATOR 27 26 25 TOP VIEW (Not to Scale) PDB RF LD 4 5 6 RF OUT A RF OUT B+ RF OUT B V VCO 24 V REF 23 V COM 22 R SET 2 A GNDVCO 20 V TUNE 9 TEMP 8 A GNDVCO 7 V VCO NOTES THE LFCSP HAS AN EXPOSED PAD THAT MUST BE CONNECTED TO GND Figure 3 Pin Configuration 09800-003 Table 5 Pin Function Descriptions Pin No Mnemonic Description CLK Serial Clock Input Data is clocked into the 32-bit shift register on the CLK rising edge This input is a high impedance CMOS input 2 DATA Serial Data Input The serial data is loaded MSB first with the three LSBs as the control bits This input is a high impedance CMOS input 3 LE Load Enable When LE goes high, the data stored in the 32-bit shift register is loaded into the register that is selected by the three control bits This input is a high impedance CMOS input 4 CE Chip Enable A logic low on this pin powers down the device and puts the charge pump into three-state mode A logic high on this pin powers up the device, depending on the status of the power-down bits 5 SW Fast Lock Switch A connection should be made from the loop filter to this pin when using the fast lock mode 6 V P Charge Pump Power Supply V P must have the same value as AV DD Place decoupling capacitors to the ground plane as close to this pin as possible 7 CP OUT Charge Pump Output When enabled, this output provides ±I CP to the external loop filter The output of the loop filter is connected to V TUNE to drive the internal VCO 8 CP GND Charge Pump Ground This output is the ground return pin for CP OUT 9 AGND Analog Ground Ground return pin for AV DD 0 AV DD Analog Power Supply This pin ranges from 30 V to 36 V Place decoupling capacitors to the analog ground plane as close to this pin as possible AV DD must have the same value as DV DD, 8, 2 A GNDVCO VCO Analog Ground Ground return pins for the VCO 2 RF OUT A+ VCO Output The output level is programmable The VCO fundamental output or a divided-down version is available 3 RF OUT A Complementary VCO Output The output level is programmable The VCO fundamental output or a divideddown version is available 4 RF OUT B+ Auxiliary VCO Output The output level is programmable The VCO fundamental output or a divided-down version is available 5 RF OUT B Complementary Auxiliary VCO Output The output level is programmable The VCO fundamental output or a divided-down version is available 6, 7 V VCO Power Supply for the VCO This pin ranges from 30 V to 36 V Place decoupling capacitors to the analog ground plane as close to these pins as possible V VCO must have the same value as AV DD 9 TEMP Temperature Compensation Output Place decoupling capacitors to the ground plane as close to this pin as possible 20 V TUNE Control Input to the VCO This voltage determines the output frequency and is derived from filtering the CP OUT output voltage Rev 0 Page 7 of 28

Data Sheet Pin No Mnemonic Description 22 R SET Connecting a resistor between this pin and ground sets the charge pump output current The nominal voltage bias at the R SET pin is 055 V The relationship between I CP and R SET is as follows: I CP = 255/R SET where: R SET = 5 kω I CP = 5 ma 23 V COM Internal Compensation Node Biased at half the tuning range Place decoupling capacitors to the ground plane as close to this pin as possible 24 V REF Reference Voltage Place decoupling capacitors to the ground plane as close to this pin as possible 25 LD Lock Detect Output Pin A logic high output on this pin indicates PLL lock A logic low output indicates loss of PLL lock 26 PDB RF RF Power-Down A logic low on this pin mutes the RF outputs This function is also software controllable 27 DGND Digital Ground Ground return pin for DV DD 28 DV DD Digital Power Supply DV DD must have the same value as AV DD Place decoupling capacitors to the ground plane as close to this pin as possible 29 REF IN Reference Input This CMOS input has a nominal threshold of AV DD /2 and a dc equivalent input resistance of 00 kω This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled 30 MUXOUT Multiplexer Output The multiplexer output allows the lock detect value, the N divider value, or the R counter value to be accessed externally 3 SD GND Digital Σ-Δ Modulator Ground Ground return pin for the Σ-Δ modulator 32 SDV DD Power Supply Pin for the Digital Σ-Δ Modulator SDV DD must have the same value as AV DD Place decoupling capacitors to the ground plane as close to this pin as possible EP Exposed Pad Exposed Pad The LFCSP has an exposed pad that must be connected to GND Rev 0 Page 8 of 28

Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS PHASE NOISE (dbc/hz) 40 50 60 70 80 90 00 0 20 30 40 50 60 k 0k 00k M 0M FREQUENCY (Hz) Figure 4 Open-Loop VCO Phase Noise, 22 GHz 09800-04 PHASE NOISE (dbc/hz) 90 00 0 20 30 40 50 60 70 k 0k 00k M 0M FREQUENCY (Hz) DIV DIV2 DIV4 DIV8 DIV6 DIV32 DIV64 Figure 7 Closed-Loop Phase Noise, Fundamental VCO and Dividers, VCO = 22 GHz, PFD = 25 MHz, Loop Filter Bandwidth = 63 khz 09800-07 PHASE NOISE (dbc/hz) 40 50 60 70 80 90 00 0 20 30 PHASE NOISE (dbc/hz) 90 00 0 20 30 40 50 DIV DIV2 DIV4 DIV8 DIV6 DIV32 DIV64 40 50 60 60 k 0k 00k M 0M FREQUENCY (Hz) 09800-05 70 k 0k 00k M 0M FREQUENCY (Hz) 09800-08 Figure 5 Open-Loop VCO Phase Noise, 33 GHz Figure 8 Closed-Loop Phase Noise, Fundamental VCO and Dividers, VCO = 33 GHz, PFD = 25 MHz, Loop Filter Bandwidth = 63 khz PHASE NOISE (dbc/hz) 40 50 60 70 80 90 00 0 20 30 PHASE NOISE (dbc/hz) 90 00 0 20 30 40 50 DIV DIV2 DIV4 DIV8 DIV6 DIV32 DIV64 40 50 60 60 k 0k 00k M 0M FREQUENCY (Hz) 09800-06 70 k 0k 00k M 0M FREQUENCY (Hz) 09800-09 Figure 6 Open-Loop VCO Phase Noise, 44 GHz Figure 9 Closed-Loop Phase Noise, Fundamental VCO and Dividers, VCO = 44 GHz, PFD = 25 MHz, Loop Filter Bandwidth = 63 khz Rev 0 Page 9 of 28

Data Sheet 60 60 70 70 80 80 PHASE NOISE (dbc/hz) 90 00 0 20 30 PHASE NOISE (dbc/hz) 90 00 0 20 30 40 40 50 50 60 k 0k 00k M 0M FREQUENCY (Hz) Figure 0 Fractional-N Spur Performance, Low Noise Mode, W-CDMA Band; RF OUT = 228 MHz, REF IN = 2288 MHz, PFD = 3072 MHz, Output Divide-by-2 Selected; Loop Filter Bandwidth = 60 khz, Channel Spacing = 240 khz; RMS Phase Error = 02, RMS Jitter = 027 ps, EVM = 037% 60 70 80 09800-0 60 k 0k 00k M 0M FREQUENCY (Hz) Figure 3 Fractional-N Spur Performance, Low Noise Mode, LTE Band; RF OUT = 264696 MHz, REF IN = 2288 MHz, PFD = 3072 MHz; Loop Filter Bandwidth = 60 khz, Channel Spacing = 240 khz; Phase Word = 9, RMS Phase Error = 028, RMS Jitter = 029 ps, EVM = 049% 60 70 80 09800-3 PHASE NOISE (dbc/hz) 90 00 0 20 30 PHASE NOISE (dbc/hz) 90 00 0 20 30 40 40 50 50 60 k 0k 00k M 0M FREQUENCY (Hz) Figure Fractional-N Spur Performance, Low Spur Mode, W-CDMA Band; RF OUT = 228 MHz, REF IN = 2288 MHz, PFD = 3072 MHz, Output Divide-by-2 Selected; Loop Filter Bandwidth = 60 khz, Channel Spacing = 240 khz; RMS Phase Error = 037, RMS Jitter = 049 ps, EVM = 064% 60 70 80 09800-60 k 0k 00k M 0M FREQUENCY (Hz) Figure 4 Fractional-N Spur Performance, Low Spur Mode, LTE Band; RF OUT = 264696 MHz, REF IN = 2288 MHz, PFD = 3072 MHz; Loop Filter Bandwidth = 60 khz, Channel Spacing = 240 khz; RMS Phase Error = 056, RMS Jitter = 059 ps, EVM = 098% 60 70 80 09800-4 PHASE NOISE (dbc/hz) 90 00 0 20 30 PHASE NOISE (dbc/hz) 90 00 0 20 30 40 40 50 50 60 k 0k 00k M 0M FREQUENCY (Hz) Figure 2 Fractional-N Spur Performance, Low Noise Mode, W-CDMA Band; RF OUT = 228 MHz, REF IN = 2288 MHz, PFD = 3072 MHz, Output Divide-by-2 Selected; Loop Filter Bandwidth = 20 khz, Channel Spacing = 240 khz; RMS Phase Error = 025, RMS Jitter = 032 ps, EVM = 044% 09800-2 60 k 0k 00k M 0M FREQUENCY (Hz) Figure 5 Fractional-N Spur Performance, Low Noise Mode, W-CDMA Band; RF OUT = 264696 MHz, REF IN = 2288 MHz, PFD = 3072 MHz; Loop Filter Bandwidth = 20 khz, Channel Spacing = 240 khz; RMS Phase Error = 035, RMS Jitter = 036 ps, EVM = 06% 09800-5 Rev 0 Page 0 of 28

Data Sheet CIRCUIT DESCRIPTION REFERENCE INPUT SECTION The reference input stage is shown in Figure 6 The SW and SW2 switches are normally closed The SW3 switch is normally open When power-down is initiated, SW3 is closed, and SW and SW2 are opened In this way, no loading of the REF IN pin occurs during power-down REF IN NC RF N DIVIDER POWER-DOWN CONTROL SW NO NC SW2 SW3 00kΩ BUFFER Figure 6 Reference Input Stage TO R COUNTER The RF N divider allows a division ratio in the PLL feedback path The division ratio is determined by the INT, FRAC, and MOD values, which build up this divider (see Figure 7) FROM VCO OUTPUT/ OUTPUT DIVIDERS RF N DIVIDER N COUNTER N = INT + FRAC/MOD THIRD-ORDER FRACTIONAL INTERPOLATOR 09800-005 TO PFD The PFD frequency (f PFD ) equation is f PFD = REF IN [( + D)/(R ( + T))] (2) where: REF IN is the reference input frequency D is the REF IN doubler bit (0 or ) R is the preset divide ratio of the binary 0-bit programmable reference counter ( to 023) T is the REF IN divide-by-2 bit (0 or ) Integer-N Mode If FRAC = 0 and the DB8 (LDF) bit in Register 2 is set to, the synthesizer operates in integer-n mode The DB8 bit in Register 2 should be set to for integer-n digital lock detect R Counter The 0-bit R counter allows the input reference frequency (REF IN ) to be divided down to produce the reference clock to the PFD Division ratios from to 023 are allowed PHASE FREQUENCY DETECTOR (PFD) AND CHARGE PUMP The phase frequency detector (PFD) takes inputs from the R counter and N counter and produces an output proportional to the phase and frequency difference between them Figure 8 is a simplified schematic of the phase frequency detector HIGH D Q UP INT VALUE FRAC VALUE MOD VALUE +IN U CLR Figure 7 RF N Divider INT, FRAC, MOD, and R Counter Relationship The INT, FRAC, and MOD values, in conjunction with the R counter, make it possible to generate output frequencies that are spaced by fractions of the PFD frequency For more information, see the RF Synthesizer A Worked Example section The RF VCO frequency (RF OUT ) equation is RF OUT = f PFD (INT + (FRAC/MOD)) () where: RF OUT is the output frequency of the voltage controlled oscillator (VCO) INT is the preset divide ratio of the binary 6-bit counter (23 to 65,535 for the 4/5 prescaler; 75 to 65,535 for the 8/9 prescaler) FRAC is the numerator of the fractional division (0 to MOD ) MOD is the preset fractional modulus (2 to 4095) 09800-006 HIGH IN CLR2 D2 Q2 U2 DELAY DOWN U3 CHARGE PUMP Figure 8 PFD Simplified Schematic CP OUT The PFD includes a programmable delay element that sets the width of the antibacklash pulse (ABP) This pulse ensures that there is no dead zone in the PFD transfer function Bit DB22 in Register 3 (R3) is used to set the ABP as follows: When Bit DB22 is set to 0, the ABP width is programmed to 6 ns, the recommended value for fractional-n applications When Bit DB22 is set to, the ABP width is programmed to 3 ns, the recommended value for integer-n applications For integer-n applications, the in-band phase noise is improved by enabling the shorter pulse width The PFD frequency can operate up to 90 MHz in this mode To operate with PFD frequencies higher than 45 MHz, VCO band select must be disabled by setting the phase adjust bit (DB28) to in Register 09800-007 Rev 0 Page of 28

MUXOUT AND LOCK DETECT The multiplexer output on the allows the user to access various internal points on the chip The state of MUXOUT is controlled by the M3, M2, and M bits in Register 2 (see Figure 26) Figure 9 shows the MUXOUT section in block diagram form THREE-STATE OUTPUT DV DD DGND R COUNTER OUTPUT N DIVIDER OUTPUT ANALOG LOCK DETECT DIGITAL LOCK DETECT MUX CONTROL Figure 9 MUXOUT Schematic DV DD DGND MUXOUT INPUT SHIFT REGISTERS The digital section includes a 0-bit RF R counter, a 6-bit RF N counter, a 2-bit FRAC counter, and a 2-bit modulus counter Data is clocked into the 32-bit shift register on each rising edge of CLK The data is clocked in MSB first Data is transferred from the shift register to one of six latches on the rising edge of LE The destination latch is determined by the state of the three control bits (C3, C2, and C) in the shift register As shown in Figure 2, the control bits are the three LSBs: DB2, DB, and DB0 Table 6 shows the truth table for these bits Figure 23 summarizes how the latches are programmed Table 6 Truth Table for the C3, C2, and C Control Bits Control Bits C3 C2 C Register 0 0 0 Register 0 (R0) 0 0 Register (R) 0 0 Register 2 (R2) 0 Register 3 (R3) 0 0 Register 4 (R4) 0 Register 5 (R5) 09800-008 Data Sheet PROGRAM MODES Table 6 and Figure 23 through Figure 29 show how the program modes are set up in the The following settings in the are double buffered: phase value, modulus value, reference doubler, reference divide-by-2, R counter value, and charge pump current setting Before the part uses a new value for any double-buffered setting, the following two events must occur: The new value is latched into the device by writing to the appropriate register 2 A new write is performed on Register 0 (R0) For example, any time that the modulus value is updated, Register 0 (R0) must be written to, to ensure that the modulus value is loaded correctly The divider select value in Register 4 (R4) is also double buffered, but only if the DB3 bit of Register 2 (R2) is set to VCO The VCO core in the consists of three separate VCOs, each of which uses 6 overlapping bands, as shown in Figure 20, to allow a wide frequency range to be covered without a large VCO sensitivity (K V ) and resultant poor phase noise and spurious performance V TUNE (V) 30 25 20 5 0 05 0 20 25 30 35 40 45 FREQUENCY (GHz) Figure 20 V TUNE vs Frequency The correct VCO and band are selected automatically by the VCO and band select logic at power-up or whenever Register 0 (R0) is updated VCO and band selection take 0 PFD cycles multiplied by the value of the band select clock divider The VCO V TUNE is disconnected from the output of the loop filter and is connected to an internal reference voltage 09800-20 Rev 0 Page 2 of 28

Data Sheet The R counter output is used as the clock for the band select logic A programmable divider is provided at the R counter output to allow division by an integer from to 255; the divider value is set using Bits[DB9:DB2] in Register 4 (R4) When the required PFD frequency is higher than 25 khz, the divide ratio should be set to allow enough time for correct band selection Band selection takes 0 cycles of the PFD frequency, equal to 80 µs If faster lock times are required, Bit DB23 in Register 3 (R3) must be set to This setting allows the user to select a higher band select clock frequency of up to 500 khz, which speeds up the minimum band select time to 20 µs For phase adjustments and small (< MHz) frequency adjustments, the user can disable VCO band selection by setting Bit DB28 in Register (R) to This setting selects the phase adjust feature After band selection, normal PLL action resumes The nominal value of K V is 40 MHz/V when the N divider is driven from the VCO output or from this value divided by D D is the output divider value if the N divider is driven from the RF divider output (selected by programming Bits[DB22:DB20] in Register 4) The contains linearization circuitry to minimize any variation of the product of I CP and K V to keep the loop bandwidth constant The VCO shows variation of K V as the V TUNE varies within the band and from band to band For wideband applications covering a wide frequency range (and changing output dividers), a value of 40 MHz/V provides the most accurate K V because this value is closest to an average value Figure 2 shows how K V varies with fundamental VCO frequency, along with an average value for the frequency band Users may prefer this figure when using narrow-band designs VCO SENSITIVITY (MHz/V) 80 70 60 50 40 30 20 OUTPUT STAGE The RF OUT A+ and RF OUT A pins of the are connected to the collectors of an NPN differential pair driven by buffered outputs of the VCO, as shown in Figure 22 VCO BUFFER/ DIVIDE-BY-/-2/-4/-8/ -6/-32/-64 Figure 22 Output Stage RF OUT A+ RF OUT A To allow the user to optimize the power dissipation vs the output power requirements, the tail current of the differential pair is programmable using Bits[DB4:DB3] in Register 4 (R4) Four current levels can be set These levels give output power levels of 4 dbm, dbm, +2 dbm, and +5 dbm, using a 50 Ω resistor to AV DD and ac coupling into a 50 Ω load Alternatively, both outputs can be combined in a + : transformer or a 80 microstrip coupler (see the Output Matching section) If the outputs are used individually, the optimum output stage consists of a shunt inductor to V VCO The unused complementary output must be terminated with a similar circuit to the used output An auxiliary output stage exists on the RF OUT B+ and RF OUT B pins, providing a second set of differential outputs that can be used to drive another circuit The auxiliary output stage can be used only if the primary outputs are enabled If the auxiliary output stage is not used, it can be powered down Another feature of the is that the supply current to the RF output stage can be shut down until the part achieves lock, as measured by the digital lock detect circuitry This feature is enabled by setting the mute till lock detect (MTLD) bit in Register 4 (R4) 09800-00 0 0 20 25 30 35 40 45 FREQUENCY (GHz) Figure 2 VCO Sensitivity (K V ) vs Frequency 09800-2 Rev 0 Page 3 of 28

Data Sheet REGISTER MAPS REGISTER 0 6-BIT INTEGER VALUE (INT) 2-BIT FRACTIONAL VALUE (FRAC) CONTROL BITS DB3 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB2 DB20 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB0 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB0 0 N6 N5 N4 N3 N2 N N0 N9 N8 N7 N6 N5 N4 N3 N2 N F2 F F0 F9 F8 F7 F6 F5 F4 F3 F2 F C3(0) C2(0) C(0) REGISTER PHASE ADJUST PRESCALER 2-BIT PHASE VALUE (PHASE) DBR 2-BIT MODULUS VALUE (MOD) DBR CONTROL BITS DB3 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB2 DB20 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB0 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB0 0 0 0 PH PR P2 P P0 P9 P8 P7 P6 P5 P4 P3 P2 P M2 M M0 M9 M8 M7 M6 M5 M4 M3 M2 M C3(0) C2(0) C() REGISTER 2 LOW NOISE AND LOW SPUR MODES MUXOUT DBR REFERENCE DOUBLER DBR RDIV2 0-BIT R COUNTER DOUBLE BUFFER CHARGE PUMP CURRENT SETTING DBR DBR LDF LDP PD POLARITY POWER-DOWN CP THREE- STATE COUNTER RESET CONTROL BITS DB3 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB2 DB20 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB0 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB0 0 L2 L M3 M2 M RD2 RD R0 R9 R8 R7 R6 R5 R4 R3 R2 R D CP4 CP3 CP2 CP U6 U5 U4 U3 U2 U C3(0) C2() C(0) REGISTER 3 BAND SELECT CLOCK MODE ABP CHARGE CANCEL CSR CLK DIV MODE 2-BIT CLOCK DIVIDER VALUE CONTROL BITS DB3 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB2 DB20 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB0 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB0 0 0 0 0 0 0 0 0 F4 F3 F2 0 0 F 0 C2 C D2 D D0 D9 D8 D7 D6 D5 D4 D3 D2 D C3(0) C2() C() REGISTER 4 FEEDBACK SELECT DBB 2 RF DIVIDER SELECT 8-BIT BAND SELECT CLOCK DIVIDER VALUE VCO POWER- DOWN MTLD AUX OUTPUT SELECT AUX OUTPUT ENABLE AUX OUTPUT POWER RF OUTPUT ENABLE OUTPUT POWER CONTROL BITS DB3 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB2 DB20 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB0 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB0 0 0 0 0 0 0 0 0 D3 D2 D D0 BS8 BS7 BS6 BS5 BS4 BS3 BS2 BS D9 D8 D7 D6 D5 D4 D3 D2 D C3() C2(0) C(0) REGISTER 5 LD PIN MODE CONTROL BITS DB3 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB2 DB20 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB0 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB0 0 0 0 0 0 0 0 0 D5 D4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C3() C2(0) C() DBR = DOUBLE-BUFFERED REGISTER BUFFERED BY THE WRITE TO REGISTER 0 2DBB = DOUBLE-BUFFERED BITS BUFFERED BY THE WRITE TO REGISTER 0, IF AND ONLY IF DB3 OF REGISTER 2 IS HIGH 09800-023 Figure 23 Register Summary Rev 0 Page 4 of 28

Data Sheet 6-BIT INTEGER VALUE (INT) 2-BIT FRACTIONAL VALUE (FRAC) CONTROL BITS DB3 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB2 DB20 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB0 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB0 0 N6 N5 N4 N3 N2 N N0 N9 N8 N7 N6 N5 N4 N3 N2 N F2 F F0 F9 F8 F7 F6 F5 F4 F3 F2 F C3(0) C2(0) C(0) N6 N5 N5 N4 N3 N2 N INTEGER VALUE (INT) 0 0 0 0 0 0 0 NOT ALLOWED 0 0 0 0 0 0 NOT ALLOWED 0 0 0 0 0 0 NOT ALLOWED 0 0 0 0 NOT ALLOWED 0 0 0 23 0 0 0 0 0 24 0 65,533 0 65,534 65,535 INTmin = 75 WITH PRESCALER = 8/9 Figure 24 Register 0 (R0) F2 F F2 F FRACTIONAL VALUE (FRAC) 0 0 0 0 0 0 0 0 0 0 0 2 0 0 3 0 0 4092 0 4093 0 4094 4095 09800-02 PHASE ADJUST PRESCALER 2-BIT PHASE VALUE (PHASE) DBR 2-BIT MODULUS VALUE (MOD) DBR CONTROL BITS DB3 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB2 DB20 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB0 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB0 0 0 0 PH PR P2 P P0 P9 P8 P7 P6 P5 P4 P3 P2 P M2 M M0 M9 M8 M7 M6 M5 M4 M3 M2 M C3(0) C2(0) C() P2 P P2 P PHASE VALUE (PHASE) M2 M M2 M INTERPOLATOR MODULUS (MOD) PH PHASE ADJ 0 OFF ON 0 0 0 0 0 0 0 0 (RECOMMENDED) 0 0 0 2 0 0 3 0 0 4092 0 0 0 0 0 0 0 0 0 2 3 4092 4093 4094 4095 PR PRESCALER 0 4/5 8/9 0 4093 0 4094 4095 09800-03 Figure 25 Register (R) Rev 0 Page 5 of 28

Data Sheet LOW NOISE AND LOW SPUR MODES MUXOUT REFERENCE DOUBLER DBR RDIV2 DBR 0-BIT R COUNTER DBR DOUBLE BUFFER CHARGE PUMP CURRENT SETTING LDF LDP PD POLARITY POWER-DOWN CP THREE- STATE COUNTER RESET CONTROL BITS DB3 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB2 DB20 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB0 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB0 0 L2 L M3 M2 M RD2 RD R0 R9 R8 R7 R6 R5 R4 R3 R2 R D CP4 CP3 CP2 CP U6 U5 U4 U3 U2 U C3(0) C2() C(0) L2 L NOISE MODE 0 0 LOW NOISE MODE 0 0 LOW SPUR MODE M3 M2 M OUTPUT RD2 REFERENCE DOUBLER 0 DISABLED ENABLED RD REFERENCE DIVIDE-BY-2 0 DISABLED ENABLED R0 R9 R2 R R COUNTER (R) 0 0 0 0 0 0 2 0 0 020 0 02 0 022 023 D DOUBLE BUFFER R4 [DB22:DB20] 0 DISABLED ENABLED CP4 CP3 CP2 CP I CP (ma) 5kΩ 0 0 0 0 03 0 0 0 063 0 0 0 094 0 0 25 0 0 0 56 0 0 88 0 0 29 0 250 0 0 0 28 0 0 33 0 0 344 0 375 0 0 406 0 438 0 469 500 U6 LDF 0 FRAC-N INT-N U5 LDP 0 0ns 6ns U4 PD POLARITY 0 NEGATIVE POSITIVE U COUNTER RESET 0 DISABLED ENABLED U2 CP THREE-STATE 0 DISABLED ENABLED U3 POWER-DOWN 0 DISABLED ENABLED 0 0 0 THREE-STATE OUTPUT 0 0 DV DD 0 0 DGND 0 R COUNTER OUTPUT 0 0 N DIVIDER OUTPUT 0 ANALOG LOCK DETECT 0 DIGITAL LOCK DETECT 09800-04 Figure 26 Register 2 (R2) BAND SELECT CLOCK MODE ABP CHARGE CANCEL CSR CLK DIV MODE 2-BIT CLOCK DIVIDER VALUE CONTROL BITS DB3 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB2 DB20 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB0 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB0 0 0 0 0 0 0 0 0 F4 F3 F2 0 0 F 0 C2 C D2 D D0 D9 D8 D7 D6 D5 D4 D3 D2 D C3(0) C2() C() CYCLE SLIP F REDUCTION 0 DISABLED ENABLED D2 D D2 D CLOCK DIVIDER VALUE 0 0 0 0 0 0 0 0 0 0 0 2 F4 BAND SELECT CLOCK MODE 0 LOW HIGH F3 CHARGE F2 CANCELATION 0 DISABLED ENABLED ANTIBACKLASH PULSE WIDTH 0 6ns (FRAC-N) 3ns (INT-N) C2 C CLOCK DIVIDER MODE 0 0 CLOCK DIVIDER OFF 0 FAST LOCK ENABLE 0 RESYNC ENABLE 0 0 3 0 0 4092 0 4093 0 4094 4095 09800-05 Figure 27 Register 3 (R3) Rev 0 Page 6 of 28

Data Sheet FEEDBACK SELECT RF DIVIDER SELECT DBB 8-BIT BAND SELECT CLOCK DIVIDER VALUE VCO POWER- DOWN MTLD AUX OUTPUT SELECT AUX OUTPUT ENABLE AUX OUTPUT POWER RF OUTPUT ENABLE OUTPUT POWER CONTROL BITS DB3 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB2 DB20 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB0 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB0 0 0 0 0 0 0 0 0 D3 D2 D D0 BS8 BS7 BS6 BS5 BS4 BS3 BS2 BS D9 D8 D7 D6 D5 D4 D3 D2 D C3() C2(0) C(0) D3 FEEDBACK SELECT 0 DIVIDED FUNDAMENTAL D2 D D0 RF DIVIDER SELECT 0 0 0 0 0 2 0 0 4 0 8 0 0 6 0 32 0 64 BS8 BS7 BS2 BS BAND SELECT CLOCK DIVIDER 0 0 0 0 0 0 2 0 0 252 0 253 0 254 255 VCO D9 POWER-DOWN 0 VCO POWERED UP VCO POWERED DOWN Figure 28 Register 4 (R4) MUTE TILL D8 LOCK DETECT 0 MUTE DISABLED MUTE ENABLED D7 0 AUX OUTPUT SELECT DIVIDED OUTPUT FUNDAMENTAL D6 AUX OUT 0 DISABLED ENABLED D2 D OUTPUT POWER 0 0 4dBm 0 dbm 0 +2dBm +5dBm D3 RF OUT 0 DISABLED ENABLED D5 D4 AUX OUTPUT POWER 0 0 4dBm 0 dbm 0 +2dBm +5dBm 09800-06 LD PIN MODE CONTROL BITS DB3 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB2 DB20 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB0 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB0 0 0 0 0 0 0 0 0 D5 D4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C3() C2(0) C() D5 D4 LOCK DETECT PIN OPERATION 0 0 LOW 0 DIGITAL LOCK DETECT 0 LOW HIGH 09800-07 Figure 29 Register 5 (R5) Rev 0 Page 7 of 28

REGISTER 0 Control Bits When Bits[C3:C] are set to 000, Register 0 is programmed Figure 24 shows the input data format for programming this register 6-Bit Integer Value (INT) The 6 INT bits (Bits[DB30:DB5]) set the INT value, which determines the integer part of the feedback division factor The INT value is used in Equation (see the INT, FRAC, MOD, and R Counter Relationship section) Integer values from 23 to 65,535 are allowed for the 4/5 prescaler; for the 8/9 prescaler, the minimum integer value is 75 2-Bit Fractional Value (FRAC) The 2 FRAC bits (Bits[DB4:DB3]) set the numerator of the fraction that is input to the Σ-Δ modulator This fraction, along with the INT value, specifies the new frequency channel that the synthesizer locks to, as shown in the RF Synthesizer A Worked Example section FRAC values from 0 to (MOD ) cover channels over a frequency range equal to the PFD reference frequency REGISTER Control Bits When Bits[C3:C] are set to 00, Register is programmed Figure 25 shows the input data format for programming this register Phase Adjust The phase adjust bit (Bit DB28) enables adjustment of the output phase of a given output frequency When phase adjustment is enabled (Bit DB28 is set to ), the part does not perform VCO band selection or phase resync when Register 0 is updated When phase adjustment is disabled (Bit DB28 is set to 0), the part performs VCO band selection and phase resync (if phase resync is enabled in Register 3, Bits[DB6:DB5]) when Register 0 is updated Disabling VCO band selection is recommended only for fixed frequency applications or for frequency deviations of < MHz from the originally selected frequency Prescaler Value The dual-modulus prescaler (P/P + ), along with the INT, FRAC, and MOD values, determines the overall division ratio from the VCO output to the PFD input The PR bit (DB27) in Register sets the prescaler value Operating at CML levels, the prescaler takes the clock from the VCO output and divides it down for the counters The prescaler is based on a synchronous 4/5 core When the prescaler is set to 4/5, the maximum RF frequency allowed is 36 GHz Therefore, when operating the above 36 GHz, the prescaler must be set to 8/9 The prescaler limits the INT value as follows: Prescaler = 4/5: N MIN = 23 Prescaler = 8/9: N MIN = 75 Data Sheet 2-Bit Phase Value Bits[DB26:DB5] control the phase word The phase word must be less than the MOD value programmed in Register The phase word is used to program the RF output phase from 0 to 360 with a resolution of 360 /MOD (see the Phase Resync section) In most applications, the phase relationship between the RF signal and the reference is not important In such applications, the phase value can be used to optimize the fractional and subfractional spur levels For more information, see the Spur Consistency and Fractional Spur Optimization section If neither the phase resync nor the spurious optimization function is used, it is recommended that the phase word be set to 2-Bit Modulus Value (MOD) The 2 MOD bits (Bits[DB4:DB3]) set the fractional modulus The fractional modulus is the ratio of the PFD frequency to the channel step resolution on the RF output For more information, see the 2-Bit Programmable Modulus section REGISTER 2 Control Bits When Bits[C3:C] are set to 00, Register 2 is programmed Figure 26 shows the input data format for programming this register Low Noise and Low Spur Modes The noise mode on the is controlled by setting Bits[DB30:DB29] in Register 2 (see Figure 26) The noise mode allows the user to optimize a design either for improved spurious performance or for improved phase noise performance When the low spur mode is selected, dither is enabled Dither randomizes the fractional quantization noise so that it resembles white noise rather than spurious noise As a result, the part is optimized for improved spurious performance Low spur mode is normally used for fast-locking applications when the PLL closed-loop bandwidth is wide Wide loop bandwidth is a loop bandwidth greater than /0 of the RF OUT channel step resolution (f RES ) A wide loop filter does not attenuate the spurs to the same level as a narrow loop bandwidth For best noise performance, use the low noise mode option When the low noise mode is selected, dither is disabled This mode ensures that the charge pump operates in an optimum region for noise performance Low noise mode is extremely useful when a narrow loop filter bandwidth is available The synthesizer ensures extremely low noise, and the filter attenuates the spurs Figure 0 through Figure 2 show the trade-offs in a typical W-CDMA setup for different noise and spur settings MUXOUT The on-chip multiplexer is controlled by Bits[DB28:DB26] (see Figure 26) Note that N counter output must be disabled for VCO band selection to operate correctly Rev 0 Page 8 of 28

Data Sheet Reference Doubler Setting the DB25 bit to 0 disables the doubler and feeds the REF IN signal directly into the 0-bit R counter Setting this bit to multiplies the REF IN frequency by a factor of 2 before feeding it into the 0-bit R counter When the doubler is disabled, the REF IN falling edge is the active edge at the PFD input to the fractional synthesizer When the doubler is enabled, both the rising and falling edges of REF IN become active edges at the PFD input When the doubler is enabled and the low spur mode is selected, the in-band phase noise performance is sensitive to the REF IN duty cycle The phase noise degradation can be as much as 5 db for REF IN duty cycles outside a 45% to 55% range The phase noise is insensitive to the REF IN duty cycle in the low noise mode and when the doubler is disabled The maximum allowable REF IN frequency when the doubler is enabled is 30 MHz RDIV2 Setting the DB24 bit to inserts a divide-by-2 toggle flip-flop between the R counter and the PFD, which extends the maximum REF IN input rate This function allows a 50% duty cycle signal to appear at the PFD input, which is necessary for cycle slip reduction 0-Bit R Counter The 0-bit R counter (Bits[DB23:DB4]) allows the input reference frequency (REF IN ) to be divided down to produce the reference clock to the PFD Division ratios from to 023 are allowed Double Buffer The DB3 bit enables or disables double buffering of Bits[DB22:DB20] in Register 4 For information about how double buffering works, see the Program Modes section Charge Pump Current Setting Bits[DB2:DB9] set the charge pump current This value should be set to the charge pump current that the loop filter is designed with (see Figure 26) Lock Detect Function (LDF) The DB8 bit configures the lock detect function (LDF) The LDF controls the number of PFD cycles monitored by the lock detect circuit to ascertain whether lock has been achieved When DB8 is set to 0, the number of PFD cycles monitored is 40 When DB8 is set to, the number of PFD cycles monitored is 5 It is recommended that the DB8 bit be set to 0 for fractional-n mode and to for integer-n mode Lock Detect Precision (LDP) The lock detect precision bit (Bit DB7) sets the comparison window in the lock detect circuit When DB7 is set to 0, the comparison window is 0 ns; when DB7 is set to, the window is 6 ns The lock detect circuit goes high when n consecutive PFD cycles are less than the comparison window value; n is set by the LDF bit (DB8) For example, with DB8 = 0 and DB7 = 0, 40 consecutive PFD cycles of 0 ns or less must occur before digital lock detect goes high Rev 0 Page 9 of 28 For fractional-n applications, the recommended setting for Bits[DB8:DB7] is 00; for integer-n applications, the recommended setting for Bits[DB8:DB7] is Phase Detector Polarity The DB6 bit sets the phase detector polarity When a passive loop filter or a noninverting active loop filter is used, this bit should be set to If an active filter with an inverting characteristic is used, this bit should be set to 0 Power-Down (PD) The DB5 bit provides the programmable power-down mode Setting this bit to performs a power-down Setting this bit to 0 returns the synthesizer to normal operation In software powerdown mode, the part retains all information in its registers The register contents are lost only if the supply voltages are removed When power-down is activated, the following events occur: Synthesizer counters are forced to their load state conditions VCO is powered down Charge pump is forced into three-state mode Digital lock detect circuitry is reset RF OUT buffers are disabled Input registers remain active and capable of loading and latching data Charge Pump Three-State Setting the DB4 bit to puts the charge pump into three-state mode This bit should be set to 0 for normal operation Counter Reset The DB3 bit is the reset bit for the R counter and the N counter of the When this bit is set to, the RF synthesizer N counter and R counter are held in reset For normal operation, this bit should be set to 0 REGISTER 3 Control Bits When Bits[C3:C] are set to 0, Register 3 is programmed Figure 27 shows the input data format for programming this register Band Select Clock Mode Setting the DB23 bit to selects a faster logic sequence of band selection, which is suitable for high PFD frequencies and is necessary for fast lock applications Setting the DB23 bit to 0 is recommended for low PFD (<25 khz) values For the faster band select logic modes (DB23 set to ), the value of the band select clock divider must be less than or equal to 254 Antibacklash Pulse Width (ABP) Bit DB22 sets the PFD antibacklash pulse width When Bit DB22 is set to 0, the PFD antibacklash pulse width is 6 ns This setting is recommended for fractional-n use When Bit DB22 is set to, the PFD antibacklash pulse width is 3 ns, which results in phase noise and spur improvements in integer-n operation For fractional-n operation, the 3 ns setting is not recommended

Charge Cancelation Setting the DB2 bit to enables charge pump charge cancelation This has the effect of reducing PFD spurs in integer-n mode In fractional-n mode, this bit should be set to 0 CSR Enable Setting the DB8 bit to enables cycle slip reduction CSR is a method for improving lock times Note that the signal at the phase frequency detector (PFD) must have a 50% duty cycle for cycle slip reduction to work The charge pump current setting must also be set to a minimum For more information, see the Cycle Slip Reduction for Faster Lock Times section Clock Divider Mode Bits[DB6:DB5] must be set to 0 to activate phase resync (see the Phase Resync section) These bits must be set to 0 to activate fast lock (see the Fast Lock Timer and Register Sequences section) Setting Bits[DB6:DB5] to 00 disables the clock divider (see Figure 27) 2-Bit Clock Divider Value Bits[DB4:DB3] set the 2-bit clock divider value This value is the timeout counter for activation of phase resync (see the Phase Resync section) The clock divider value also sets the timeout counter for fast lock (see the Fast Lock Timer and Register Sequences section) REGISTER 4 Control Bits When Bits[C3:C] are set to 00, Register 4 is programmed Figure 28 shows the input data format for programming this register Feedback Select The DB23 bit selects the feedback from the VCO output to the N counter When this bit is set to, the signal is taken directly from the VCO When this bit is set to 0, the signal is taken from the output of the output dividers The dividers enable coverage of the wide frequency band (34375 MHz to 44 GHz) When the dividers are enabled and the feedback signal is taken from the output, the RF output signals of two separately configured PLLs are in phase This is useful in some applications where the positive interference of signals is required to increase the power RF Divider Select Bits[DB22:DB20] select the value of the RF output divider (see Figure 28) Band Select Clock Divider Value Bits[DB9:DB2] set a divider for the band select logic clock input By default, the output of the R counter is the value used to clock the band select logic, but, if this value is too high (>25 khz), a divider can be switched on to divide the R counter output to a smaller value (see Figure 28) Data Sheet VCO Power-Down Setting the DB bit to 0 powers the VCO up; setting this bit to powers the VCO down Mute Till Lock Detect (MTLD) When the DB0 bit is set to, the supply current to the RF output stage is shut down until the part achieves lock, as measured by the digital lock detect circuitry AUX Output Select The DB9 bit sets the auxiliary RF output If DB9 is set to 0, the auxiliary RF output is the output of the RF dividers; if DB9 is set to, the auxiliary RF output is the fundamental VCO frequency AUX Output Enable The DB8 bit enables or disables the auxiliary RF output If DB8 is set to 0, the auxiliary RF output is disabled; if DB8 is set to, the auxiliary RF output is enabled AUX Output Power Bits[DB7:DB6] set the value of the auxiliary RF output power level (see Figure 28) RF Output Enable The DB5 bit enables or disables the primary RF output If DB5 is set to 0, the primary RF output is disabled; if DB5 is set to, the primary RF output is enabled Output Power Bits[DB4:DB3] set the value of the primary RF output power level (see Figure 28) REGISTER 5 Control Bits When Bits[C3:C] are set to 0, Register 5 is programmed Figure 29 shows the input data format for programming this register Lock Detect Pin Operation Bits[DB23:DB22] set the operation of the lock detect (LD) pin (see Figure 29) REGISTER INITIALIZATION SEQUENCE At initial power-up, after the correct application of voltages to the supply pins, the registers should be started in the following sequence: Register 5 2 Register 4 3 Register 3 4 Register 2 5 Register 6 Register 0 Rev 0 Page 20 of 28

Data Sheet RF SYNTHESIZER A WORKED EXAMPLE The following equations are used to program the synthesizer: RF OUT = [INT + (FRAC/MOD)] (f PFD /RF Divider) (3) where: RF OUT is the RF frequency output INT is the integer division factor FRAC is the numerator of the fractional division (0 to MOD ) MOD is the preset fractional modulus (2 to 4095) RF Divider is the output divider that divides down the VCO frequency f PFD = REF IN [( + D)/(R ( + T))] (4) where: REF IN is the reference frequency input D is the RF REF IN doubler bit (0 or ) R is the RF reference division factor ( to 023) T is the reference divide-by-2 bit (0 or ) As an example, a UMTS system requires a 226 MHz RF frequency output (RF OUT ); a 0 MHz reference frequency input (REF IN ) is available and a 200 khz channel resolution (f RESOUT ) is required on the RF output Note that the VCO operates in the frequency range of 22 GHz to 44 GHz Therefore, the RF divider of 2 should be used (VCO frequency = 42252 MHz, RF OUT = VCO frequency/ RF divider = 42252 MHz/2 = 226 MHz) It is also important where the loop is closed In this example, the loop is closed before the output divider (see Figure 30) f PFD PFD VCO N DIVIDER 2 RF OUT Figure 30 Loop Closed Before Output Divider Channel resolution (f RESOUT ) of 200 khz is required at the output of the RF divider Therefore, the channel resolution at the output of the VCO (f RES ) needs to be 2 f RESOUT, that is, 400 khz MOD = REF IN /f RES MOD = 0 MHz/400 khz = 25 From Equation 4, f PFD = [0 MHz ( + 0)/] = 0 MHz (5) 226 MHz = 0 MHz [(INT + (FRAC/25))/2] (6) where: INT = 422 FRAC = 3 09800-027 REFERENCE DOUBLER AND REFERENCE DIVIDER The on-chip reference doubler allows the input reference signal to be doubled Doubling the reference signal doubles the PFD comparison frequency, which improves the noise performance of the system Doubling the PFD frequency usually improves noise performance by 3 db Note that in fractional-n mode, the PFD cannot operate above 32 MHz due to a limitation in the speed of the Σ-Δ circuit of the N divider For integer-n applications, the PFD can operate up to 90 MHz The reference divide-by-2 divides the reference signal by 2, resulting in a 50% duty cycle PFD frequency This is necessary for the correct operation of the cycle slip reduction (CSR) function For more information, see the Cycle Slip Reduction for Faster Lock Times section 2-BIT PROGRAMMABLE MODULUS The choice of modulus (MOD) depends on the reference signal (REF IN ) available and the channel resolution (f RES ) required at the RF output For example, a GSM system with 3 MHz REF IN sets the modulus to 65 This means that the RF output resolution (f RES ) is the 200 khz (3 MHz/65) necessary for GSM With dither off, the fractional spur interval depends on the selected modulus values (see Table 7) Unlike most other fractional-n PLLs, the allows the user to program the modulus over a 2-bit range When combined with the reference doubler and the 0-bit R counter, the 2-bit modulus allows the user to set up the part in many different configurations for the application For example, consider an application that requires a 75 GHz RF frequency output with a 200 khz channel step resolution The system has a 3 MHz reference signal One possible setup is to feed the 3 MHz reference signal directly into the PFD and to program the modulus to divide by 65 This results in the required 200 khz resolution Another possible setup is to use the reference doubler to create 26 MHz from the 3 MHz input signal The 26 MHz is then fed into the PFD, and the modulus is programmed to divide by 30 This setup also results in 200 khz resolution but offers superior phase noise performance over the first setup The programmable modulus is also very useful for multistandard applications For example, if a dual-mode phone requires PDC and GSM 800 standards, the programmable modulus is of great benefit PDC requires 25 khz channel step resolution, whereas GSM 800 requires 200 khz channel step resolution A 3 MHz reference signal can be fed directly to the PFD, and the modulus can be programmed to 520 when in PDC mode (3 MHz/520 = 25 khz) The modulus must be reprogrammed to 65 for GSM 800 operation (3 MHz/65 = 200 khz) Rev 0 Page 2 of 28