PERFORMANCE EVALUATION OF BOOTH AND WALLACE MULTIPLIER USING FIR FILTER 1 H. RAGHUNATHA RAO, T. ASHOK KUMAR & 3 N.SURESH BABU 1,&3 Department of Electroncs and Communcaton Engneerng, Chrala Engneerng College, Chrala. Abstract: An area-and speed effcent multplers s proposed n the thess. the proposed booth and Wallace multplers shows the tradeoff n the performance evaluaton for the fr flter applcatons. For mplementaton of fr flter n ths paper the adders ntroduced are carry save adder and carry skp adder. For evaluatng the fr flter performance the tested combnatons are booth carry save, booth carry skp, Wallace carry save, Wallace carry skp. Keywords: carry save adder, carry skp adder, booth and Wallace multpler. 1. INTRODUCTION The desgn of hgh-speed, area-effcent multplers s essental for VLSI mplementatons of dgtal sgnal processng systems.multplcaton are frequently requred n dgtal sgnal processng. Parallel multplers provde a hgh-speed method for multplcaton, but requre large area for VLSI mplementatons. In most sgnal processng applcatons, a product s desred to avod growth n word-sze. Thus, an mportant desgn goal s to reduce the area requrements of output multplers. Ths paper presents a technque for multplcaton whch computes the product of two numbers by summng the partal products. The domnant factors n the desgn of multplers for dgtal flters and other dgtal sgnal processng (DSP) applcatons are the chp area requred and the speed of operaton. Among the many classes of multplers, array multplers and multplers based on the Booth algorthm have been popular. In array multplers, multplcaton s effected by addng all the partal products generated by an array of ANDgate cells. In the past few years, sgnfcant reducton n the chp area as well as an assocated ncrease n the speed of operaton of these multplers have been acheved through ncreased devce densty by takng advantage of advancements n VLSI technology. Unfortunately, ths approach has reached a stage of dmnshng returns and further mprovements n the desgn of multplers wll occur only f major breakthroughs are acheved n the technology. In ths paper, we explore an alternatve approach to the desgn of area-effcent multplers for DSP applcatons, whch s ndependent of technology. Very often n these applcatons fxed-pont arthmetc s used and typcally N-bt sgnals are multpled by N-bt coeffcents. Two N-bt numbers to be multpled, A and B, and ther product P can be represented as A B P N 1 0 N 1 0 N 1 0 a b p N N N respectvely, where a,, b,, p, E (0, I}. In the standard N x N parallel multpler, the N bt products are generated smultaneously and are then added by an array of full adders, for an 8 x 8 multpler.. EVALUATION OF CARRY SAVE AND CARRY SKIP ADDERS A carry-save adder s a type of dgtal adder, used n computer mcro archtecture to compute the sum of three or more n-bt numbers n bnary. CSA conssts of a sequence of full adders, n whch one of the operands s entered n the carry nputs, and the carry outputs, nstead of feedng the carry nputs of the followng full adders, form a second output word whch s then added to the ordnary output n a two-operand adder to form the fnal sum. A carry-save adder s a knd of adder wth low propagaton delay (crtcal path), but nstead of addng two nput numbers to a sngle sum output, t adds three nput numbers to an output par of numbers. When ts two outputs are then summed by a tradtonal carry-look ahead or rpple-carry adder, we get the sum of all three nputs. When addng three or more numbers together, a sequence of carry-save adders termnated by a sngle carry-look ahead adder provdes much better propagaton delays than a sequence of carry-look ahead adders. 50
Performance Evaluaton of Booth and Wallace Multpler Usng FIR Flter In partcular, the propagaton delay of a carrysave adder s not affected by the wdth of the vectors beng added. The carry save adder can be vewed as follows.e. A dgtal adder Used to sum 3 or more bnary numbers Outputs two numbers of equal dmensons as the nput Advantages of Carry Save Adder Produces all of ts outputs n parallel resultng n the same delay as a full adder. Very lttle propagaton delay when mplemented. Allows for hgh clock speeds. Carry Skp Adder s an alternatve way of reducng the delay n the carry-chan of a RCA by checkng f a carry wll propagate through to the next block. Ths s called carry-skp adders. Fgure Reducng 3 operands to usng CSAs Probably the sngle most mportant advance n mprovng the speed of multplers, poneered by Wallace s the use of carry save adders (CSAs also known as combnaton of full adders and half adders or 3- counters), to add three or more numbers n a redundant and carry propagate free manner. The method s llustrated n Fgure. Fgure 1 Carry-Skp Adder. The carry-out of each block s determned by selectng the carry-n and G:j usng P:j. When P:j = 1, the carry-n cj s allowed to get through the block mmedately. Otherwse, the carry-out s determned by G:j. The CSKA has less delay n the carry-chan wth only a lttle addtonal extra logc. Further mprovement can be acheved generally by makng the central block szes larger and the two-end block szes smaller. Advantages of Carry Skp Adder Relatvely constant ncrease n performance. The performance and the consstency of the carry skp adder wll be excellent. There s no guaranteed wasted power. 3. WALLACE TREE MULTIPLIER The Wallace tree multpler wll use a set of adders to produce the fnal outputs. Carry propagate adds are relatvely slow, because of the long wres needed to propagate carres from low order bts to hgh order bts. By applyng the basc three nput adder n a recursve manner, any number of partal products can be added and reduced to numbers wthout a carry propagate adder. A sngle carry propagate addton s only needed n the fnal step to reduce the numbers to a sngle, fnal product. The general method can be appled to trees and lnear arrays alke to mprove the performance. Wallace Trees are combnatoral logc crcuts used to multply bnary ntegers. Constructed usng full adders and half adders, they are a fast, effcent method to mplement multplcaton. Integer multplcaton can be performed usng any of several methods. The tradtonal shft-add approach and ROM lookup tables are two methods used to mplement multplcaton, but each has ts drawbacks. The tme needed to calculate products usng the shftadd method ncreases lnearly as the number of bts n the operands ncreases, and the sze of the lookup ROM ncreases exponentally wth ncreases n the sze of the operands. Wallace Trees, whch use full and half adders to calculate partal results, resolve much of these problems wthout unduly ncreasng hardware requrements. Although t requres more hardware than shft-add multplers, t produces a product n far less tme. The advantages of the Wallace Tree Multpler are lsted as follows: Each layer of the tree reduces the number of vectors by a factor of 3: Mnmum propagaton delay. The beneft of the Wallace tree s that there are only O (log n) reducton layers, but addng partal products wth regular adders would requre O (log n) tmes. 51
Performance Evaluaton of Booth and Wallace Multpler Usng FIR Flter 4. BOOTH MULTIPLIER Booth's multplcaton algorthm s a multplcaton algorthm that multples two sgned bnary numbers n two's complement notaton. The algorthm was nvented by Andrew Donald Booth n 1950. Booth used desk calculators that were faster at shftng than addng and created the algorthm to ncrease ther speed[3]. Booth's algorthm s of nterest n the study of computer archtecture. Booth's algorthm examnes adjacent pars of bts of the N-bt multpler Y n sgned two's complement representaton. It ncludes an mplct bt below the least sgnfcant bt, y -1 = 0. For each bt y, for runnng from 0 to N-1, the bts y and y -1 are consdered. Where these two bts are equal, the product accumulator P remans unchanged. Where y = 0 and y -1 = 1, the multplcand tmes s added to P; and where y = 1 and y -1 = 0, the multplcand tmes s subtracted from P. The fnal value of P s the sgned product. The representaton of the multplcand and product are not specfed; typcally, these are both also n two's complement representaton, lke the multpler, but any number system that supports addton and subtracton wll work as well. Here, the order of the steps s not determned. Typcally, t proceeds from LSB to MSB, startng at = 0; the multplcaton by s then typcally replaced by ncremental shftng of the P accumulator to the rght between steps; low bts can be shfted out, and subsequent addtons and subtractons can then be done just on the hghest N bts of P. There are many varatons and optmzatons on these detals. Booth's algorthm can be mplemented by repeatedly addng (wth ordnary unsgned bnary addton) one of two predetermned values A and S to a product P, then performng a rghtward arthmetc shft on P. Let m and r be the multplcand and multpler, respectvely; and let x and y represent the number of bts n m and r. Determne the values of A and S, and the ntal value of P. All of these numbers should have a length equal to (x + y + 1). A: Fll the most sgnfcant (leftmost) bts wth the value of m. Fll the remanng (y + 1) bts wth zeros. S: Fll the most sgnfcant bts wth the value of ( m) n two's complement notaton. Fll the remanng (y + 1) bts wth zeros. P: Fll the most sgnfcant x bts wth zeros. To the rght of ths, append the value of r. Fll the least sgnfcant (rghtmost) bt wth a zero. Determne the two least sgnfcant (rghtmost) bts of P. If they are 01, fnd the value of P + A. Ignore any overflow. If they are 10, fnd the value of P + S. Ignore any overflow. If they are 00, do nothng. Use P drectly n the next step. If they are 11, do nothng. Use P drectly n the next step. Arthmetcally shft the value obtaned n the nd step by a sngle place to the rght. Let P now equal ths new value. Repeat steps and 3 untl they have been done y tmes. Drop the least sgnfcant (rghtmost) bt from P. Ths s the product of m and r. The Booth and wallance waveforms are as shown n Fgure 3 and Fgure 4. 5. CONCLUSION By the results we can conclude that Wallace multpler s area and speed effcent than booth multpler and booth multpler s power effcent. Compared wth the exstng works, the proposed methods has better area power and speed effcent. Trade off s there between the speed, power and area depend on the applcatons. Fgure 3 Wallace Waveform Fgure 4 Booth Waveform Fgure 5 RTL Schematc for Booths Multpler 5
Performance Evaluaton of Booth and Wallace Multpler Usng FIR Flter Fgure 6 Technology Schematc Fgure 10 Desgn Summary of Wallace tree multpler Fgure 7 Desgn Summary of Booths Multpler Fgure 11 FIR Implementaton usng Booth Multplers Fgure 8 RTL Schematc of Wallace Tree Multpler Fgure 1 FIR Implementaton usng Wallace Multplers Table 1 Comparson report Fgure 9 Technology Schematc of Wallace Tree Multpler TIMING REPORT POWER MEMORY FIR_BOOTH_MUL_CARRY_SAVE 77.446 ns 3mw 80.51 MB FIR_BOOTH_MUL_CARRY_SKIP 57.18ns 18mw 35.14MB FIR_WALLACE_MUL_CARRY_SAVE 50.503ns 8mw 75.0MB FIR_WALLACE_MUL_CARRY_SKIP 34.884ns 4mw 86.08MB 53
Performance Evaluaton of Booth and Wallace Multpler Usng FIR Flter ACKNOWLEDGEMENTS The authors would lke to thank the anonymous revewers for ther comments whch were very helpful n mprovng the qualty and presentaton of ths paper. Authors Profle: H.Raghunatha Rao s pursung M.Tech n VLSI &ES at Chrala Engneerng College,Chrala. REFERENCES: [1] J. M. Jou, S. R. Kuang, and R. D. Chen, Desgn of lowererror fxedwdth multplers for DSP applcatons, IEEE Trans. Crcuts Syst. II, Analog Dgt. Sgnal Process, vol. 46, no. 6, pp. 836 84, Jun. 1999. [] L. D. Van, S. S. Wang, and W. S. Feng, Desgn of the lower-error fxedwdth multpler and ts applcaton, IEEE Trans. Crcuts Syst. II, Analog Dgt. Sgnal Process, vol. 47, no. 10, pp. 111 1118, Oct. 000. [3] L. D. Van and C. C. Yang, Generalzed low-error areaeffcent fxedwdth multplers, IEEE Trans. Crcuts Syst. I, Reg. Papers, vol. 5, no. 8, pp. 1608 1619, Aug. 005. [4] Y. C. Lao, H. C. Chang, and C. W. Lu, Carry estmaton for two s complement fxed-wdth multplers, n Proc. IEEE Workshop on Sgnal Process. Syst. Desgn Implementaton, 006, pp. 345 350. [5] N. Petra, D. D. Caro, V. Garofalo, E. Napol, and A. G. M. Strollo, Truncated bnary multplers wth varable correcton and mnmum mean square error, IEEE Trans. Crcuts Syst. I, Reg. Papers, vol. 57, no. 6, pp. 131 135, Jun. 010. T.Ashok kumar s Workng as Assoc.prof n ECE Dept. CEC,Chrala.He was Awarded wth M.Tech n CSE from Anna Unversty He has over 5 year teachng Experence. Prof.N.Suresh Babu s Vce- Prncpal & HOD of ECE Dept n CEC,Chrala.He got hs M.Tech n Mcrowave Engneerng from Brla Innsttute of technology, Ranch. He has 13 years of teachng Experence and Years of Industral Experence n varous organsatons. [6] S. J. Jou, M. H. Tsa, and Y. L. Tsao, Low-error reducedwdth Booth multplers for DSP applcatons, IEEE Trans. Crcuts Syst. I, Fundam. Theory Appl., vol. 50, no. 11, pp. 1470 1474, Nov. 003. [7] K. J. Cho, K. C. Lee, J. G. Chung, and K. K. Parh, Desgn of low-error fxed-wdth modfed Booth multpler, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 1, no. 5, pp. 5 531, May 004. [8] K. J. Cho, K. C. Lee, J. G. Chung, and K. K. Parh, Desgn of low-error fxed-wdth modfed Booth multpler, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 1, no. 5, pp. 5 531, May 004. [9] T. B. Juang and S. F. Hsao, Low-error carry-free fxedwdth multplers wth low-cost compensaton crcuts, IEEE Trans. Crcuts Syst. II, Exp. Brefs, vol. 5, no. 6, pp. 99 303, Jun. 005. [10] K. K. Parh, J. G. Chung, K. C. Lee, and K. J. Cho, Lowerror fxed-wdth modfed Booth multpler, U.S. Patent 7 334 00, Feb. 19, 008. [11] H. A. Huang, Y. C. Lao, and H. C. Chang, A selfcompensaton fxedwdth Booth multpler and ts 18-pont FFT applcatons, n Proc. IEEE ISCAS, 006, pp. 3538 3541. [1] J. P. Wang, S. R. Kuang, and S. C. Lang, Hgh-accuracy fxedwdth modfed Booth multplers for lossy applcatons, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 19, no. 1, pp. 5 60, Jan. 011. 54