Lab Experiments L Power diode V g C Power MOSFET Load Boost converter (Experiment 2) V ref PWM chip UC3525A Gate driver TSC427 Control circuit (Experiment 1) Adjust duty cycle D
The UC3525 PWM Control IC Key functions: Oscillator (sawtooth wave generator) PWM comparator and latch Error amplifier 5.1 V reference Pulse-steering logic Output drivers Shutdown and softstart circuitry oratory
How a pulse-width modulator works V M v saw (t) Sawtooth wave v saw (t) v c (t) generator analog input v c (t) comparator δ(t) PWM waveform 0 δ(t) t 0 dt s T s 2T s oratory
Equation of pulse-width modulator For a linear sawtooth waveform: d(t)= v c(t) V M for 0 v c (t) V M V M v c (t) v saw (t) So d(t) is a linear function of v c (t). 0 δ(t) t T s 0 dt s 2T s oratory
oratory Sawtooth (Ramp) Oscillator
Simplified Block Diagram of Oscillator 5.1 V Reference V ref 7.4 kω i T = C T dv T dt hence dv T dt = i T C T I Current mirror 6 5 R D R T C T i T I v T 7 Comparator Sawtooth (Ramp) signal v T 2 kω 14 kω Blanking pulse v T V max V min I /C T Charge interval t C I charges C T Discharge interval t D R D discharges C T V M = V max V min UC3525 Oscillator section Switching period T s I = (5.1 V) 2(0.7 V) R T V max = (5.1 V) 14 kω 14 kω 7.4 kω = 3.3 V V min = (5.1 V) 2kΩ 14 kω 2kΩ 14 kω 7.4 kω = 1.0 V Blanking pulse causes driver outputs to be low, so that dt s t c Increasing R D reduces maximum allowed duty cycle D max oratory
Error Amplifier 1 2 g m 9 to PWM comparator _ v 1 model: _ 1 i 9 9 Transconductance amplifier v 2 2 g m (v 2 - v 1 )
Error Amplifier with Load v 1 1 _ i 9 9 v 2 2 g m (v 2 - v 1 ) Z(s) v9 = gmz( s)( v2 v1) The differential voltage gain is: g m Z(s) With large Z(s), the differential voltage gain is large. The data sheet specifies a low-frequency differential voltage gain of at least 1000 (60 db).
Connect to produce adjustable D pin 16 V ref 1 9 v comp v in 2 g m to PWM comparator internal Z(s) external pot The error amplifier is connected as a unity-gain stage: v comp = v in The duty cycle D can be adjusted by the external pot.
Outputs of the UC3515A 13 V C flip-flop output Q output A flip-flop output Q output B 11 14 output of PWM comparator Output of PWM comparator Flip-flop output Q Flip-flop output Q DT s T s Frequency of the outputs is one half the oscillator frequency. Duty cycle cannot be greater than 50%. Output A Output B Such outputs are needed in some types of switching converters such as push-pull. Outputs A and B can be OR-ed to restore the PWM pulses at the oscillator frequency.
Driving a Power MOSFET Switch MOSFET is off when v gs < V th 2.5 V Gate Drain C gd ~ 30 pf Gate Drain C ds ~ 1 nf MOSFET fully on when v gs is sufficiently large (10-15 V) Warning: MOSFET gate oxide breaks down and the device fails when v gs > 20 V. v gs _ Source C gs ~ 3 nf Source Fast turn on or turn off (10 s of ns) requires a large spike (1-2 A) of gate current to charge or discharge the gate capacitance Power MOSFET MOSFET capacitances MOSFET gate driver is a logic buffer that has high output current capability
Driving a Power MOSFET Switch V CC PWM pulses from UC3525A decoupling C TSC427 10 Ω Gate rest of the converter circuit Drain Source Gate driver MOSFET gate driver is used as a logic buffer with high output current (1.5 A) capability The amplitude of the gate voltage equals the supply voltage V CC Decoupling capacitors are necessary at all supply pins of UC3525A and TSC427
1 Experiment 1 Pulse-Width Modulator PRELAB ASSIGNMENT ECEN 4517 / 5017 In the laboratory, you are going to construct a pulse-width modulator (PWM) circuit, test operation of the UC3525A PWM chip, and the TSC427 gate driver chip. The purpose of the prelab assignment is to familiarize yourself with these integrated circuits, understand their data sheets, and design the basic control circuitry that you will use in later experiments. For the prelab assignment, do the following: 1. Reading assignment: Introduction to converters handout Data sheets for the UC3525A PWM chip and the TSC427 power MOSFET driver chip Laboratory procedure handout All of the above materials can be downloaded from the course web site 2. Circuit design: Design a circuit around the UC3525A and TSC427 such that the gate drive signal at the output of the TSC427 is a PWM waveform having switching frequency f s equal to 50 khz, and duty ratio D adjustable between 0 and 40%. The maximum duty cycle should be limited to 40% by your design. Your circuit should include bypass capacitors at the power supply pins of all chips. A DC supply voltage of V CC = 15 V is available. You may use an adjustable trimmer potentiometer for duty cycle adjustments, and as many resistors and capacitors as necessary around the chips. You should turn in a complete circuit diagram with all component names and values. For each component, not how you selected the value, referring to the UC3525A data sheet as necessary. A separate prelab assignment is required from each student. The prelab should be turned in at the beginning of the week 2 lecture. Keep a copy of your work, for your use during the lab experiment.