Ultra Low Power/High Speed CMOS SRAM 512K X 16 bit Pb-Free and Green package materials are compliant to RoHS BH616UV8010 FEATURES Wide low operation voltage : 165V ~ 36V Ultra low power consumption : = 36V Operation current : 12mA (Max)at 55ns 2mA (Max) at 1MHz Standby current : 25uA (Typ) at 30V/25 O C = 12V Data retention current : 12uA (Typ) at 25 O C High speed access time : -55 55ns (Max) at =165~36V -70 70ns (Max) at =165~36V Automatic power down when chip is deselected Easy expansion with, and OE options I/O Configuration x8/x16 selectable by LB and UB pin Three state outputs and TTL compatible Fully static operation, no clock, no refresh Data retention supply voltage as low as 10V DESCRIPTION The BH616UV8010 is a high performance, ultra low power CMOS Static Random Access Memory organized as 524,288 by 16 bits and operates in a wide range of 165V to 36V supply voltage Advanced CMOS technology and circuit techniques provide both high speed and low power features with typical operating current of 15mA at 1MHz at 36V/25 O C and maximum access time of 55ns at 165V/85 O C Easy memory expansion is provided by an active LOW chip enable (), an active HIGH chip enable () and active LOW output enable (OE) and three-state output drivers The BH616UV8010 has an automatic power down feature, reducing the power consumption significantly when chip is deselected The BH616UV8010 is available in DICE form, JEDEC standard 48-pin TSOP-I and 48-ball BGA package POWER CONSUMPTION PRODUCT FAMILY OPERATING TEMPERATURE STANDBY (ICCSB1, Max) =36V =18V POWER DISSIPATION Operating (ICC, Max) =36V =18V 1MHz 10MHz f Max 1MHz 10MHz f Max PKG TYPE BH616UV8010DI DICE BH616UV8010AI Industrial -40 O C to +85 O C 15uA 12uA 2mA 6mA 12mA 15mA 5mA 8mA BGA-48-0608 BH616UV8010TI TSOP I-48 PIN CONFIGURATIONS BLOCK DIAGRAM A15 A14 A13 A12 A11 A10 A9 A8 WE UB LB A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 BH616UV8010TI 1 2 3 4 5 6 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE A0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 DQ0 DQ15 Address Input Buffer 16 16 10 Row Decoder Data Input Buffer Data Output Buffer 16 16 1024 Memory Array 1024 x 8192 Column I/O 8192 Write Driver Sense Amp 512 Column Decoder A B C LB DQ8 DQ9 OE UB DQ10 A0 A3 A5 A1 A2 A4 DQ0 A6 DQ1 DQ2 WE OE UB LB Control 9 Address Input Buffer A18 A17 A15 A14 A13 A16 A2 A1 A0 D DQ11 A17 A7 DQ3 VCC VCC E VCC DQ12 A16 DQ4 F DQ14 DQ13 A14 A15 DQ5 DQ6 G DQ15 A12 A13 WE DQ7 H A18 A8 A9 A10 A11 48-ball BGA top view Brilliance Semiconductor, Inc reserves the right to change products and specifications without notice Detailed product characteristic test report is available upon request and being accepted R0201-BH616UV8010 1 Revision 12 May 2006
PIN DESCRIPTIONS Name A0-A18 Address Input Function These 19 address inputs select one of the 524,288 x 16 bit in the RAM Chip Enable 1 Input Chip Enable 2 Input WE Write Enable Input OE Output Enable Input LB and UB Data Byte Control Input is active LOW and is active HIGH Both chip enables must be active when data read from or write to the device If either chip enable is not active, the device is deselected and is in standby power mode The DQ pins will be in the high impedance state when the device is deselected The write enable input is active LOW and controls read and write operations With the chip selected, when WE is HIGH and OE is LOW, output data will be present on the DQ pins; when WE is LOW, the data present on the DQ pins will be written into the selected memory location The output enable input is active LOW If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled The DQ pins will be in the high impendence state when OE is inactive Lower byte and upper byte data input/output control pins DQ0-DQ15 Data Input/Output Ports 16 bi-directional ports are used to read data from or write data into the RAM Power Supply V SS Ground TRUTH TABLE MODE WE OE LB UB DQ0~DQ7 DQ8~DQ15 CURRENT Chip De-selected (Power Down) H X X X X X High Z High Z I CCSB, I CCSB1 X L X X X X High Z High Z I CCSB, I CCSB1 X X X X H H High Z High Z I CCSB, I CCSB1 Output Disabled L H H H L X High Z High Z I CC L H H H X L High Z High Z I CC L L D OUT D OUT I CC Read L H H L H L High Z D OUT I CC L H D OUT High Z I CC L L D IN D IN I CC Write L H L X H L X D IN I CC L H D IN X I CC NOTES: H means V IH; L means V IL; X means don t care (Must be V IH or V IL state) R0201-BH616UV8010 2 Revision 12 May 2006
ABSOLUTE MAXIMUM RATINGS (1) SYMBOL PARAMETER RATING UNITS V TERM T BIAS Terminal Voltage with Respect to GND Temperature Under Bias -05 (2) to 46V V -40 to +125 O C OPERATING RANGE RANG AMBIENT TEMPERATURE Industrial -40 O C to + 85 O C 165V ~ 36V T STG Storage Temperature -60 to +150 O C CAPACITAE (1) (T A = 25 O C, f = 10MHz) P T Power Dissipation 10 W I OUT DC Output Current 20 ma 1 Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect reliability 2 20V in case of AC pulse width less than 30 ns SYMBOL PAMAMETER CONDITIONS MAX UNITS C IN C IO Input Capacitance Input/Output Capacitance V IN = 0V 6 pf V I/O = 0V 8 pf 1 This parameter is guaranteed and not 100% tested DC ELECTRICAL CHARACTERISTICS (T A = -40 O C to +85 O C) PARAMETER NAME PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNITS Power Supply 165 -- 36 V V IL V IH I IL I LO V OL V OH I CC I CC1 I CCSB I CCSB1 Input Low Voltage Input High Voltage Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage Operating Power Supply Current Operating Power Supply Current Standby Current TTL Standby Current CMOS VCC=18V 04 VCC=36V VCC=18V 14 VCC=36V 22-03 (2) -- 06 V -- +03 (3) V V IN = 0V to, = V IH or = V IL -- -- 1 ua V I/O = 0V to, = V IH or = V IL or OE = V IH or -- -- 1 ua UB = LB = V IH = Max, I OL = 02mA VCC=18V 02 -- -- = Max, I OL = 20mA 04 VCC=36V = Min, I OH = -01mA VCC=18V -02 -- -- V = Min, I OH = -10mA VCC=36V 24 = V IL and = V IH, (4) I DQ = 0mA, f = F MAX = V IL and = V IH, I DQ = 0mA, f = 1MHz = V IH, or = V IL, I DQ = 0mA -02V or 02V, V IN -02V or V IN 02V VCC=18V 6 8 -- 8 12 VCC=36V VCC=18V 10 15 -- 15 20 VCC=36V VCC=18V 05 VCC=36V -- -- 10 VCC=18V 20 12 -- 25 (5) 15 VCC=36V V ma ma ma ua 1 Typical characteristics are at T A=25 O C and not 100% tested 2 Undershoot: -10V in case of pulse width less than 20 ns 3 Overshoot: +10V in case of pulse width less than 20 ns 4 F MAX=1/t RC 5 =30V R0201-BH616UV8010 3 Revision 12 May 2006
DATA RETENTION CHARACTERISTICS (T A = -40 O C to +85 O C) SYMBOL PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNITS V DR for Data Retention -02V or 02V, VIN -02V or VIN 02V 10 -- -- V I CCDR Data Retention Current -02V or 02V, VIN -02V or VIN 02V VCC=12V -- 12 70 ua t CDR t R Chip Deselect to Data Retention Time Operation Recovery Time See Retention Waveform 0 -- -- ns t RC (2) -- -- ns 1 Typical characteristics are at T A=25 O C and not 100% tested 2 t RC = Read Cycle Time LOW DATA RETENTION WAVEFORM (1) ( Controlled) Data Retention Mode t CDR V DR 10V t R V IH - 02V V IH LOW DATA RETENTION WAVEFORM (2) ( Controlled) Data Retention Mode V DR 10V t CDR t R V IL 02V V IL AC TEST CONDITIONS (Test Load and Input/Output Reference) KEY TO SWITCHING WAVEFORMS Input Pulse Levels / 0V WAVEFORM INPUTS OUTPUTS Input Rise and Fall Times Input and Output Timing Reference Level t CLZ1, t CLZ2, t BE, t OLZ, t CHZ1, Output Load t CHZ2, t BDO, t OHZ, t WHZ, t OW Others Output 1 TTL C L (1) GND 1 Including jig and scope capacitance 10% 1V/ns 05Vcc C L = 5pF+1TTL C L = 30pF+1TTL ALL INPUT PULSES 90% Rise Time: 1V/ns 90% 10% Fall Time: 1V/ns MUST BE STEADY MAY CHANGE FROM H TO L MAY CHANGE FROM L TO H DON T CARE ANY CHANGE PERMITTED DOES NOT APPLY MUST BE STEADY WILL BE CHANGE FROM H TO L WILL BE CHANGE FROM L TO H CHANGE : STATE UNKNOW CENTER LINE IS HIGH INPEDAE OFF STATE R0201-BH616UV8010 4 Revision 12 May 2006
AC ELECTRICAL CHARACTERISTICS (T A = -40 O C to +85 O C) READ CYCLE JEDEC PARAMETER NAME PARANETER NAME DESCRIPTION CYCLE TIME : 55ns CYCLE TIME : 70ns MIN TYP MAX MIN TYP MAX UNITS t AVAX t RC Read Cycle Time 55 -- -- 70 -- -- ns t AVQX t AA Address Access Time -- -- 55 -- -- 70 ns t E1LQV t ACS1 Chip Select Access Time () -- -- 55 -- -- 70 ns t E2LQV t ACS2 Chip Select Access Time () -- -- 55 -- -- 70 ns t BLQV t BA Data Byte Control Access Time (LB, UB) -- -- 55 -- -- 70 ns t GLQV t OE Output Enable to Output Valid -- -- 30 -- -- 35 ns t E1LQX t CLZ1 Chip Select to Output Low Z () 10 -- -- 10 -- -- ns t E2LQX t CLZ2 Chip Select to Output Low Z () 10 -- -- 10 -- -- ns t BLQX t BE Data Byte Control to Output Low Z (LB, UB) 10 -- -- 10 -- -- ns t GLQX t OLZ Output Enable to Output Low Z 5 -- -- 5 -- -- ns t E1HQZ t CHZ1 Chip Select to Output High Z () -- -- 25 -- -- 30 ns t E2HQZ t CHZ2 Chip Select to Output High Z () -- -- 25 -- -- 30 ns t BHQZ t BDO Data Byte Control to Output High Z (LB, UB) -- -- 25 -- -- 30 ns t GHQZ t OHZ Output Enable to Output High Z -- -- 25 -- -- 30 ns t AVQX t OH Data Hold from Address Change 10 -- -- 10 -- -- ns SWITCHING WAVEFORMS (READ CYCLE) READ CYCLE 1 (1,2,4) ADDRESS t RC t OH t AA t OH D OUT R0201-BH616UV8010 5 Revision 12 May 2006
READ CYCLE 2 (1,3,4) t ACS1 D OUT t CLZ (5,6) t ACS2 (6) t CHZ (5, 6) READ CYCLE 3 (1, 4) t RC ADDRESS t AA OE t OE t OH LB, UB t OLZ t CLZ1 (5) t ACS1 t ACS2 (5) t CLZ2 t BA (5) t OHZ (1,5) t CHZ t CHZ2 (2,5) t BE t BDO D OUT NOTES: 1 WE is high in read Cycle 2 Device is continuously selected when = V IL and = V IH 3 Address valid prior to or coincident with transition low and/or transition high 4 OE = V IL 5 Transition is measured ± 500mV from steady state with C L = 5pF The parameter is guaranteed but not 100% tested R0201-BH616UV8010 6 Revision 12 May 2006
AC ELECTRICAL CHARACTERISTICS (T A = -40 O C to +85 O C) WRITE CYCLE JEDEC PARAMETER NAME PARANETER NAME DESCRIPTION CYCLE TIME : 55ns CYCLE TIME : 70ns MIN TYP MAX MIN TYP MAX UNITS t AVAX t WC Write Cycle Time 55 -- -- 70 -- -- ns t AVWL t AS Address Set up Time 0 -- -- 0 -- -- ns t AVWH t AW Address Valid to End of Write 45 -- -- 60 -- -- ns t ELWH t CW Chip Select to End of Write 45 -- -- 60 -- -- ns t BLWH t BW Data Byte Control to End of Write (LB, UB) 45 -- -- 60 -- -- ns t WLWH t WP Write Pulse Width 35 -- -- 35 -- -- ns t WHAX t WR1 Write Recovery Time (, WE) 0 -- -- 0 -- -- ns t E2LAX t WR2 Write Recovery Time () 0 -- -- 0 -- -- ns t WLQZ t WHZ Write to Output High Z -- -- 20 -- -- 25 ns t DVWH t DW Data to Write Time Overlap 25 -- -- 30 -- -- ns t WHDX t DH Data Hold from Write Time 0 -- -- 0 -- -- ns t GHQZ t OHZ Output Disable to Output in High Z -- -- 25 -- -- 30 ns t WHQX t OW End of Write to Output Active 5 -- -- 5 -- -- ns SWITCHING WAVEFORMS (WRITE CYCLE) WRITE CYCLE 1 (1) ADDRESS t WC OE (5) t CW (11) t WR1 (3) (5) LB, UB t CW (11) t BW t WR2 (3) WE t AS t AW t WP (2) t OHZ (4,10) D OUT t DH t DW D IN R0201-BH616UV8010 7 Revision 12 May 2006
WRITE CYCLE 2 (1,6) t WC ADDRESS (5) t CW (11) (5) LB, UB (12) t CW (11) t BW t WR (3) WE t AS t AW t WHZ (4,10) t WP (2) t OW (7) (8) D OUT t DW t DH (8,9) D IN NOTES: 1 WE must be high during address transitions 2 The internal write time of the memory is defined by the overlap of and active and WE low All signals must be active to initiate a write and any one signal can terminate a write by going inactive The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write 3 t WR is measured from the earlier of or WE going high or going low at the end of write cycle 4 During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied 5 If the low transition or the high transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state 6 OE is continuously low (OE = V IL) 7 D OUT is the same phase of write data of this write cycle 8 D OUT is the read data of next address 9 If is low and is high during this period, DQ pins are in the output state Then the data input signals of opposite phase to the outputs must not be applied to them 10 Transition is measured ± 500mV from steady state with C L = 5pF The parameter is guaranteed but not 100% tested 11 t CW is measured from the later of going low or going high to the end of write R0201-BH616UV8010 8 Revision 12 May 2006
ORDERING INFORMATION BH616UV8010 X X Z Y Y SPEED 55: 55ns 70: 70ns PKG MATERIAL -: Normal G: Green, RoHS Compliant P: Pb free, RoHS Compliant GRADE I: -40 o C ~ +85 o C PACKAGE D: DICE A: BGA-48-0608 T: TSOP I-48 Note: Brilliance Semiconductor Inc (BSI) assumes no responsibility for the application or use of any product or circuit described herein BSI does not authorize its products for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support systems and critical medical instruments PACKAGE DIMENSIONS NOTES: 1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS 2: PIN#1 DOT MARKING BY LASER OR PAD PRINT 3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS 12 Max BALL PITCH e = 075 D E N D1 E1 80 60 48 525 375 D1 E1 e VIEW A 48 mini-bga (6 x 8) R0201-BH616UV8010 9 Revision 12 May 2006
PACKAGE DIMENSIONS TSOP I-48 Pin (12mm x 20mm) R0201-BH616UV8010 10 Revision 12 May 2006
Revision History Revision No History Draft Date Remark 10 Initial Production Version July 15,2005 Initial 11 To improve access speed Dec 23, 2005 - from 70ns to 55ns 12 Change I-grade operation temperature range May 25, 2006 - from 25 O C to 40 O C R0201-BH616UV8010 11 Revision 12 May 2006