All Devices Discontinued!

isplsi 3320 Device Datasheet June 200 All Devices Discontinued! Product Change Notification (PCN) #09-0 has been issued to discontinue all devices in this data sheet. The original datasheet pages have not been modified and do not reflect those changes. Please refer to the table below for reference PCN and current product status. Product Line Ordering Part Number Product Status Reference PCN isplsi 3320 isplsi 3320-70LQ isplsi 3320-00LQ isplsi 3320-70LB320 Discontinued PCN#09-0 isplsi 3320-00LB320 5555 N.E. Moore Ct. Hillsboro, Oregon 9724-642 Phone (503) 268-8000 FAX (503) 268-8347 Internet: http://www.latticesemi.com

Features HIGH-DENSITY PROGRAMMABLE LOGIC 60 Pins 4000 PLD Gates 480 Registers High Speed Global Interconnect Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. Small Logic Block Size for Random Logic HIGH-PERFORMANCE E 2 CMOS TECHNOLOGY fmax = 00 MHz Maximum Operating Frequency tpd = 0 ns Propagation Delay TTL Compatible Inputs and Outputs Electrically Erasable and Reprogrammable Non-Volatile 00% Tested at Time of Manufacture Unused Product Term Shutdown Saves Power isplsi FEATURES: 5V In-System Programmable (ISP ) Using Lattice ISP or Boundary Scan Test (IEEE 49.) Protocol Increased Manufacturing Yields, Reduced Time-to- Market, and Improved Product Quality Reprogram Soldered Devices for Faster Debugging 00% IEEE 49. BOUNDARY SCAN COMPATIBLE OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS Complete Programmable Device Can Combine Glue Logic and Structured Designs Enhanced Pin Locking Capability Five Dedicated Clock Input Pins Synchronous and Asynchronous Clocks Programmable Output Slew Rate Control to Minimize Switching Noise Flexible Pin Placement Optimized Global Routing Pool Provides Global Interconnectivity Pin Compatible with isplsi 360 ispdesignexpert LOGIC COMPILER AND COM- PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING Superior Quality of Results Tightly Integrated with Leading CAE Vendor Tools Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispanalyzer PC and UNIX Platforms isplsi 3320 In-System Programmable High Density PLD Functional Block Diagram Boundary Scan H0 H H2 H3 I0 I I2 I3 J0 J J2 J3 Description G3 G2 G G0 A0 A A2 A3 Global Routing Pool (GRP) F3 F2 F F0 AND Array OR Array OR Array Twin GLB B0 B B2 B3 E3 E2 E E0 D3 D2 D D0 C3 C2 C C0 039/3320 The isplsi 3320 is a High-Density Programmable Logic Device containing 480 Registers, 60 Universal pins, five Dedicated Clock Input Pins, ten Output Routing Pools (ORP) and a Global Routing Pool (GRP) which allows complete inter-connectivity between all of these elements. The isplsi 3320 features 5V in-system programmability and in-system diagnostic capabilities. The isplsi 3320 offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. The basic unit of logic on the isplsi 3320 device is the Twin Generic Logic Block (Twin GLB) labelled A0, A...J3. There are a total of 40 of these Twin GLBs in the isplsi 3320 device. Each Twin GLB has 24 inputs, a programmable AND array and two OR/Exclusive-OR Arrays, and eight outputs which can be configured to be either combinatorial or registered. All Twin GLB inputs come from the GRP. Copyright 2003 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 9724, U.S.A. December 2003 Tel. (503) 268-8000; -800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com 3320_07

Functional Block Diagram Figure. isplsi 3320 Functional Block Diagram GOE0 GOE 59 58 57 56 55 54 53 52 5 50 49 48 47 46 45 44 43 42 4 40 39 38 37 36 35 34 33 32 3 30 29 28 27 26 25 24 23 22 2 20 9 8 7 6 5 4 3 2 BSCAN/ispEN TCK/SCLK TMS/MODE TOE 0 2 3 4 5 6 7 8 9 0 2 3 4 5 6 7 8 9 20 2 22 23 24 25 26 27 28 29 30 3 RESET A0 A A2 A3 B0 B B2 B3 J3 J2 J J0 C0 C C2 C3 32 33 34 35 36 37 38 39 40 4 42 43 44 45 46 47 I3 I2 I I0 Global Routing Pool (GRP) D0 D D2 D3 48 49 50 5 52 53 54 55 56 57 58 59 60 6 62 63 H3 H2 H H0 E0 E E2 E3 64 65 66 67 68 69 70 7 72 73 74 75 76 77 78 79 Boundary Scan G3 G2 G G0 F3 F2 F F0 CLK 0 CLK CLK 2 IOCLK IOCLK 0 Y0 Y Y2 Y3 Y4 TDI/SDI TRST TDO/SDO 0 09 08 07 06 05 04 03 02 0 00 99 98 97 96 95 94 93 92 9 90 89 88 87 86 85 84 83 82 8 80 039/3320 2

Description (continued) All local logic block outputs are brought back into the GRP so they can be connected to the inputs of any other logic block on the device. The device also has 60 cells, each of which is directly connected to an pin. Each cell can be individually programmed to be a combinatorial input, a registered input, a latched input, an output or a bidirectional pin with 3-state control. The signal levels are TTL compatible voltages and the output drivers can source 4 ma or sink 8 ma. Each output can be programmed independently for fast or slow output slew rate to minimize overall output switching noise. The 60 cells are grouped into ten sets of 6 bits. Each of these groups is associated with a logic Megablock through the use of the ORP. Each Megablock is able to provide one Product Term Output Enable (PTOE) signal which is globally distributed to all cells. That PTOE signal can be generated within any GLB in the Megablock. Each cell can select one of 2 available OEs (two Global OEs and ten PTOEs). Four Twin GLBs, 6 cells and one ORP are connected together to make a logic Megablock. The Megablock is defined by the resources that it shares. The outputs of the four Twin GLBs are connected to a set of 6 cells by the ORP. The isplsi 3320 Device contains ten of these Megablocks. The GRP has as its inputs the outputs from all of the Twin GLBs and all of the inputs from the bidirectional cells. All of these signals are made available to the inputs of the Twin GLBs. Delays through the GRP have been equalized to minimize timing skew and logic glitching. Clocks in the isplsi 3320 device are provided through five dedicated clock pins. The five pins provide three clocks to the Twin GLBs and two clocks to the cells. The table below lists key attributes of the device along with the number of resources available. An additional feature of the isplsi 3320 is the Boundary Scan capability, which is composed of cells connected between the on-chip system logic and the device s input and output pins. All pins have associated boundary scan registers, with 3-state using three boundary scan registers and inputs using one. The isplsi 3320 supports all IEEE 49. mandatory instructions, which include BYPASS, EXTEST and SAMPLE. Key Attributes of the isplsi 3320 Attribute Twin GLBs Registers Pins Global Clocks Global OE Test OE Quantity 40 480 60 5 2 Table -0003/3320 3

Absolute Maximum Ratings Supply Voltage V cc... -0.5 to +7.0V Input Voltage Applied... -2.5 to V CC +.0V Off-State Output Voltage Applied... -2.5 to V CC +.0V Storage Temperature... -65 to 50 C Case Temp. with Power Applied... -55 to 25 C Max. Junction Temp. (T J ) with Power Applied (208-Pin PQFP)... 50 C Max. Junction Temp. (T J ) with Power Applied (320-Ball BGA)... 40 C. Stresses above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). DC Recommended Operating Condition SYMBOL PARAMETER MIN. MAX. UNITS TA Ambient Temperature 0 70 C Supply Voltage 4.75 5.25 V VIL Input Low Voltage 0 0.8 V VIH Input High Voltage 2.0 V CC + V Capacitance (T A =25 C,f=.0 MHz) SYMBOL PARAMETER TYPICAL UNITS TEST CONDITIONS C Capacitance 0 pf V CC= 5.0V, V = 2.0V C2 Clock Capacitance pf V CC= 5.0V, V Y = 2.0V Data Retention Specifications Data Retention PARAMETER isplsi Erase/Reprogram Cycles MINIMUM MAXIMUM UNITS 20 Years 0000 Cycles Table 2-0005/3320 Table 2-0006/3320 Table 2-0008/3320 4

Switching Test Conditions Input Pulse Levels to 3.0V Input Rise and Fall Time 3 ns 0% to 90% Input Timing Reference Levels.5V Output Timing Reference Levels.5V Output Load See Figure 2 3-state levels are measured 0.5V from steady-state active level. Output Load conditions (See Figure 2) Table 2-0003/3320 TEST CONDITION R R2 CL A 470Ω 390Ω 35pF B Active High 390Ω 35pF Active Low 470Ω 390Ω 35pF C Active High to Z at V OH-0.5V 390Ω 5pF Active Low to Z at V +0.5V 470Ω 390Ω 5pF OL DC Electrical Characteristics Table 2-0004A Figure 2. Test Load Device Output + 5V R R2 CL* *CL includes Test Fixture and Probe Capacitance. Over Recommended Operating Conditions SYMBOL PARAMETER CONDITION MIN. 3 TYP. MAX. UNITS VOL Output Low Voltage I OL = 8 ma 0.4 V VOH Output High Voltage I OH = -4 ma 2.4 V IIL Input or Low Leakage Current 0V V IN V IL (Max.) -0 µa IIH Input or High Leakage Current 3.5V V IN 0 µa IIL-isp ispen Input Low Leakage Current 0V V IN VIL -50 µa IIL-PU Active Pull-Up Current 0V V IN VIL -50 µa IOS Output Short Circuit Current V CC = 5V, V OUT = 0.5V -200 ma 2, 4 ICC Operating Power Supply Current V IL = 0.0V, V IH = 3.0V, f CLOCK = MHz 370 ma. One output at a time for a maximum duration of one second. V OUT = 0.5V was selected to avoid test problems by tester ground degradation. Characterized but not 00% tested. 2. Measured using twenty 6-bit counters. 3. Typical values are at V CC= 5V and T A= 25 C. 4. Maximum I CC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum I. CC Test Point 023A Table 2-0007/3320 5

External Switching Characteristics, 2, 3 Over Recommended Operating Conditions 5 TEST -00-70 PARAMETER # 2 DESCRIPTION COND. MIN. MAX. MIN. MAX. UNITS tpd A Data Propagation Delay, 4PT Bypass, ORP Bypass 0.0 5.0 ns tpd2 A 2 Data Propagation Delay 3.0 8.0 ns fmax A 3 3 Clock Frequency with Internal Feedback 00 70.0 MHz fmax (Ext.) 4 Clock Frequency with External Feedback ( tsu2 + tco) 77.0 50.0 MHz fmax (Tog.) 5 4 Clock Frequency, Maximum Toggle 00 83.0 MHz tsu 6 GLB Reg. Setup Time before Clock, 4 PT Bypass 6.0 9.0 ns tco A 7 GLB Reg. Clock to Output Delay, ORP Bypass 6.0 9.0 ns th 8 GLB Reg. Hold Time after Clock, 4 PT Bypass 0.0 0.0 ns tsu2 9 GLB Reg. Setup Time before Clock 7.0.0 ns tco2 0 GLB Reg. Clock to Output Delay 7.0 0.0 ns th2 GLB Reg. Hold Time after Clock 0.0 0.0 ns tr A 2 Ext. Reset Pin to Output Delay 3.5 5.0 ns trw 3 Ext. Reset Pulse Duration 6.5 2.0 ns tptoeen B 4 Input to Output Enable 8.0 2.0 ns tptoedis C 5 Input to Output Disable 8.0 2.0 ns tgoeen B 6 Global OE Output Enable 9.0 2.0 ns tgoedis C 7 Global OE Output Disable 9.0 2.0 ns ttoeen B 8 Test OE Output Enable 2.0 5.0 ns ttoedis C 9 Test OE Output Disable 2.0 5.0 ns twh 20 Ext. Synchronous Clock Pulse Duration, High 5.0 6.0 ns twl 2 Ext. Synchronous Clock Pulse Duration, Low 5.0 6.0 ns tsu3 22 Reg Setup Time before Ext. Synchronous Clock (Y3, Y4) 4.5 5.0 ns th3 23 Reg Hold Time after Ext. Sync Clock (Y3, Y4) 0.0 0.0 ns. Unless noted otherwise, all parameters use 20 PTXOR path and ORP. 2. Refer to Timing Model in this data sheet for further details. 3. Standard 6-bit counter using GRP feedback. 4. fmax (Toggle) may be less than /(twh + twl). This is to allow for a clock duty cycle of other than 50%. 5. Reference Switching Test Conditions section. Table 2-0030/3320 6

Internal Timing Parameters Over Recommended Operating Conditions PARAMETER # 2 DESCRIPTION -00-70 MIN. MAX. MIN. MAX. UNITS Inputs tiobp 24 Register Bypass.5 3.2 ns tiolat 25 Latch Delay 3.0 8.2 ns tiosu 26 Register Setup Time before Clock 7.5 9.0 ns tioh 27 Register Hold Time after Clock -3.0-4.0 ns tioco 28 Register Clock to Out Delay 2.5 4.2 ns tior 29 Register Reset to Out Delay 2.5 4.2 ns GRP tgrp 30 GRP Delay 3.0 3.5 ns tfeedback 3 Feedback Delay..6 ns GLB t4ptbp 32 4 Product Term Bypass Path Delay (Comb.) 3.5 5.3 ns t4ptbr 33 4 Product Term Bypass Path Delay (Reg.) 3.5 3.8 ns tptxor 34 Product Term/XOR Path Delay 4.5 5.8 ns t20ptxor 35 20 Product Term/XOR Path Delay 4.5 5.8 ns txoradj 36 3 XOR Adjacent Path Delay 5.5 7.3 ns tgbp 37 GLB Register Bypass Delay 0.5 0.5 ns tgsu 38 GLB Register Setup Time before Clock.0 2.5 ns tgh 39 GLB Register Hold Time after Clock 4.9 6.3 ns tgco 40 GLB Register Clock to Output Delay 0.5.0 ns tgro 4 GLB Register Reset to Output Delay.0.0 ns tptre 42 GLB Product Term Reset to Register Delay 7.9.5 ns tptoe 43 GLB Product Term Output Enable to Cell Delay 9.5 9.3 ns tptck 44 GLB Product Term Clock Delay 3.2 3.2 4.5 4.5 ns ORP torp 45 ORP Delay.5 2.0 ns torpbp 46 ORP Bypass Delay 0.0 0.0 ns. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros. Table 2-0036/3320 7

Internal Timing Parameters PARAMETER Outputs # 2 Over Recommended Operating Conditions DESCRIPTION tob 47 Output Buffer Delay 2.0 3.0 ns tobs 48 Output Buffer Delay, Slew Limited Adder 2.0 3.0 ns toen 49 Cell OE to Output Enabled 4.0 5.0 ns todis 50 Cell OE to Output Disabled 4.0 5.0 ns Clocks tgy0//2 5 Clock Delay, Y0 or Y or Y2 to Global GLB Clock Line 3.0 3.0 4.0 4.0 ns tioy3/4 52 Clock Delay, Y3 or Y4 to Cell Global Clock Line 3.0 3.0 4.0 4.0 ns Global Reset tgr 53 Global Reset to GLB and Registers 9.0 9.0 ns tgoe 54 Global OE Pad Buffer 5.0 7.0 ns ttoe 55 Test OE Pad Buffer 8.0 0.0 ns. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. -00 MIN. MAX. -70 MIN. MAX. UNITS Table 2-0037/3320 8

isplsi 3320 Timing Model Cell GRP GLB ORP Cell Feedback #3 Pin (Input) Reset Y3,4 Y0,,2 GOE0, TOE #53 Reg Bypass Input D Register Q RST #25-29 #52 #24 Derivations of tsu, th and tco from the Product Term Clock tsu = = = Logic + Reg su - Clock (min) (tiobp + tgrp + t20ptxor) + (tgsu) - (tiobp + tgrp + tptck(min)) (#24+ #30+ #35) + (#38) - (#24+ #30+ #44) 2.3 ns = (.5 + 3.0 + 4.5) + (.0) - (.5 + 3.0 + 3.2) th = = = Clock (max) + Reg h - Logic (tiobp + tgrp + tptck(max)) + (tgh) - (tiobp + tgrp + t20ptxor) (#24+ #30+ #44) + (#39) - (#24+ #30+ #35) 3.6 ns = (.5 + 3.0 + 3.2) + (4.9) - (.5 + 3.0 + 4.5) tco.7 ns = = = = Clock (max) + Reg co + Output (tiobp + tgrp + tptck(max)) + (tgco) + (torp + tob) (#24 + #30 + #44) + (#40) + (#45 + #47) (.5 + 3.0 + 3.2) + (0.5) + (.5 + 2.0) GRP 4 PT Bypass GLB Reg Bypass ORP Bypass #30 #33 #37 #46 #5 #54 #55 20 PT XOR Delays #34-36 #53 Control RE PTs OE #42-44 CK #32 Table 2-0042/3320 GLB Reg Delay RST #38-4 0902/3320 ORP Delay Note: Calculations are based on timing specs for the isplsi 3320-00L. #45 #47, 48 #49, 50 Pin (Output) 9

Power Consumption Power consumption in the isplsi 3320 device depends on two primary factors: the speed at which the device is operating and the number of product terms used. Figure 3 shows the relationship between power and operating speed. Figure 3. Typical Device Power Consumption vs fmax ICC (ma) 800 700 600 500 400 300 200 0 25 50 75 00 fmax (MHz) Notes: Configuration of 20 6-bit Counters Typical Current at 5V, 25 C ICC can be estimated for the isplsi 3320 using the following equation: ICC = 60 + (# of PTs * 0.5) + (# of nets * Max. freq * 0.0095) where: # of PTs = Number of Product Terms used in design # of nets = Number of Signals used in device Max. freq = Highest Clock Frequency to the device isplsi 3320 The ICC estimate is based on typical conditions ( = 5.0V, room temperature) and an assumption of 2 GLB loads on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions and the program in the device, the actual ICC should be verified. 027A/3320 0

Signal Descriptions Signal Name Description GOE0, GOE Global Output Enable input pins. Input/Output Pins These are the general purpose pins used by the logic array. TOE Test Output Enable pin This pin tristates all pins when a logic low is driven. RESET Active Low (0) Reset pin which resets all of the GLB and registers in the device. Y0, Y, Y2 Dedicated Clock inputs. These clock inputs are connected to one of the clock inputs of all the GLBs on the device. Y3, Y4 Dedicated Clock inputs. These clock inputs are connected to one of the clock inputs of all the cells on the device. BSCAN/ispEN Input Dedicated in-system programming enable input pin. When this pin is high, the BSCAN TAP controller pins TMS, TDI, TDO and TCK are enabled. When this pin is brought low, the ISP State Machine control pins MODE, SDI, SDO and SCLK are enabled. High-to-low transition of this pin will put the device in the programming mode and put all pins in the high-z state. TDI/SDI Input This pin performs two functions. It is the Test Data input pin when ispen is logic high. When ispen is logic low, it functions as an input pin to load programming data into the device. SDI is also used as one of the two control pins for the ISP State Machine. TCK/SCLK Input This pin performs two functions. It is the Test Clock input pin when ispen is logic high. When ispen is logic low, it functions as a clock pin for the Serial Shift Register. TMS/MODE Input This pin performs two functions. It is the Test Mode Select input pin when ispen is logic high. When ispen is logic low, it functions as a pin to control the operation of the ISP State Machine. TRST Input Test Reset, active low to reset the Boundary Scan State Machine. TDO/SDO Output This pin performs two functions. When ispen is logic low, it functions as the pin to read the ISP data. When ispen is high, it functions as Test Data Out. Ground () Vcc NC No Connect.. NC pins are not to be connected to any active signals, or.

Signal Locations Signal 208-Pin PQFP 320-Ball BGA GOE0, GOE 33, 34 AD2, AC TOE 30 B4 RESET 28 D3 Y0, Y, Y2, Y3, Y4 32, 30, 29, 28, 27 AA2, AC3, AB3, AA3, AD3 BSCAN/ispEN 27 B2 TDI/SDI 25 C2 TCK/SCLK 24 D2 TMS/MODE 23 A2 TRST 29 A3 TDO/SDO 85 M4, 26, 42, 53, 65, 78, 92, 04, 5, A6, B3, C8, D6, D9, F4, F2, H22, J, M2, N23, T24, U3, 3, 46, 57, 69, 83, 96, 208 W4, W2, AA6, AA9, AB7, AC2, AD9 4, 39, 58, 80, 99, 8, 43, 62, 8, B0, B8, C3, D4, D2, G2, K23, R2, V23, AA4, AA2,AC7, 203 AC5 NC 76, 77, 79, 8, 80, 82, 84 A, A2, A3, A6, A9, A, A4, A20, A23, A24, B, B2, B5, B8, B9, B6, B7, B20, B23, B24, C5, C3, C7, C20, C24, D7, D, D4, D7, D20, E, E2, E3, E4, E22, E23, F24, G2, G23, H2, H3, H4, H23, J2, J23, J24, K3, L, L4, L2, L24, M3, M2, M22, M23, N2, N3, N4, N2, N22, N24, P, P4, P2, P24, R22, T, T2, T23, U2, U2, U22, U23, V2, V4, W, Y2, Y3, Y2, Y22, Y23, Y24, AA5, AA8, AA, AA4, AA8, AB, AB5, AB8, AB2, AB20, AC, AC2, AC5, AC8, AC9, AC6, AC7, AC20, AC23, AC24, AD, AD2, AD5, AD, AD4, AD6, AD9, AD22, AD23, AD24. NC pins are not to be connected to any active signals, or. 2

Locations Signal PQFP BGA Signal PQFP BGA Signal PQFP BGA Signal PQFP BGA 0 3 C4 32 A5 2 33 B5 3 34 C5 4 35 D5 5 36 A7 6 37 C6 7 38 D6 8 40 A8 9 4 A9 0 43 C8 44 B9 2 45 D8 3 46 C9 4 47 A2 5 48 B2 6 49 A22 7 50 C2 8 5 B22 9 52 C22 20 54 C23 2 55 D22 22 56 E2 23 57 D23 24 59 D24 25 60 F22 26 6 E24 27 62 F23 28 63 G22 29 64 H2 30 66 G24 3 67 J2 32 68 J22 33 69 H24 34 70 K2 35 7 K22 36 72 K24 37 73 L22 38 74 L23 39 75 M24 40 82 P23 4 83 P22 42 84 R24 43 85 R23 44 86 R2 45 87 U24 46 88 T22 47 89 T2 48 90 V24 49 9 W24 50 93 V22 5 94 W23 52 95 V2 53 96 W22 54 97 AA24 55 98 AA23 56 00 AB24 57 0 AA22 58 02 AB23 59 03 AB22 60 05 AC22 6 06 AB2 62 07 AA20 63 08 AC2 64 09 AD2 65 0 AB9 66 AD20 67 2 AC9 68 3 AB8 69 4 AA7 70 6 AC8 7 7 AD8 72 9 AA6 73 20 AB6 74 2 AD7 75 22 AA5 76 23 AB5 77 24 AD5 78 25 AB4 79 26 AC4 80 35 AB 8 36 AD0 82 37 AC0 83 38 AB0 84 39 AA0 85 40 AD8 86 4 AB9 87 42 AA9 88 44 AD7 89 45 AD6 90 47 AB7 9 48 AC6 92 49 AA7 93 50 AB6 94 5 AD4 95 52 AC4 96 53 AD3 97 54 AB4 98 55 AC3 99 56 AB3 00 58 AB2 0 59 AA3 02 60 Y4 03 6 AA2 04 63 AA 05 64 W3 06 65 Y 07 66 W2 08 67 V3 09 68 U4 0 70 V 7 T4 2 72 T3 3 73 U 4 74 R4 5 75 R3 6 76 R 7 77 P3 8 78 P2 9 79 N 20 86 M 2 87 L2 22 88 L3 23 89 K 24 90 K2 25 9 K4 26 92 H 27 93 J3 28 94 J4 29 95 G 30 97 F 3 98 G3 32 99 F2 33 200 G4 34 20 F3 35 202 D 36 204 D2 37 205 C 38 206 D3 39 207 C2 40 B3 4 2 C4 42 3 D5 43 4 B4 44 5 A4 45 6 C6 46 7 A5 47 8 B6 48 9 C7 49 0 D8 50 2 B7 5 3 A7 52 5 D9 53 6 C9 54 7 A8 55 8 D0 56 9 C0 57 20 A0 58 2 C 59 22 B 3

Pin Configuration isplsi 3320 208-Pin PQFP (with Heat Spreader) Pinout Diagram 39 38 37 36 35 34 33 32 3 30 29 28 27 26 25 24 23 22 2 20 TDO/SDO NC NC NC 9 i/o 8 7 6 5 4 3 2 0 09 08 07 06 05 04 03 02 0 00 40 4 42 43 44 45 46 47 48 49 50 5 52 53 54 55 56 57 58 59 TMS/MODE TCK/SCLK TDI/SDI BSCAN/ispEN RESET TRST/NC TOE 0 2 3 4 5 6 7 8 9 0 2 3 4 5 6 7 8 9 2 3 4 5 6 7 8 9 0 2 3 4 5 6 7 8 9 20 2 22 23 24 25 26 27 28 29 30 3 32 33 34 35 36 37 38 39 40 4 42 43 44 45 46 47 48 49 50 5 52 208 207 206 205 204 203 202 20 200 99 98 97 96 95 94 93 92 9 90 89 88 87 86 85 84 83 82 8 80 79 78 77 76 75 74 73 72 7 70 69 68 67 66 65 64 63 62 6 60 59 58 57 isplsi 3320 Top View 53 54 55 56 57 58 59 60 6 62 63 64 65 66 67 68 69 70 7 72 73 74 75 76 77 78 79 80 8 82 83 84 85 86 87 88 89 90 9 92 93 94 95 96 97 98 99 00 0 02 03 04 20 2 22 23 24 25 26 27 28 29 30 3 32 33 34 35 36 37 38 39 NC NC NC NC 40 4 42 43 44 45 46 47 48 49 50 5 52 53 54 55 56 57 58 59. NC pins are not to be connected to any active signal, or. 56 55 54 53 52 5 50 49 48 47 46 45 44 43 42 4 40 39 38 37 36 35 34 33 32 3 30 29 28 27 26 25 24 23 22 2 20 9 8 7 6 5 4 3 2 0 09 08 07 06 05 99 98 97 96 95 94 93 92 9 90 89 88 87 86 85 84 83 82 8 80 GOE GOE0 Y0 Y Y2 Y3 Y4 79 78 77 76 75 74 73 72 7 70 69 68 67 66 65 64 63 62 6 60 208MQUAD/3320 4

Signal Configuration isplsi 3320 320-Ball BGA Signal Diagram 24 23 22 2 20 9 8 7 6 5 4 3 2 0 9 8 7 6 5 4 3 2 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD NC NC TMS/ TRST NC 6 4 9 8 5 MODE 57 54 5 46 44 NC NC NC NC NC NC NC ispen/ NC TOE NC NC 8 5 2 BSCAN 59 50 47 43 40 NC TDI/ 20 9 7 3 0 6 3 0 SDI 58 56 53 48 45 4 39 37 NC NC TCK/ RESET 24 23 2 2 7 4 SCLK 55 52 49 42 38 36 35 NC NC NC NC NC NC 26 22 27 25 34 32 30 NC NC 30 28 33 3 29 NC NC NC NC 33 29 26 NC NC 32 3 28 27 36 35 34 25 24 23 NC NC 38 37 22 2 NC isplsi 3320 NC NC SDO/ NC 39 TDO 20 NC NC NC Bottom View NC NC NC 9 NC NC 40 4 7 8 NC 42 43 44 4 5 6 NC NC 46 47 2 NC NC NC NC 45 09 3 NC NC 48 50 52 08 0 NC 49 5 53 05 07 NC NC NC NC NC NC 02 06 NC Y3 Y0 NC 54 55 57 62 69 72 75 84 87 92 0 03 04 Y2 NC 56 58 59 6 65 68 73 76 78 80 83 86 90 93 97 99 00 NC NC NC GOE Y NC NC NC NC 60 63 67 70 79 82 9 95 98 NC NC NC NC GOE Y4 NC NC 64 66 7 74 77 0 8 85 88 89 94 96 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD 24 23 22 2 20 9 8 7 6 5 4 3 2 0 9 8 7 6 5 4 3 2. NCs are not to be connected to any active signals, Vcc or. Note: Ball A indicator dot on top side of package. 320BGA/3320 5

Part Number Description Device Family Device Number Speed 00 = 00 MHz fmax 70 = 70 MHz fmax Ordering Information FAMILY isplsi fmax (MHz) 00 70 isplsi 3320 XXX X XXXX X tpd (ns) 0 5 COMMERCIAL ORDERING NUMBER isplsi 3320-00LQ Grade Blank = Commercial Package Q = PQFP (with Heat Spreader) B320 = BGA Power L = Low 022A/3320 PACKAGE 208-Pin PQFP 00 0 isplsi 3320-00LB320 320-Ball BGA isplsi 3320-70LQ 208-Pin PQFP 70 5 isplsi 3320-70LB320 320-Ball BGA Table 2-004A/3320 6