ORDERING INFORMATION TOP-SIDE

Similar documents
ORDERING INFORMATION PACKAGE

description/ordering information

SN74LVC2244ADWR OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS. description/ordering information

1OE 3B V GND ORDERING INFORMATION. TOP-SIDE MARKING QFN RGY Tape and reel SN74CBTLV3126RGYR CL126 PACKAGE

ORDERING INFORMATION PACKAGE

SN54HC541, SN74HC541 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS

description/ordering information

CD74HCT4514, CD74HCT LINE TO 16-LINE DECODERS/DEMULTIPLEXERS WITH INPUT LATCHES

ORDERING INFORMATION PACKAGE

SN54HC00, SN74HC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES

SN54HC126, SN74HC126 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS

ORDERING INFORMATION PACKAGE

CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541

SN54LS245, SN74LS245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

AM26LS31 QUADRUPLE DIFFERENTIAL LINE DRIVER

SN54LV4052A, SN74LV4052A DUAL 4-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS

SN54AHC573, SN74AHC573 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

ORDERING INFORMATION. 40 C to 85 C TSSOP DGG Tape and reel SN74LVCH16245ADGGR LVCH16245A TVSOP DGV Tape and reel SN74LVCH16245ADGVR LDH245A


SN74ALVCH V 20-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS

SN65176B, SN75176B DIFFERENTIAL BUS TRANSCEIVERS

SN54HC245, SN74HC245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

SN74ALVCH BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS

µa78m00 SERIES POSITIVE-VOLTAGE REGULATORS


SN74LVC1G06 SINGLE INVERTER BUFFER/DRIVER WITH OPEN-DRAIN OUTPUT

description/ordering information


description/ordering information

SN74ALVCH BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS

PRODUCT PREVIEW SN54AHCT257, SN74AHCT257 QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS. description

CD54ACT74, CD74ACT74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

SN54HC365, SN74HC365 HEX BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS

SN54LVC14A, SN74LVC14A HEX SCHMITT-TRIGGER INVERTERS

SN74ALVCHR BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS

SN54AHCT174, SN74AHCT174 HEX D-TYPE FLIP-FLOPS WITH CLEAR

MC3486 QUADRUPLE DIFFERENTIAL LINE RECEIVER WITH 3-STATE OUTPUTS

MAX211 5-V MULTICHANNEL RS-232 LINE DRIVER/RECEIVER WITH ±15-kV ESD PROTECTION

SN54HC373, SN74HC373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

ORDERING INFORMATION PACKAGE

EN: This Datasheet is presented by the m anufacturer. Please v isit our website for pricing and availability at ore.hu.

SN54ACT573, SN74ACT573 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS

CDC337 CLOCK DRIVER WITH 3-STATE OUTPUTS


ORDERING INFORMATION. SSOP DL SN74ALVC164245DLR ALVC Reel of ALVC164245ZQLR

SN54HCT14, SN74HCT14 HEX SCHMITT-TRIGGER INVERTERS

SN54ALS1035, SN74ALS1035 HEX NONINVERTING BUFFERS WITH OPEN-COLLECTOR OUTPUTS

CD54AC08, CD74AC08 QUADRUPLE 2-INPUT POSITIVE-AND GATES

CD54HC221, CD74HC221, CD74HCT221. High-Speed CMOS Logic Dual Monostable Multivibrator with Reset. Features. Description

The ULN2003AI has a 2.7-kΩ series base resistor for each Darlington pair for operation directly with TTL or 5-V CMOS devices. ORDERING INFORMATION

CD74HCT4543 BCD-TO-7 SEGMENT LATCH/DECODER/DRIVER

SN74AUC1G07 SINGLE BUFFER/DRIVER WITH OPEN-DRAIN OUTPUT

SN54LV174A, SN74LV174A HEX D-TYPE FLIP-FLOPS WITH CLEAR

SN54HCT373, SN74HCT373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

SN54HC573A, SN74HC573A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS147B DECEMBER 1982 REVISED MAY 1997


SN54ALS05A, SN74ALS05A HEX INVERTERS WITH OPEN-COLLECTOR OUTPUTS

74ACT11374 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS

description/ordering information

SN54HC373, SN74HC373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS140B DECEMBER 1982 REVISED MAY 1997

description 1G 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 GND V CC 2G/2G 1Y1 2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1 1Y1 2A4 1Y2 2A3 1Y3 1A2 2Y3 1A3 2Y2 1A4 2A2 2G/2G 2Y1

SN74AHC1G04 SINGLE INVERTER GATE

SN5404, SN54LS04, SN54S04, SN7404, SN74LS04, SN74S04 HEX INVERTERS

54AC16245, 74AC BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

MAX232, MAX232I DUAL EIA-232 DRIVER/RECEIVER

SN54HC175, SN74HC175 QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR

PAH PACKAGE (TOP VIEW) AGND FBIN AGND A VCC GND 3Y1 2Y3

ORDERING INFORMATION SOT (SOT-23) DBV SOT (SC-70) DCK

SN74AVCA BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS

SN65LVDM31 HIGH-SPEED DIFFERENTIAL LINE DRIVER

SN54HC377, SN74HC377 OCTAL D-TYPE FLIP-FLOPS WITH CLOCK ENABLE

ORDERING INFORMATION PACKAGE SOT (SC-70) DCK

SN54ACT16373, 74ACT BIT D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS

SN54ACT00, SN74ACT00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES

74AC11373 OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS

ORDERING INFORMATION. SSOP DCT Reel of 3000 SN74LVC2G125DCTR C25 _

SN54HC00, SN74HC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES

SN54HC74, SN74HC74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

SN5407, SN5417, SN7407, SN7417 HEX BUFFERS/DRIVERS WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS

SN75176A DIFFERENTIAL BUS TRANSCEIVER

CD54AC74, CD74AC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

SN55110A, SN75110A, SN75112 DUAL LINE DRIVERS

ua9636ac DUAL LINE DRIVER WITH ADJUSTABLE SLEW RATE

SN54AHCT174, SN74AHCT174 HEX D-TYPE FLIP-FLOPS WITH CLEAR

CD4066B CMOS QUAD BILATERAL SWITCH

MSP53C391, MSP53C392 SLAVE SPEECH SYNTHESIZERS

SN54AHCT74, SN74AHCT74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

SN75158 DUAL DIFFERENTIAL LINE DRIVER

54ACT11020, 74ACT11020 DUAL 4-INPUT POSITIVE-NAND GATES

MC3487 QUADRUPLE DIFFERENTIAL LINE DRIVER

1.5 C Accurate Digital Temperature Sensor with SPI Interface

SN74CB3Q BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER 2.5-V/3.3-V LOW-VOLTAGE HIGH-BANDWIDTH BUS SWITCH

SN54HC132, SN74HC132 QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS

SN54ALS541, SN74ALS540, SN74ALS541 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS

TIB82S105BC FIELD-PROGRAMMABLE LOGIC SEQUENCER WITH 3-STATE OUTPUTS OR PRESET

available options TA PACKAGED DEVICE FEATURES 40 C to 85 C ONET2501PARGT 2.5-Gbps limiting amplifier with LOS and RSSI

description/ordering information

HIGH-VOLTAGE HIGH-CURRENT DARLINGTON TRANSISTOR ARRAYS

L293, L293D QUADRUPLE HALF-H DRIVERS

SN54LVC157A, SN74LVC157A QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS

Transcription:

SCES JULY Control Inputs V IH /V IL Levels are Referenced to V CCA Voltage V CC Isolation Feature If Either V CC Input Is at, Both Ports Are in the High-Impedance State Overvoltage-Tolerant Inputs/Outputs Allow Mixed-Voltage-Mode Data Communications Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full.-V to.-v Power-Supply Range I off Supports Partial-Power-Down Mode Operation description/ordering information This -bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track V CCA. V CCA accepts any supply voltage from. V to. V. The B port is designed to track V CCB. V CCB accepts any supply voltage from. V to. V. This allows for universal low-voltage bidirectional translation between any of the.-v,.-v,.-v, and -V voltage nodes. The SNLVCT is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the outputs so the buses are effectively isolated. The SNLVCT is designed so that the control pins (DIR, DIR, OE, and OE) are supplied by V CCA. ORDERING INFORMATION DGG OR DGV PACKAGE (TOP VIEW) DIR B B B B V CCB B B B B B B B B V CCB B B B B DIR OE A A A A V CCA A A A A A A A A V CCA A A A A OE TA PACKAGE ORDERABLE PART NUMBER TOP-SIDE MARKING TSSOP DGG Tape and reel SNLVCTDGGR C to C TVSOP DGV Tape and reel SNLVCTDGVR VFBGA GQL Tape and reel SNLVCTGQLR Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright, Texas Instruments Incorporated POST OFFICE BOX DALLAS, TEXAS

SCES JULY description/ordering information (continued) This device is fully specified for partial-power-down applications using I off. The I off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The V CC isolation feature ensures that if either V CC input is at, both ports are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. GQL PACKAGE (TOP VIEW) terminal assignments A DIR NC NC NC NC OE A B C D E F G H J K B B B A A C B B VCCB VCCA A A D B B A A E B B A A F B B A A G B B A A H B B VCCB VCCA A A J B B A A K DIR NC NC NC NC OE NC No internal connection FUNCTION TABLE (each -bit section) INPUTS OE DIR OPERATION L L B data to A bus L H A data to B bus H X Isolation logic diagram (positive logic) DIR DIR OE OE A A B B To Seven Other Channels To Seven Other Channels POST OFFICE BOX DALLAS, TEXAS

SCES JULY absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, V CCA and V CCB............................................... V to. V Input voltage range, V I (see Note ): I/O ports (A port).................................. V to. V I/O ports (B port).................................. V to. V Control inputs.................................... V to. V Voltage range applied to any output in the high-impedance or power-off state, V O (see Note ): (A port)............................................................ V to. V (B port)............................................................ V to. V Voltage range applied to any output in the high or low state, V O (see Notes and ): (A port)............................................. V to V CCA +. V (B port)............................................. V to V CCB +. V Input clamp current, I IK (V I < )........................................................... ma Output clamp current, I OK (V O < )........................................................ ma Continuous output current, I O............................................................. ± ma Continuous current through each V CCA, V CCB, and................................... ± ma Package thermal impedance, θ JA (see Note ): DGG package............................... C/W DGV package................................ C/W GQL package................................ C/W Storage temperature range, T stg................................................... C to C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES:. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.. The output positive-voltage rating may be exceeded up to. V maximum if the output current rating is observed.. The package thermal impedance is calculated in accordance with JESD -. POST OFFICE BOX DALLAS, TEXAS

SCES JULY recommended operating conditions (see Notes through ) VCCA VCCB VIH VIL VIH VIL Supply voltage VCCI VCCO MIN MAX UNIT. V to. V VCCI. High-level input Data inputs. V to. V. voltage (see Note ) V to. V. V to. V VCCI...... V to. V VCCI. Low-level input Data inputs. V to. V. voltage (see Note ) V to. V. High-level input voltage Low-level input voltage DIR (Referenced to VCCA) (see Note ) DIR (Referenced to VCCA) (see Note ). V to. V VCCI.. V to. V VCCA.. V to. V. V to. V. V to. V VCCA.. V to. V VCCA.. V to. V. V to. V.. V to. V VCCA. VI Input voltage. V VO IOH IOL t/ v Output voltage High-level output current Low-level output current Input transition rise or fall rate Active state VCCO -State. Data inputs. V to. V. V to. V V to. V. V to. V. V to. V. V to. V V to. V. V to. V. V to. V. V to. V V to. V. V to. V TA Operating free-air temperature C NOTES:. VCCI is the VCC associated with the data input port.. VCCO is the VCC associated with the output port.. All unused data inputs of the device must be held at VCCI or to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA.. For VCCI values not specified in the data sheet, VIH(min) = VCCI x. V, VIL(max) = VCCI x. V.. For VCCI values not specified in the data sheet, VIH(min) = VCCA x. V, VIL(max) = VCCA x. V. V V V V V V ma ma ns/v POST OFFICE BOX DALLAS, TEXAS

SCES JULY electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Notes and ) PARAMETER TEST CONDITIONS VCCA VCCB TA = C C to C MIN TYP MAX MIN MAX IOH = µa, VI = VIH. V to. V. V to. V V CCO. V IOH = ma, VI = VIH.V. V. VOH IOH = ma, VI = VIH. V. V. V IOH = ma, VI = VIH V V. IOH = ma, VI = VIH. V. V. IOL = µa, VI = VIL. V to. V. V to. V. IOL = ma, VI = VIL. V. V. VOL IOL = ma, VI = VIL. V. V. V IOL = ma, VI = VIL V V. II Ioff IOZ ICCA ICCB DIR input A or B port A or B ports ICCA ICCB ICCA ICCB Ci Cio NOTES: A port DIR B port DIR input A or B ports IOL = ma, VI = VIL. V. V. VI = VCCA or. V to. V. V to. V ± ± µa VI or VO = to. V VO = VCCO or VI = VCCI or VI = VCCI or V I = VCCI or One A port at VCCA. V, DIR at VCCA, B port = OPEN DIR at VCCA. V, B port = OPEN, A port at VCCA or One B port at VCCB. V, DIR at, A port = OPEN V to. V ± ± to. V V ± ± OE = VIH. V to. V. V to. V ± ± µa. V to. V. V to. V UNIT IO = V V µa V V. V to. V. V to. V IO = V V µa V V IO =. V to. V. V to. V µa V to. V V to. V V to. V V to. V µa VI = VCCA or. V. V pf VO = VCCA/B or. V. V pf. VCCO is the VCC associated with the output port.. VCCI is the VCC associated with the input port. µaa µa POST OFFICE BOX DALLAS, TEXAS

SCES JULY switching characteristics over recommended operating free-air temperature range, V CCA =. V ±. V (unless otherwise noted) (see Figure ) PARAMETER tpzh tpzl FROM (INPUT) TO (OUTPUT) VCCB =. V ±. V VCCB =. V ±. V VCCB =. V ±. V VCCB = V UNIT MIN MAX MIN MAX MIN MAX MIN MAX A B ns B A ns OE A ns OE B ns OE A ns tpzh tpzl OE B ns switching characteristics over recommended operating free-air temperature range, V CCA =. V ±. V (unless otherwise noted) (see Figure ) PARAMETER FROM (INPUT) TO (OUTPUT) VCCB =. V ±. V VCCB =. V ±. V VCCB =. V ±. V VCCB = V UNIT MIN MAX MIN MAX MIN MAX MIN MAX A B ns B A ns OE A ns OE B ns tpzh tpzl tpzh tpzl OE A ns OE B ns POST OFFICE BOX DALLAS, TEXAS

SCES JULY switching characteristics over recommended operating free-air temperature range, V CCA =. V ±. V (unless otherwise noted) (see Figure ) PARAMETER tpzh tpzl FROM (INPUT) TO (OUTPUT) VCCB =. V ±. V VCCB =. V ±. V VCCB =. V ±. V VCCB = V UNIT MIN MAX MIN MAX MIN MAX MIN MAX A B ns B A ns OE A ns OE B ns OE A ns tpzh tpzl OE B ns switching characteristics over recommended operating free-air temperature range, V CCA = V ±. V (unless otherwise noted) (see Figure ) PARAMETER FROM (INPUT) TO (OUTPUT) VCCB =. V ±. V VCCB =. V ±. V VCCB =. V ±. V VCCB = V UNIT MIN MAX MIN MAX MIN MAX MIN MAX A B ns B A ns OE A ns OE B ns tpzh tpzl OE A ns tpzh tpzl OE B ns operating characteristics, T A = C PARAMETER TEST CONDITIONS A port input, B port output CpdA B port input, A port output CL =, f = MHz, A port input, B port output tr = tf = ns CpdB r f B port input, A port output Power-dissipation capacitance per transceiver VCCA = VCCB =. V VCCA = VCCB =. V VCCA = VCCB =. V VCCA = VCCB = V TYP TYP TYP TYP UNIT pf POST OFFICE BOX DALLAS, TEXAS

SCES JULY power-up considerations A proper power-up sequence always should be followed to avoid excessive supply current, bus contention, oscillations, or other anomalies. To guard against such power-up problems, take the following precautions:. Connect ground before any supply voltage is applied.. Power up V CCA.. V CCB can be ramped up along with or after V CCA. typical total static power consumption (I CCA + I CCB ) Table VCCB V. V VCCA V. V. V. V V UNIT. V µa. V V POST OFFICE BOX DALLAS, TEXAS

SCES JULY TYPICAL CHARACTERISTICS TYPICAL PROPAGATION DELAY (A TO B) vs LOAD CAPACITANCE T A = C, V CCA =. V t PHL ns t PLH ns TYPICAL PROPAGATION DELAY (B TO A) vs LOAD CAPACITANCE T A = C, V CCA =. V t PHL ns t PLH ns POST OFFICE BOX DALLAS, TEXAS

SCES JULY TYPICAL CHARACTERISTICS TYPICAL PROPAGATION DELAY (A TO B) vs LOAD CAPACITANCE T A = C, V CCA =. V t PHL ns t PLH ns TYPICAL PROPAGATION DELAY (B TO A) vs LOAD CAPACITANCE T A = C, V CCA =. V t PHL ns t PLH ns POST OFFICE BOX DALLAS, TEXAS

SCES JULY TYPICAL CHARACTERISTICS TYPICAL PROPAGATION DELAY (A TO B) vs LOAD CAPACITANCE T A = C, V CCA =. V t PHL ns t PLH ns TYPICAL PROPAGATION DELAY (B TO A) vs LOAD CAPACITANCE T A = C, V CCA =. V t PHL ns t PLH ns POST OFFICE BOX DALLAS, TEXAS

SCES JULY TYPICAL CHARACTERISTICS TYPICAL PROPAGATION DELAY (A to B) vs LOAD CAPACITANCE T A = C, V CCA = V t PHL ns t PLH ns TYPICAL PROPAGATION DELAY (B TO A) vs LOAD CAPACITANCE T A = C, V CCA = V t PHL ns t PLH ns POST OFFICE BOX DALLAS, TEXAS

SCES JULY PARAMETER MEASUREMENT INFORMATION From Output Under Test CL (see Note A) RL RL S VCCO Open TEST tpd /tpzl /tpzh S Open VCCO LOAD CIRCUIT tw VCCI Input VCCI/ VCCI/ VCCO. V ±. V. V ±. V. V ±. V V ±. V CL pf pf pf pf RL kω kω kω kω VTP. V. V. V. V VOLTAGE WAVEFORMS PULSE DURATION V Input Output VCCI/ VCCO/ VCCI/ VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCCI V VOH VCCO/ VOL Output Control (low-level enabling) Output Waveform S at VCCO (see Note B) Output Waveform S at (see Note B) tpzl tpzh VCCA/ VCCO/ VCCO/ VCCA/ VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOL + VTP VOH VTP VCCA V VCCO VOL VOH V NOTES: A. CL includes probe and jig capacitance. B. Waveform is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR MHz, ZO = Ω, dv/dt V/ns, dv/dt V/ns. D. The outputs are measured one at a time, with one transition per measurement. E. and are the same as tdis. F. tpzl and tpzh are the same as ten. G. and are the same as tpd. H. VCCI is the VCC associated with the input port. I. VCCO is the VCC associated with the output port. J. All parameters and waveforms are not applicable to all devices. Figure. Load Circuit and Voltage Waveforms POST OFFICE BOX DALLAS, TEXAS

MECHANICAL DATA MPDSC FEBRUARY REVISED AUGUST DGV (R-PDSO-G**) PINS SHOWN PLASTIC SMALL-OUTLINE,,,, M, NOM,,,, Gage Plane A,,,, MAX,, Seating Plane, DIM PINS ** A MAX,,,,,,, A MIN,,,,,,, /E / NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed, per side. D. Falls within JEDEC: / Pins MO- /// Pins MO- POST OFFICE BOX DALLAS, TEXAS

MECHANICAL DATA MTSSD JANUARY REVISED JANUARY DGG (R-PDSO-G**) PINS SHOWN PLASTIC SMALL-OUTLINE PACKAGE,,,, M,,,,, NOM Gage Plane A,,,, MAX,, Seating Plane, DIM PINS ** A MAX,,, A MIN,,, / F / NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold protrusion not to exceed,. D. Falls within JEDEC MO- POST OFFICE BOX DALLAS, TEXAS

IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DSP dsp.ti.com Broadband www.ti.com/broadband Interface interface.ti.com Digital Control www.ti.com/digitalcontrol Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security Telephony www.ti.com/telephony Video & Imaging www.ti.com/video Wireless www.ti.com/wireless Mailing Address: Texas Instruments Post Office Box Dallas, Texas Copyright, Texas Instruments Incorporated