rin n Width W chnnel p-type (doped) sustrte MO Trnsistors n Gte Length L O 2 (insultor) ource Conductor (poly) rin rin Gte nmo trnsistor Gte ource pmo trnsistor licon sustrte doped with impurities dding or cutting wy insulting glss (O 2 ) dding wires mde of polycrystlline silicon (polysilicon, poly) or metl, insulted from the sustrte y O 2 EE 26 Krish Chkrrty ource licon Lttice Trnsistors re uilt on silicon sustrte licon is Group IV mteril Forms crystl lttice with onds to four neighors EE 26 Krish Chkrrty 2
opnts licon is semiconductor Pure silicon hs no free crriers nd conducts poorly dding dopnts increses the conductivity Group V: extr electron (n-type) Group III: missing electron, clled hole (p-type) - + + s - B EE 26 Krish Chkrrty 3 p-n Junctions junction etween p-type nd n-type semiconductor forms diode. Current flows only in one direction p-type n-type node cthode EE 26 Krish Chkrrty 4 2
nmo Trnsistor Four terminls: gte, source, drin, ody Gte oxide ody stck looks like cpcitor Gte nd ody re conductors O 2 (oxide) is very good insultor Clled metl oxide semiconductor (MO) cpcitor Even though gte is no longer mde of metl ource Gte rin Polysilicon O 2 n+ n+ p ulk EE 26 Krish Chkrrty 5 nmo Opertion Body is commonly tied to ground ( V) When the gte is t low voltge: P-type ody is t low voltge ource-ody nd drin-ody diodes re OFF No current flows, trnsistor is OFF ource Gte rin Polysilicon O 2 n+ p n+ ulk EE 26 Krish Chkrrty 6 3
nmo Opertion Cont. When the gte is t high voltge: Positive chrge on gte of MO cpcitor Negtive chrge ttrcted to ody Inverts chnnel under gte to n-type Now current cn flow through n-type silicon from source through chnnel to drin, trnsistor is ON ource Gte rin Polysilicon O 2 n+ p n+ ulk EE 26 Krish Chkrrty 7 pmo Trnsistor milr, ut doping nd voltges reversed Body tied to high voltge (V ) Gte low: trnsistor ON Gte high: trnsistor OFF Bule indictes inverted ehvior Polysilicon ource Gte rin O 2 p+ p+ n ulk EE 26 Krish Chkrrty 8 4
Power upply Voltge GN = V In 98 s, V = 5V V hs decresed in modern processes High V would dmge modern tiny trnsistors Lower V sves power V = 3.3, 2.5,.8,.5,.2,., EE 26 Krish Chkrrty 9 Trnsistors s witches We cn view MO trnsistors s electriclly controlled switches Voltge t gte controls pth from source to drin nmo g d s g = d s OFF g = d s ON pmo g d s d s ON d s OFF EE 26 Krish Chkrrty 5
MO Trnsistor witches N-switch s s N = = (degrded) Good, Poor EE 26 Krish Chkrrty MO Trnsistor witches P-switch s CMO switch (Trnsmission gte) s s s P s = = (degrded) Good, Poor C = s = s Good Good EE 26 Krish Chkrrty 2 6
gnl trength trength of signl How close it pproximtes idel voltge source V nd GN rils re strongest nd nmo pss strong But degrded or wek pmo pss strong But degrded or wek Thus nmo re est for pull-down network EE 26 Krish Chkrrty 3 CMO Inverter V GN EE 26 Krish Chkrrty 4 7
CMO Logic Gtes- Inverter Input 2-input NN V Pull-up pth Output Pull-down pth Gnd V Pull-up tree z Pull-down tree Gnd Pull-down Pull-up truth tle truth tle z z Z Z Z Z NN truth tle z EE 26 Krish Chkrrty 5 CMO Inverter V OFF = = ON GN EE 26 Krish Chkrrty 6 8
CMO Inverter V ON = = OFF GN EE 26 Krish Chkrrty 7 CMO NN Gte B B EE 26 Krish Chkrrty 8 9
CMO NN Gte B = ON ON = OFF B= OFF EE 26 Krish Chkrrty 9 CMO NN Gte B = OFF ON = OFF B= ON EE 26 Krish Chkrrty 2
CMO NN Gte B = ON OFF = ON B= OFF EE 26 Krish Chkrrty 2 CMO NN Gte B = OFF OFF = ON B= ON EE 26 Krish Chkrrty 22
CMO NOR Gte B B EE 26 Krish Chkrrty 23 2-input NOR CMO Logic Gtes-2 V Gnd Pull-up tree z Pull-down tree Pull-down truth tle z Z There is lwys (for ll input comintions) pth from either or to the output No direct pth from to (low power dissiption) Fully restored logic No rtio-ing is necessry (rtio-less logic) Generlize to n-input NN nd n-input NOR? NOR truth tle z Pull-up truth tle z Z Z Z EE 26 Krish Chkrrty 24 2
3-input NN Gte pulls low if LL inputs re pulls high if N input is EE 26 Krish Chkrrty 25 3-input NN Gte pulls low if LL inputs re pulls high if N input is B C EE 26 Krish Chkrrty 26 3
CMO Compound (Complex) Gtes- V c d z Wht function is implemented y this circuit? c d Gnd EE 26 Krish Chkrrty 27 How to implement F = + c + c? F = + c + c Compound Gtes-2 V c c V c F F c Gnd Gnd EE 26 Krish Chkrrty 28 4
nd-or-invert (OI) Gtes c d e f g h F d Pull-up network f F e g c h Gnd EE 26 Krish Chkrrty 29 Or-nd-Invert (OI) Gte c d e f g h F c d Pull-up network e F f g h Gnd Generlly, complex CMO gtes cn e derived directly from mxterms of the function (s in Krnugh mp) EE 26 Krish Chkrrty 3 5
Trnsmission Gtes Pss trnsistors produce degrded outputs Trnsmission gtes pss oth nd well EE 26 Krish Chkrrty 3 Trnsmission Gtes Pss trnsistors produce degrded outputs Trnsmission gtes pss oth nd well g g g =, g = g =, g = Input Output g =, g = strong g =, g = strong g g g g g g EE 26 Krish Chkrrty 32 6
Tristtes Tristte uffer produces Z when not enled EN EN EN EN EE 26 Krish Chkrrty 33 Tristtes Tristte uffer produces Z when not enled EN Z Z EN EN EN EE 26 Krish Chkrrty 34 7
Nonrestoring Tristte Trnsmission gte cts s tristte uffer Only two trnsistors But nonrestoring Noise on is pssed on to EN EN EE 26 Krish Chkrrty 35 Tristte Inverter Tristte inverter produces restored output Violtes conduction complement rule Becuse we wnt Z output EN EN EE 26 Krish Chkrrty 36 8
Tristte Inverter Tristte inverter produces restored output Violtes conduction complement rule Becuse we wnt Z output EN EN EN = = 'Z' EN = = EE 26 Krish Chkrrty 37 Multiplexers 2: multiplexer chooses etween two inputs X X X X EE 26 Krish Chkrrty 38 9
Multiplexers 2: multiplexer chooses etween two inputs X X X X EE 26 Krish Chkrrty 39 Gte-Level Mux esign = + (too mny trnsistors) How mny trnsistors re needed? EE 26 Krish Chkrrty 4 2
Gte-Level Mux esign How = mny + (too mny trnsistors) trnsistors re needed? 2 2 4 4 2 2 4 2 EE 26 Krish Chkrrty 4 Trnsmission Gte Mux Nonrestoring mux uses two trnsmission gtes EE 26 Krish Chkrrty 42 2
Trnsmission Gte Mux Nonrestoring mux uses two trnsmission gtes Only 4 trnsistors EE 26 Krish Chkrrty 43 Inverting multiplexer Inverting Mux Use compound OI22 Or pir of tristte inverters Essentilly the sme thing Noninverting multiplexer dds n inverter EE 26 Krish Chkrrty 44 22
4: Multiplexer 4: mux chooses one of 4 inputs using two selects EE 26 Krish Chkrrty 45 4: Multiplexer 4: mux chooses one of 4 inputs using two selects Two levels of 2: muxes Or four tristtes 2 2 3 3 EE 26 Krish Chkrrty 46 23
CMO Exclusive-Nor Gte 8-trnsistor implementtion TG F = TG 2 TG TG 2 F nonconducting conducting B () nonconducting conducting B () conducting nonconducting B () conducting nonconducting B () Better, 6-trnsistor implementtion is possile! EE 26 Krish Chkrrty 47 Ltch When =, ltch is trnsprent flows through to like uffer When =, the ltch is opque holds its old vlue independent of.k.. trnsprent ltch or level-sensitive ltch Ltch EE 26 Krish Chkrrty 48 24
Ltch esign Multiplexer chooses or old EE 26 Krish Chkrrty 49 Ltch Opertion = = EE 26 Krish Chkrrty 5 25
Flip-flop When rises, is copied to t ll other times, holds its vlue.k.. positive edge-triggered flip-flop, msterslve flip-flop Flop EE 26 Krish Chkrrty 5 Flip-flop esign Built from mster nd slve ltches M Ltch M Ltch EE 26 Krish Chkrrty 52 26
Flip-flop Opertion M = M = EE 26 Krish Chkrrty 53 Rce Condition Bck-to-ck flops cn mlfunction from clock skew econd flip-flop fires lte ees first flip-flop chnge nd cptures its result Clled hold-time filure or rce condition 2 2 Flop Flop 2 2 EE 26 Krish Chkrrty 54 27
Nonoverlpping Clocks Nonoverlpping clocks cn prevent rces s long s nonoverlp exceeds clock skew We will use them in this clss for sfe design Industry mnges skew more crefully insted φ 2 φ M φ 2 φ 2 φ φ φ 2 φ φ φ 2 EE 26 Krish Chkrrty 55 esign Representtion Levels esign domins Behviorl tructurl Physicl Behviorl lgorithms Boolen equtions ifferentil equtions Gjski nd Kuhn s -chrt (lyered like n onion) tructurl Gtes Trnsistors Processor Hrdwre description lnguges commonly used t ehviorl level, e.g. VHL, Verilog Polygons Cells Chip Exmple: Consider the crry function c o = + c + c i Physicl (geometric) EE 26 Krish Chkrrty 56 28
Verilog Exmple (Behviorl) Boolen eqution form: module crry (c o,,, c i ); output c o ; input,, ci; ssign c o = ( & ) ( & c i ) ( & c i ); end module Timing informtion: module crry (c o,,, c i ); output c o ; input,, ci; Wire # c o = ( & ) ( & c i ) ( & c i ); end module c o chnges time units fter,, or c chnges Boolen truth tle form: primitive crry (c o,,, c i ); output c o ; input,, ci; tle // c co? : ;? : ;? : ;? : ;? : ;? : ; end tle end module EE 26 Krish Chkrrty 57 Verilog Exmple (tructurl) tructurl representtion of 4-it dder (top-down) : module dd4 (s, c4, c i,, ); output [3:] s; output [3:] c4; input [3:], ; input ci; wire [2:] c o ; dd (c o [], s[], [], [], c i ); dd (c o [],, [], c o []); dd 2 (c o [2],,, c o []); dd 3 (c4, s[3], [3], [3], c o [2]); end module Technology-independent 3-it internl signl module dd (c o, s,,, c i ); output s, c o ; input,, c i ; sum s (s,,, c i ); crry c (c o,,, c i ); end module module crry (c o,,, c i ); output c o ; input,, c i ; wire x, y, z; nd g (y, z, ); nd g2 (z,, ci); nd g3 (z,, ci); or g4 (co, x, y, z); end module EE 26 Krish Chkrrty 58 29