TDA73 SERIAL BUS CONTROLLED AUDIO PROCESSOR INPUT MULTIPLEXER: - 4 STEREO INPUTS - ONE DIFFERENTIAL STEREO INPUT FOR REMOTE SOURCES SELECTABLE INPUT GAIN FOR OPTIMAL ADAPTION TO DIFFERENT SOURCES INPUT AND OUTPUT FOR EXTERNAL EQUALIZER OR NOISE REDUCTION SYS- TEM VOLUME CONTROL IN.25dB STEPS LOUDNESS FUNCTION TREBLE AND BASS CONTROL FOUR SPEAKER ATTENUATORS: - 4 INDEPENDENT SPEAKERS CONTROL IN.25dB STEPS FOR BALANCE AND FADER FACILITIES - INDEPENDENT MUTE FUNCTION ALL FUNCTIONS PROGRAMMABLE VIA SE- RIAL BUS SELECTABLE CHIP ADDRESS DEDICATED PIN PIN CONNECTION (Top view) PQFP44 ( x ) ORDERING NUMBER: TDA73 DESCRIPTION The TDA73 is a volume, tone (bass and treble) and fader (front/rear) processor for high quality audio applications in car radio and Hi-Fi systems. Loudness and selectable input gain are provided. The control of all fuctions is accomplished by serial bus microprocessor interface. The AC signal setting is obtained by resistor networks and switches combined with operational amplifiers. Thanks to the used BIPOLAR/CMOS Tecnology, Low Distortion, Low Noise and DC stepping are obtained. November 999 This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice. /5
TDA73 TEST CIRCUIT THERMAL DATA Symbol Description Value Unit R th j-pins Thermal Resistance Junction-pins max 85 C/W ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit V S Operating Supply Voltage.2 V T amb Ambient Temperature -4 to 85 C T stg Storage Temperature Range -55 to +5 C QUICK REFERENCE DATA Symbol Parameter Min. Typ. Max. Unit V S Supply Voltage 6 9 V V CL Max. input signal handling 2 Vrms THD Total Harmonic Distortion V = Vrms f = KHz. % S/N Signal to Noise Ratio 6 db S C Channel Separation f = KHz 3 db Volume Control.25dB step -78.75 db Bass and Treble Control 2dB step -4 +4 db Fader and Balance Control.25dB step -38.75 db Input Gain 6.25dB step 8.75 db Mute Attenuation db 2/5
TDA73 BLOCK DIAGRAM LOUD SW L 28 L L2 27 L2 L3 26 L3 L4 25 L4 LEFT INPUTS CD RIGHT INPUTS L5 R5 C C2 C3 C4 C5 C6 C7 C8 C9 C C 4x 2.2µF 4.7µF SGND µf 4.7µF 4x 2.2µF 6 L5 7 8 R5 R4 9 R4 R3 2 R3 R2 2 R2 R 24 R SUPPLY 8 9 7 V CC AGND CREF C2 22µF INPUT SELECTOR + GAIN C4 2.2µF OUT(L) IN(L) 3 29 5 4 4 OUT(R) IN(R) C3 2.2µF 38 39 C5 VOL + LOUD VOL + LOUD C6 nf nf LOUD(L) 32 5.6K R2 C9 nf BOUT(L) RB BASS 3 C2 BIN(L) TREBLE C22 2.7nF TREBLE(L) SERIAL BUS DECODER + LATCHES BASS TREBLE RB 36 35 LOUD(R) BOUT(R) BIN(R) nf nf nf C7 C8 5.6K R 3 TREBLE(R) C2 2.7nF SPKR ATT MUTE SPKR ATT MUTE SPKR ATT MUTE SPKR ATT MUTE 5K D94AU7 2 42 37 43 4 6 5 4 3 OUT LEFT FRONT OUT LEFT REAR ADDR SCL SEN SDA DIGGND OUT RIGHT FRONT OUT RIGHT REAR +V CC BUS 3/5
TDA73 ELECTRICAL CHARACTERISTICS (Tamb = 25 C, VS = 9V, RL = KΩ, RG = 6Ω, GV=dB, f = KHz unless otherwise specified) (refer to the test circuit) Symbol Parameter Test Condition Min. Typ. Max. Unit SUPPLY V S Supply Voltage 6 9 V I S Supply Current 4 8 ma SVR Ripple Rejection 6 85 db INPUT SELECTORS R II Input Resistance Input, 2, 3, 4 5 KΩ Differential Input KΩ V CL Clipping Level 2 2.5 Vrms CMRR Common Mode Rejection 65 db Differential Input INS Input Separation (2) 8 db R L Output Load resistance 2 KΩ G INmin Min. Input Gain - db G INmax Max. Input Gain 8.75 db G STEP Step Resolution 6.25 db e IN Input Noise G = 8.75dB 2 µv V DC DC Steps adjacent gain steps 4 mv G = 8.75 to Mute 4 mv VOLUME CONTROL R IN Input Resistance 33 kω C RANGE Control Range 75 db A VMIN Min. Attenuation - db A VMAX Max. Attenuation 75 db A STEP Step Resolution.25 db E A Attenuation Set Error A V = to -2dB A V = -2 to -6dB -.25-3.25 2 db db E T Tracking Error 2 db V DC DC Steps adjacent attenuation steps From db to A Vmax..5 mv mv SPEAKER ATTENUATORS Control Range 37.5 db Step Resolution.25 db Attenuation set error.5 db Output Mute Attenuation 8 db DC Steps adjacent att. steps from to mute mv mv BASS CONTROL () Control Range +4 db Step Resolution 2 db R B Internal Feedback Resistance 5 KΩ V DC DC Steps adjacent control steps. mv 4/5
TDA73 ELECTRICAL CHARACTERISTICS (continued) Symbol Parameter Test Condition Min. Typ. Max. Unit TREBLE CONTROL () Control Range +4 db Step Resolution 2 db V DC DC Steps adjacent control steps. mv AUDIO OUTPUTS GENERAL Clipping Level d =.3% 2.5 Vrms Output Load Resistance 2 KΩ Output Load Capacitance nf Output resistance 75 2 Ω DC Voltage Level 4.2 4.5 4.8 V e NO Output Noise BW = 2-2KHz, flat output muted all gains = db 2.5 5 5 S/N Signal to Noise Ratio all gains = db; V O = Vrms 6 db d Distortion V IN = Vrms. % Sc Channel Separation left/right 8 3 db BUS INPUTS Total Tracking error A V = to -2dB -2 to -6 db V IL Input Low Voltage V V IH Input High Voltage 3 V V O LOUDNESS SWITCH Output Voltage SDA Acknowledge I O =.6mA.4 V V IL Input Low Voltage V V IH Input High Voltage 3 V I IN Input Current -5 +5 µa DC Step ON OFF position. mv Loudness OFF = pin38 Open; Loudness ON = pin 38 Closed to GND ADDRESS PIN (Internal 5KΩ pull down resistor) Notes: V IL Input Low Voltage V V IH Input High Voltage V CC -V V I IN Input Current µa () Bass and Treble response see attached diagram (fig.7). The center frequency and quality of the resonance behaviour can be choosen by the external circuitry. A standard first order bass response can be realized by a standard feedback network 2 µv µv db db (2) The selected input is grounded thru the 2.2µF capacitor. 5/5
TDA73 APPLICATION SUGGESTION (see to Test circuit) Component Recc. Value Purpose Smaller than Recc. Value Larger than C to C4, C8 to C C5, C7 C6 2.2µF 4.7µF µf THD optimization at low frequencies CMRR optimization differential input C2 22µF C REF SVR optimization < -66 db C3, C4 2.2µF Decoupling Input-Output if external equalizer is not used C5, C6 nf Loudness characteristic C7, C8 nf Bass Filter R 5.6kΩ (standard T - type) C!9, C2 nf cut freq. = Hz R2 5.6kΩ C2 C22 Worse THD at very low frequencies Worse CMRR for ratio not equal to 2 Better SVR at low frequencies Worse SVR at low frequencies 2.7nF Treble Filter Higher cut frequency Lower cut frequency Figure : Loudness versus Volume Attenuation Figure 2: Loudness versus Frequency (CLOUD = nf) 6/5
TDA73 Figure 3: Loudness versus External Capacitors Figure 4: Noise vs. Volume/Gain Settings LOUDNESS VS = 9V Volume = -4dB All other control flat Cin = 2.2µF Figure 5: Signal to Noise Ratio vs. Volume Setting Figure 6: Distortion vs. Load Resistance 7/5
TDA73 Figure 7 : Channel Separation (L R) vs. Frequency Figure 8 : Input Separation (L L2, L3, L4) vs. Frequency Figure 9 : Supply Voltage Rejection vs. Frequency Figure : Output Clipping Level vs. Supply Voltage 8/5
TDA73 Figure : Quiescent Current vs. Supply Voltage Figure 2: Supply Current vs. Temperature Figure 3: Bass Resistance vs. Temperature Figure 4: Typical Tone Response (with the ext. components indicated in the test circuit) 9/5
TDA73 APPLICATION INFORMATION (continued) SERIAL BUS INTERFACE S-BUS Interface and I 2 CBUS Compability Data transmission from microprocessor to the TDA73 and viceversa takes place thru the 3- wire S-BUS interface, consisting of the three lines SDA, SCL, SEN. If SDA and SEN inputs are short-circuited together, then the TDA73 appears as a standard I 2 CBUS slave. According to I 2 CBUS specification the S-BUS lines are connected to a positive supply voltage via pull-up resistors. Data Validity As shown in fig. 5, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. Start and Stop Conditions I 2 CBUS: as shown in fig. 6 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. S-bus: the start/stop conditions (points and 6) are detected exclusively by a transition of the SEN line ( / )wile the SCL line is at the HIGH level. The SDA line is only allowed to change during the time the SCL line is low (points 2, 3, 4, 5). after the start information (point ) the SEN line returns to the HIGH level and remains uncharged for all the time the transmission is performed. Byte Fornat Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first. Acknowledge The master (µp) puts a resistive HIGH level on Figure 5: Data Validity on the I 2 CBUS Figure 7: Acknowledge on the I 2 CBUS Figure 6: Timing Diagram of S-BUS and I 2 CBUS the SDA line during the acknowledge clock pulse (see fig. 7). The peripheral (audioprocessor) that acknowledges has to pull-down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock. /5
TDA73 APPLICATION INFORMATION (continued) The audioprocessor which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer. Transmission without Acknowledge Avoiding to detect the acknowledge of the audioprocessor, the µp can use a simpler transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data. SOFTWARE SPECIFICATION Chip address MSB A LSB A = LOGIC LEVEL ON PIN ADDR DATA BYTES TDA73 ADDRESS This approach of course is less protected from misworking and decreases the noise immunity. Interface Protocol The interface protocol comprises: A start condition (s) A chip address byte, containing the TDA73 address (the 8th bit of the byte must be ). The TDA73 must always acknowledge at the end of each transmitted byte. A sequence of data (N-bytes + acknowledge) A stop condition (P) MSB first byte LSB MSB LSB MSB LSB S A ACK DATA ACK DATA ACK P ACK = Acknowledge S = Start P = Stop MAX CLOCK SPEED kbits/s Data Transferred (N-bytes + Acknowledge) MSB LSB FUNCTION B2 B B B B B G B B B B B G C3 C3 S2 C2 C2 A A A A A S C C A A A A A S C C Volume control Speaker ATT LR Speaker ATT RR Speaker ATT LF Speaker ATT RF Audio switch Bass control Treble control Ax =.25dB steps; Bx = db steps; Cx = 2dB steps; Gx = 6.25dB steps STATUS AFTER POWER ON RESET Volume speaker audio Switch bass treble gain -77.5dB -37.5dB Stereo 5 +2dB +2dB db /5
TDA73 SOFTWARE SPECIFICATION (continued) DATA BYTES (detailed description) Volume MSB LSB FUNCTION B2 B B A A Volume.25dB steps -.25-2.5-3.75-5 -6.25-7.5-8.75 B2 B B A A Volume db steps - -2-3 -4-5 -6-7 For example a volume of -45dB is given by: Speaker Attenuators MSB LSB FUNCTION B B B B B B B B A A A A A A A A Speaker LF Speaker RF Speaker LR Speaker RR -.25-2.5-3.75-5 -6.25-7.5-8.75 - -2-3 Mute For example attenuation of 25dB on speaker RF is given by: 2/5
TDA73 Audio Switch MSB LSB FUNCTION G G S2 S S Audio Switch For example to select the stereo 2 input with a gain of +2.5dB the 8bit string is: Bass and Treble C3 C3 C2 C2 C3 = Sign For example Bass at -db is obtained by the following 8 bit string: C C Stereo Stereo 2 Stereo 3 Stereo 4 Stereo 5 Not allowed Not allowed Not allowed +8.75dB +2.5dB +6.25dB db C C Bass Treble -4-2 - -8-6 -4-2 2 4 6 8 2 4 Purchase of I 2 C Components from STMicroelectronics, conveys a license under the Philips I 2 C Patent Rights to use these components in an I 2 C system, provided that the system conforms to the I 2 C Standard Specifications as defined by Philips. 3/5
TDA73 mm inch DIM. MIN. TYP. MAX. MIN. TYP. MAX. A 2.45.96 OUTLINE AND MECHANICAL DATA A.25..95 2. 2..77.79.83 B.3.45.2.8 c.3.23.5.9 D 2.95 3.2 3.45.5.52.53 D 9.9...39.394.398 D3 8..35 e.8.3 E 2.95 3.2 3.45.5.52.53 E 9.9...39.394.398 E3 8..35 L.65.8.95.26.3.37 L.6.63 K B 34 33 (min.), 7 (max.) D D D3 23 22 E3 PQFP44 ( x ) Seating Plane 44 2 C e E E.mm.4 B A A L L PQFP44 K 4/5
TDA73 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 999 STMicroelectronics Printed in Italy All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 5/5