An on-chip antenna integrated with a transceiver in 0.18-µm CMOS technology

This article has been accepted and published on J-STAGE in advance of copyediting. Content is final as presented. IEICE Electronics Express, Vol.* No.*,*-* An on-chip antenna integrated with a transceiver in 0.18-µm CMOS technology Yexi Song 1,2, Yunqiu Wu 1, Min Sun 2, Guang Yang 2, Xiaoning Zhang 1, Chenxi Zhao 1, Yongling Ban 1, Xiaohong Tang 1 and Kai Kang 1,a) 1 University of Electronic Science and Technology of China, Chengdu, 611731, P. R. China 2 Sichuan Jiuzhou Electric Group Co., Ltd., Mianyang, 621000, P. R. China a) kangkai@uestc.edu.cn Abstract: This paper presents an on-chip antenna integrated with a Ku-band transceiver using a standard 0.18-µm CMOS process. An off-chip guard ring is used to improve the gain of the antenna. As the guard ring is implemented on the test carrier board, this gain improvement technology does not require additional process, and it is easy to implement. It is shown that, a gain improvement of 5.8 dbi can be obtained by using the guard ring with the radiation efficiency improved from 18% to 32%. Additionally, the influence of the CMOS process metal rules and the existence of the transceiver on the antenna performance are studied in this paper. The proposed antenna is fabricated with and without the transceiver, respectively. It is shown that the single-chip antenna (without transceiver) has a gain of 2.4 dbi at 17 GHz, with a 3-dB bandwidth from 14.2 GHz to 21.5 GHz. Meanwhile, the transceiver (with integrated antenna) has a 3-dB bandwidth from 15.8 GHz to 18.0 GHz, with a peak gain of 13.5 db in the transmitter link and a peak gain of 15.3 db in the receiver link. Keywords: On-chip antenna, CMOS process, guard ring Classification: Microwave and millimeter wave devices, circuits, and systems References IEICE 2017 DOI: 10.1587/elex.14.20170836 Received August 8, 2017 Accepted August 18, 2017 Publicized September 13, 2017 [1] Y. P. Zhang, et al.: On-chip antennas for 60-GHz radios in silicon technology, IEEE Trans. Electron Devices 52 (2005) 1664 (DOI: 10.1109/TED.2005.850628). [2] S. S. Hsu, K. C. Wei, C. Y. Hsu, and R. -C. Huey: A 60-GHz millimeter-wave CPW- fed Yagi antenna fabricated by using 0.18-µm CMOS technology, IEEE Electron Device Lett. 29 (2008) 625 (DOI: 10.1109/LED.2008.920852). [3] K. Kang, et al.: A 60-GHz OOK receiver with an on-chip antenna in 90 nm CMOS, IEEE J. Solid-State Circuits 45 (2010) 1720 (DOI: 10.1109/JSSC.2010.2053095). 1

[4] F. Gutierrez, S. Agarwal, K. Parrish, and T. S. Rappaport: On-chip integrated antenna structures in CMOS for 60 GHz WPAN systems, IEEE J. Sel. Areas Commun. 27 (2009) 1367 (DOI: 10.1109/JSAC.2009.091007). [5] Y. Song et al.: A hybrid integrated high gain antenna with an on-chip radiator backed by off-chip ground for system-on-chip applications, IEEE Trans. Compon., Packag. Manuf. Technol. 7 (2017) 114 (DOI: 10.1109/TCPMT.2016.2628388). [6] Aydin Babakhani et al.: A 77-GHz Phased-Array Transceiver With On-Chip Antennas in Silicon: Receiver and Antennas, IEEE J. Solid-State Circuit 41 (2006) 2795 (DOI: 10.1109/JSSC.2006.884811). [7] E. Ojefors, H. Kratz, K. Grenier, R. Plana, and A. Rydberg: Micromachined loop antennas on low resistivity silicon substrates, IEEE Trans. Antennas Propag. 54 (2006) 3593 (DOI: 10.1109/TAP.2006.886532). [8] M. R. Nezhad-Ahmadi et al.: High-efficiency on-chip dielectric resonator antenna for mm-wave transceivers, IEEE Trans. Antennas Propag. 58 (2010) 3388 (DOI: 10.1109/TAP.2010.2055802). [9] S. Y. Kim, O. Inac, C. Y. Kim, D. Shin, and G. M. Rebeiz: A 76-84 GHz 16-element phased array receiver with a chip-level built-in self-test system, IEEE Trans. Microw. Theory Tech. 61 (2013) 3083 (DOI: 10.1109/TMTT.2013.2265016). [10] G. M. Rebeiz: Millimeter-wave and terahertz integrated circuit antennas, Proceedings of the IEEE 80 (1992) 1748 (DOI: 10.1109/5.175253). [11] P. S. Kildal: Artificially soft and hard surfaces in electromagnetics and their application to antenna design, in Proc. Eur. Microw. Conf. (1993) 30 (DOI: 10.1109/EUMA.1993.336763). [12] E. Ojefors et al.: Monolithic integration of a folded dipole antenna with a 24-GHz receiver in SiGe HBT technology, IEEE Trans. Microw. Theory Tech. 55 (2007) 1467 (DOI: 10.1049/TMTT.2007.900315). 1 Introduction On-chip antenna has received great attention in the last decade for its attractive advantages. For example, it can remove the lossy interconnection between the RF front-end IC and the off-chip antenna. Furthermore, with the on-chip antenna, single-chip transceiver is available for many applications, such as wireless communications and phased array systems. To the best of our knowledge,most of the on-chip antenna is implemented using the silicon process from the point of view of cost reduction [1]-[5]. However, the silicon-based on-chip antenna suffers from low radiation gain and low efficiency due to the high permittivity and low resistivity substrate used in the process. As a result, most of the energy is consumed rather than radiated by the antenna in the form of surface-wave and heat [6]. This is the bottleneck for the design of an on-chip antenna. Up to now, so many methods have been proposed to solve this problem, such as the micro-machining technology [7], the dielectric-lens-based concept [6] and the dielectric-resonance-based technology [8]. These techniques, however, need additional processes for the antenna fabrications. This, accordingly, extends the complexity of the implementation of the on-chip antenna. In this work, a single-chip Ku-band (15.8~18 GHz) transceiver integrated with 2

Antenn a Receiver link LNA1 AT1 LNA2 PS1 LNA3 Φ Φ PA AT2 PS3 PS2 Φ Receiver link Antenna Transmitter link Transmitter link (a) (b) Fig. 1. (a) Block diagram of the proposed Ku-band transceiver. (b) Microphotograph of the chip. an on-chip antenna is presented using the standard 0.18-µm CMOS process. To improve the gain of the on-chip antenna, an off-chip guard ring and an off-chip reflector are introduced. The ring and the reflector are implemented on a printed circuit board (PCB), which is also used as the carrier board of the transceiver for test. Obviously, this gain improvement technology does not require additional process, and is easy to realize. Moreover, to satisfy the strict metal design rules of the CMOS technology, a large number of holes are etched in the antenna and plenty of metal dummy blocks are placed under this antenna. The influence of these holes and dummy blocks on the performance of the antenna has been investigated in this paper. In addition, this paper studies the coupling between the antenna and the on-chip inductor to reveal the unwanted coupling level between the antenna and the transceiver circuit. The single-chip antenna and the whole transceiver (with antenna) are on-wafer measured, respectively. It shows that, the single on-chip antenna has a gain of 2.4 dbi at 17 GHz. Meanwhile, the peak gain of the transmitter link and the receiver link of the transceiver is 13.5 db (at 17.5 GHz) and 15.3 db (at 17.0 GHz), respectively. 2 Transceiver architecture Fig. 1 illustrates the block diagram of the proposed Ku-band transceiver fabricated in 0.18-µm CMOS process. To achieve a simple layout and low power consumption, the all-rf architecture is utilized to implement this transceiver [9]. As is seen that, the transmit link consists a power amplifier, a 4-bit attenuator and a 5-bit phase shifter, while the receiver link consists three stages of low noise amplifier, two stages of phase shifters and an attenuator. The transceiver operates in time division duplex (TDD) model and two switches are used to achieve the channel selection. Additionally, an on-chip antenna is integrated with these two channels. As a result, the proposed transceiver has much more integration density and less transmission loss when compared with the traditional one. 3 On-chip antenna design In this work, a folded monopole antenna is adopted, for it is suitable for this bar-type layout of the transceiver. The die photograph and the 3-D simulation model of the antenna are presented in Fig. 2. As is shown that, this antenna is implemented on the top metal layer of the chip, and a microstrip line is used to feed this antenna. A ground-signal-ground (GSG) pad with the pitch of 100 µm is added at the antenna input port for the single antenna test in the later section. To improve 3

1.3 mm 2.5 mm Passivation layer Antenna on top metal layer SiO2 (with metal dummy in it) Feed line GND Si substrate σ = 10Ω-cm, εr = 11.9 Guard ring with grounded vias PCB with metal reflector on the bottom (a) PCB (Ro4350B, h = 2.5 mm) Metal reflector (b) Folded monopole antenna Guard ring Slot in the antenn On-chip antenna GND vias GSG pad Feed line Metal dummy blocks Fig. 2. (a) Antenna die photo. (b) Cross-section view of the on-chip antenna amounted on a PCB (not to scale). (c) 3-D simulation model of the on-chip antenna with an off-chip guard ring for suppressing the surface wave. (c) the antenna gain, an off-chip reflector is adopted, as is presented in our previous literature [5]. This reflector is implemented using the bottom metal of a print circuit board (PCB) and this PCB is also used as the test carrier board for the antenna. The optimized thickness of the PCB is around 2.5 mm, which is about 1/4 λ g (λ g is the guided wavelength in the PCB substrate). In addition, a guard ring is designed to suppress the surface wave that propagating along the surface of PCB. With this ring, the antenna gain has an obviously enhancement of 5.8 db according to the following simulations. The final dimensions of the antenna are shown in Fig. 2(c). With the test pad, the proposed on-chip antenna occupies a die area of only 1.3 2.5 mm 2. 3.1 Guard ring design As mentioned above, the on-chip antenna is mounted on a thick PCB reflector to improve the gain of the antenna. However, the antenna on the electrically thick substrate can suffer strongly from the loss of the surface wave modes [10]. Therefore, in this work, a guard ring is introduced to suppress the surface wave and improve the antenna gain. The guard ring consists of a metal ring on the top layer of PCB and a shorting wall with grounded vias as shown in Fig. 3. The thickness of the dielectric layer is designed to 2.5 mm (around 1/4 λ g ), which leads the Off-chip guard ring On-chip antenna Surface wave d k x kε k y Ground Grounded vias, from top layer to bottom layer Fig. 3 Structure of the guard ring (cross-section view) 4

E-plane H-plane (a) (b) Fig. 4. (a) Simulated reflection coefficient with different guard ring size and simulated radiation efficiency with and without guard ring. (b) Simulated gain pattern with different guard ring size (at 17 GHz). (c) Comparisons of electric field distributions for the on-chip antenna with and without guard ring. equivalent surface impedance of the guard ring Z ring. In order to explain this in detail, the propagation constant k ε of the propagation wave in the dielectric layer is also presented in Fig. 3. Then it will get k k k k 1 (1) 2 2 y r x r Where k is the propagation constant in the free space (k=2π/λ, k ε = ε r k), while k x and k y are the components of the k ε in the horizontal and vertical directions, respectively. Note that the component k y will transform the metal ring to an equivalent surface impedance Z ring at the dielectric surface as Z jtan( k d) Z ( 1) / (2) ring y 0 r r where Z 0 is wave impedance in the free space and d is the thickness of the dielectric layer [11]. It is easily seen that when kd /2, ie.. d /(4 1) (3) y the Z ring =. As a result, with this guard ring the surface wave can be suppressed and the antenna gain can be improved. Then, with the fixed thickness of PCB, the size of the guard ring is optimized. Fig. 4 shows the comparisons of the simulated reflection coefficient and the gain pattern (at 17 GHz) with different ring size (l l mm 2 ). It is seen that the -10 db bandwidth of the antenna is slightly affected by the ring size. But the ring size has a significant influence on the antenna gain. Increasing the ring size in a certain range can increase the gain of the antenna and a peak gain of 2.8 dbi is observed when the l=10 mm. However, further increasing the ring size (l=12 mm for (c) r 5

example) will result in an increase in the side lobe level of the antenna. The width of the ring has little influence on the antenna performance. Therefore it is not shown in this paper. The reflection coefficient, the radiation efficiency and the gain pattern of the antenna without the guard ring are also presented in Fig. 4 for comparison. It is shown that with the proposed guard ring, the resonant frequency of the antenna is shifted down by around 1.9 GHz. Meanwhile, applying this guard ring the antenna gain has a maximum improvement of 5.8 db and the antenna efficiency has an improvement from 18% to 32%. Fig. 4(c) shows the electric field distributions on the surface of the PCB for the on-chip antenna with and without the guard ring. It is obviously seen that the electric field is indeed contained inside the guard ring, and the surface wave is significantly deduced. As a result, the gain and the directivity of the antenna can be improved. 3.2 Investigate of the CMOS process metal rules influence on the antenna performance (a) (b) (c) Fig. 5 (a) Reflection coefficient of antenna with and without dummy blocks and holes. (b) 3-D pattern of antenna without dummy blocks and holes (at 17 GHz). (c) 3-D pattern of antenna with dummy blocks and holes (at 17 GHz). To satisfy the metal rules of the 0.18-µm CMOS process, a large number of dummy blocks are buried under the antenna and plenty of holes are etched in the antenna as Fig. 2(c) presented. The size of the blocks and the holes are 25 µm 25 µm and 5 µm 5 µm, respectively. Fig. 5 illustrates the comparisons of the S 11 and the 3-D pattern of the antenna with and without the dummy blocks and holes (l is fixed to 10 mm). It is shown that with the buried dummy fills and etched holes, the resonant frequency of the antenna is shifted down by around 300 MHz, which is 1.5% with respect to the center frequency. Additionally, according to the 3-D pattern, the peak gain is reduced by 0.12 dbi with these metal blocks and holes. However, these deviations are too small, and we choose to ignore these minor deviations to improve the efficiency of the simulation. Therefore, the influence of the process metal rules is not taken into account in the optimal design of the antenna in this work. 3.3 Investigate of the transceiver influence on the antenna performance For the antenna is integrated with the transceiver in a single chip, the influence of the substrate under the transceiver and the crosstalk between the antenna and the 6

Ground plane of the transceiver 100 µm On-chip antenna Port 1 D Substrate under the transceiver Port 2 On-chip inductor (a) E-plane H-plane (b) (c) Fig. 6 Investigate the influence of the transceiver on the antenna performance. (a) Simulation model. (b) S-parameter simulated results. (c) Antenna patterns with and without the simplified transceiver. transceiver circuit are studied in this section. Additionally, as the on-chip inductor has the largest size in the transceiver circuit, by investigating the crosstalk between the antenna and the inductor can reveal the coupling level between the on-chip antenna and the transceiver circuit [12]. The simulation model beside with the simulated results is shown in Fig. 6. It is seen that the additional substrate and inductor have few influences on the antenna resonant frequency. But a notable change in the E-plane pattern with a 0.9 db decrease of the antenna gain can be observed. This is due to the increase of the lossy substrate area. Meanwhile,it is shown that the existence of the simplified transceiver reduces the cross-polarization level of the antenna by 3.9 db in the H-plane. Furthermore, according to Fig.6(b), the simulated crosstalk level is less than 63 db in the operating bandwidth, which shows a good performance in the unwanted coupling. 4 Measurement results The proposed antenna is fabricated and tested with and without the transceiver respectively. The measured setup is shown in Fig. 7(a), which contains a vector network analyzer (VNA), a spectrum analyzer, a DC power, a GSG probe, and a standard horn antenna, as reported in our previous work [5]. For the first step, the single-chip antenna without the transceiver is mounted on a PCB and measured. The comparison between the measured and simulated antenna input reflection coefficient and gain pattern (at 17 GHz) are presented in Fig. 7(b) and Fig. 7(c). It is seen that the proposed antenna has a 3-dB bandwidth of 7.3 GHz, from 14.2 GHz to 21.5 GHz and a measured peak gain of 2.4 dbi is obtained at θ = 20 @ 17 GHz. A good agreement between the simulated and the measured results can be observed. The shift of the resonance frequency and the deviation of the pattern may due to the process deviation, the existence of the metal probe and the 7

Antenna under test (not integrated with the transceiver) Transceiver with integrated antenna under test E-plane (a) H-plane (b) E-plane -10-20 -30 (c) H-plane -10-20 -30 (d) (e) Fig. 7 (a) Measurement setup and the photos of the device under test. (b) Simulated and measured reflection coefficient and peak gain of the antenna (not integrated with the transceiver). (c) Gain pattern at 17 GHz of the antenna (not integrated with the transceiver). (d) Measured reflection coefficient and gain of the transceiver (with integrated antenna). (e) Measured normalized pattern of the antenna (integrated with transceiver) at 17 GHz. influence of the dummy fills. Additionally, the cross-polarization levels are less than 15 db in both of the E- and H-plane. For the second step, the transceiver integrated with the on-chip antenna is tested. As Fig. 7(d) presented, the peak gain of the receiver link (with antenna) is 15.3 db at 17.0 GHz, with a 3-dB bandwidth from 15.7 GHz to 18.1 GHz. Meanwhile, the transmitter link (with antenna) has a peak gain of 13.5 db at 17.5 GHz, with a 3-dB bandwidth from 15.8 GHz to 18.0 GHz. In addition, the effect of the transceiver on the antenna pattern has been validated. Fig. 7(e) shows the normalized pattern of the antenna integrated with transceiver at 17 GHz. The peak gain is obtained at θ = 0 and the cross-polarization levels are less than db in E-plane and less than -12 db in H-plane, which are agree with the predicted results presented in Fig. 6(c). 5 Conclusion A Ku-band on-chip antenna is fabricated with and without an integrated 8

transceiver in this work respectively. An off-chip guard ring is proposed to raise the antenna gain by 5.8 db and the radiation efficiency is improved from 18% to 32%. Moreover, in the design of antenna, dummy fills and metal slots are introduced to satisfy the metal design rules of the CMOS technology. It shows that these fills and slots have a little influence on the antenna performance (1.5% shift of frequency and 0.12 db decrease of gain). The proposed antenna has a size of 1.3 2.5 mm 2 with a gain of 2.4 dbi at 17 GHz. Acknowledgments This work is supported by National Natural Science Foundation of China (Grant No. 61331006,61422104), National Science and Technology Major Project of the Ministry of Science and Technology of China (Grand No. 2016ZX03001015-004) and Fundamental Research Funds for the Central Universities (Grant No. ZYGX2015J016). 9