The two-dimensional systems embedded in modulation-doped heterostructures are a very interesting and actual research field. The FIB implantation technique can be successfully used to fabricate using these heterostructures two-dimensional p-n junctions, i.e. in-plane junctions between a 2DEG and a 2DHG. Interesting physical properties have been predicted for 2D p-n junctions like a linear dependence of the depletion region width on the applied voltage, a high breakdown voltage and an extremely small capacitance value. Introduced by Wieck and Ploog [1] the IPG transistor fabrication is based on a standard MODFET structure with a high-mobility 2DEG and using the FIB implantation technique, one defines the source, the drain, the gate and, therefore the channel, by implanting insulating lines. The main distinct characteristic of in-plane gate transistors is that the gate-induced electric field is parallel to 2DEG, the gate being separated from the narrow conducting channel by an implantation barrier. The gate bias can control the effective width of the channel and consequently, the drain current. The IPG transistor fabrication, in comparison with other conventional FETs, is inherently self-aligned, and consequently, consists of an easy single maskless step process. Considering the aforementioned interesting properties of the 2D p-n junctions, the IPG transistor is a very promising device for a new semiconductor technology, since the device functions not only at cryogenic temperature, but also at RT. The fact that the 2D p-n junction capacitance is extremely small could also be a starting point to design and fabricate an IPG-based device that would function in ultra- or even extremely-high frequency regime. The fabrication method based on FIB-implanted insulating lines is also known as negative pattern definition. Even if there is no report about IPG transistors fabricated in negative pattern definition on heterostructures with 2DHG, it is theoretically also possible to use p-type wafers as starting material. However, depending on the heterostructure doping, only one type of carriers governs the electrical transport properties of these devices and the fabrication of both n- and p-type IPG transistors on the same wafer is intrinsically impossible. Another difficulty to fabricate IPG transistors in negative pattern definition on heterostructures with a 2DHG consists in the impossibility to obtain high resistive Ga-implanted regions after heat treatment [12]. A different approach is to start from a semi-insulating substrate, which can be used as highly resistive region, and to implant both the channel and gate regions. Consequently, contrary to the negative pattern definition, in which one implants insulating lines in order to define the quasi-1d channel, in positive pattern definition one implants conductive regions. Due to the implantation process, which induces defects, the electrical characteristics of the implanted regions are not too good. It is therefore necessary to perform a rapid thermal annealing process, immediately after the implantation, in order to heal these defects and repair the lattice. Also, the optimization of the FIB implantation doses is a very important step for 119
improving further the mobility, and therefore the channel conductivity. The positive pattern definition proposed by Hirayama [6] was much improved in 2004 by Reuter et al. [9] after successfully fabrication of 2DEGs by overcompensation doping. According to this technique, one uses as substrate, for example, p-type GaAs/In y Ga 1-y As/Al x Ga 1-x As heterostructures and implants only Si 2+. This method opened the possibility of fabrication of two-dimensional n- and p-type IPG transistors from the same heterostructure [8, 9]. Since the goal of this work is to fabricate IPG transistors in negative and positive pattern definition, these techniques supposing to implant either insulating lines or areas with a certain and constant dose, the starting point was to investigate in which conditions the sum of the discretely implanted Gaussian-shape distributions, permitted experimentally by a FIB machine, could lead to a constant-like character. Then the IPG transistors were fabricated in negative pattern definition on two different heterostructures, a normal modulation-doped heterostructure and a pseudomorphic one. The I-V characteristics were measured and it was shown that the pseudomorphic heterostructure yields higher saturation currents (approximate two times higher for the investigated heterostructures) and much lower leakage currents, about two orders of magnitude lower. In order to explain the electrical characteristics of the IPG transistor different theoretical models were proposed and analyzed. Considering as hypotheses that the FIB produces abrupt 2D p-n junctions, and considering in a first approximation that the depletion region along the insulating line between source and drain is a perfect rectangle, a constant mobility model is proposed and analyzed starting from the linear dependence of the depletion region width on the applied bias [5, 108-110]. The high values of the current obtained using this model by numerical calculations proved that the field-dependent mobility cannot be neglected. Consequently, a standard dependence of the drift velocity on the electric field [40] was considered and the implications investigated. The saturation velocity model, the usually model used for IPG transistors [114, 115] was also reviewed. For the first time the negative drain voltage range of the I-V characteristics obtained for IPG transistors is largely discussed. It was shown that depending on the gate bias, there are three different situations: for small gate biases the pinch-off of the channel never produces, but still a kind of saturation is obtained because the current increases slowly in absolute value for large negative biases mainly due to the field-dependent mobility effect. The second situation corresponds to a gate bias, for which the pinch-off occurs at the source. In the third situation for larger gate biases and zero drain voltage, the channel is completely pinched-off. Decreasing the drain voltage, the depletion region from the drain is decreasing until its width is the same as the geometrical channel width, then the channel starts to open. Decreasing further the drain voltage the channel continues to open up until the depletion region from the drain is completely expulsed into the gate region. The main consequence is that a threshold voltage is obtained for this situation, which was also experimentally observed. Then, the depletion and enhancement modes are reviewed in the frame of these models. The discussion continues with a comparison between the RT and 4.2 K electrical characteristics (I-V and transconductance characteristics) of an IPG transistor fabricated on pseudomorphic heterostructure. At RT, it was found that for very small drain voltages, the transconductance curves are flat curves in comparison with those measured in saturation regime, in good 120
agreement with the predictions of the field-dependent theoretical model. However, in a zoomed-in plot, these curves have a very slow dependence on the gate bias that cannot be explained by any of the presented models. The measured maxima depend linearly on the drain voltage suggesting that, in spite of the gate bias dependence, the correction, which should be made to the theoretical model, is small. At 4.2 K the I-V characteristics change drastically. The threshold voltage is shifted to V T = 0 V almost changing the transistor behavior from normally-on to normally-off. The transconductance curves in saturation regime present two distinct regions with a linear behavior in both of them, but with different slopes. Probably this occurs because the gate bias is increased too much in the positive range (enhancement mode) and the channel cannot be enhanced accordingly. Another reason for a very different behavior at RT and 4.2 K is the strong temperature-dependent scattering mechanism. At RT the dominant scattering mechanism is due to the optical phonons and does not depend on the impurity concentration. Therefore, the RT mobilities in the IPG channel and in the 2DEG of the MBE heterostructures are similar. At low temperatures, the scattering mechanism is due to the ionized impurities and therefore, the mobilities in the channel region (very close to the FIB implanted lines) could be much lower than in the 2DEG that is far away from the implanted lines/regions. This affirmation is sustained by a numerical simulation, which proved that the pinch-off voltage that depends linearly on the carrier density is overestimated. At the end of the Chapter 4, the two-region model is also proposed and discussed. IPG transistors fabricated in positive pattern definition were also investigated. Starting again with the simplest model of constant mobility adapted for the geometry of the IPG implanted in positive pattern definition and continuing with the field-dependent mobility model, the results obtained experimentally are discussed. For the first time, a formula analogue to Lehovec-Zuleeg one, which was deduced for junction field-effect transistors, is calculated for IPGJFETs. Detailed graphical representation of the equation is provided in Chapter 5. By implanting either the channel or the gate regions the positive pattern definition technique allows the fabrication of both n- and p-type channel transistors for p- and similar for n-type heterostructures. Consequently, the fabrication of IPG transistors was divided in four different cases. For n-channel IPGJFETs obtained on p-doped heterostructures, the I-V characteristics present well-defined saturation currents, the drain current can be controlled by the gate bias and the breakdown occurs at very large drain voltages. The leakage currents are more than three orders of magnitude smaller than the corresponding drain currents. The transconductance measurements showed the following characteristics: for gate biases lower than the threshold voltage the transconductance is zero, independent of the drain voltage; for drain voltages higher than the saturation value, when the 2D p-n junctions between gates-source and gates-drain are reverse biased, the saturation transconductance is linear when the channel is open; for the transconductance measured at very small source-drain voltages, when the IPGJFET works in the linear region of I-V characteristics, flat curves are obtained and the mean value of these curves is dependent on the applied drain voltage. Again, as for the IPG implanted in negative pattern definition, a zoomed-in plot shows that these flat curves are monotonically increasing until a maximum close to zero gate bias, and the position of the maximum is practically fixed. For p-type channel IPGJFETs the measured drain currents are two orders or magnitude smaller than for n-type channel transistors and the saturation region 121
is not well defined. Also, the leakage currents are higher, being only about two orders of magnitude smaller than the corresponding drain currents. The last important remark is that the channel could be closed only by applying a very high gate bias. For the first time, IPGJFETs fabricated on n-doped heterostructures are reported. For n-channel IPGJFETs obtained on n-doped heterostructures, the I-V characteristics are similar to that obtained on p-doped heterostructures, but the saturation currents have a much better constant-like character. Practically there is no increase of the saturation current, as was previously observed for the other aforementioned transistors. This may be associated with the fact that the channel of these transistors is not implanted, but the gates are. The channel region is consequently a FIB defect-free region. The leakage currents are about three orders of magnitude smaller than the corresponding drain currents. Another difference appears for the transconductances measured at very small drain voltages, which do not present a maximum in the negative range of the gate bias, i.e. normal working regime (for positive gate biases the source-gate junctions are forward biased and consequently, in this range the transistor does not function). For small drain voltages the transconductances seems to linearly increase with the gate bias, fact that cannot be explained by any discussed theoretical model. The fabricated p-type channel IPGJFETs showed very bad I-V characteristics. The saturation region can hardly be seen and the channel could not be closed by applying gate biases up to 20 V. An ample analysis of different implanted geometries of the IPGJFETs is for the first time reported. IPGJFETs with the channel implanted in three different geometries were compared. An U -geometry provides the easiest possibility to close the channel with only one gate, because the channel is situated at one edge of the gates. It is, in fact, the complementary geometry of the standard IPG implanted with insulating lines, and one would naturally think that the channel could be controlled with one gate. The measurements proved that the channel cannot be closed with one gate, due probably to the potential redistribution in the region of unconnected gate close to the channel, together with the fact that the current path is shifted toward the unconnected region. Consequently, all electrical measurements were performed with both gates connected together for all implanted geometries. It was shown that the Z -geometry provided the highest saturation drain currents for n-type channel IPGFETs implanted on p-doped heterostructures. However, the constant-like character of the saturation currents of n-channel IPGJFETs implanted on n-doped heterostructures could determine one to use these transistors, if the selection criterion was the behavior of the current in the saturation regime. The drain current dependence on the geometrical dimensions of the channel was also investigated, this being a test of the models. The fitting shows that as in the case of IPG transistors fabricated in negative pattern definition, the length of the channel is dependent on the drain voltage and this thing cannot be neglected. A two-region model could be a good solution, but the subject remains open, waiting for eventually a more detailed model to be proposed. The last chapter is dedicated to IPG transistor applications. For the first time an electron pump with two in-plane gate transistors is proposed and fabricated. The electron pump was measured in three different working regimes. Thus three different gate biases sequences were considered. The measured currents have a linear dependence on the frequency 122
of the applied gate sequence. A linear dependence on the active gate bias is also measured for low active gate biases. Increasing further the active gate bias in absolute value a kind of saturation occurs probably due to the fact that the active region is practically flooded by the depletion regions. However, the currents still increase linearly, but with a different slope. Different logic circuits with IPG transistors either in negative or in positive pattern definition are proposed. The theme remains also open in this field since the fabrication and optimization of logic circuits was always an attractive subject for electronics. 123