Analysis on Effective parameters influencing Channel Length Modulation ndex in MOS Abhishek Debroy, Rahul Choudhury,Tanmana Sadhu 2 Department of ECE,NT Agartala, Tripura 2 Department of ECE,St. Thomas college of Engineering,Kolkata,west Bengal Abstract We study the phenomenon of Channel length modulation (CLM) in Metal Oxide semiconductors, both PMOS and NMOS and analyze the parameters affecting it. The phenomenon of variation of drain-source current with drain-source voltage is analyzed with respect to channel Length modulation parameter. The governing factor for channel modulation is generally taken as a constant, but detail analysis shows the variation of the channel length modulation parameter in saturation region. The channel length modulation parameter is seen to be varying with thickness of the depletion region, and eventually with drain-source voltage. The Equation governing channel length modulation is first studied with constant parameter and -V characteristics are plotted. Then the equation is studied with varying channel length modulation parameter and -V graph is re- plotted. The dependence of output resistance of both PMOS and NMOS on various parameters is also discussed and results are established. The study of output resistance versus drainsource current at constant & varying Channel length modulation index have been shown and conclusions are being drawn. Keywor channel length modulation,drain-to-source voltage,drain-to-source current,metal oxide semiconductor field effect transistor,dynamic resistance. NTRODUCTON Channel length modulation (CLM) is a shortening of the length of the inverted channel region with increase in drain bias for large drain biases. The result of CLM is an increase in current with drain bias and a reduction of output resistance. The channel is first formed by attraction of carriers to the gate, and the current drawn through the channel is nearly a constant independent of drain voltage in saturation mode. However, near the drain, the gate and drain jointly determine the electric field pattern. nstead of flowing in a channel, beyond the pinch-off point the carriers flow in a subsurface pattern made possible because the drain and the gate both control the current. The channel is generally formed due to gate-source voltage (V gs ) and influenced by drain-source (V ) which can be seen as it becomes weaker as the drain is approached, leaving a gap of un-inverted silicon between the end of the formed inversion layer and the drain (the pinch-off region).the channel is generally formed effectively over the length of the substrate As the drain voltage increases, its control over the current exten further toward the source, so the uninverted region expan toward the source, shortening the length of the channel region, the effect called Channel Length Modulation (CLM).The channel length modulation depen upon the drain-source voltage (V ).The relationship between both of them are studied and corresponding Source-drain current ( ) is noted. The graph between and V are plotted at various values of channel length modulation constant. The Effect of channel length modulation is studied for both NMOS and PMOS. Because resistance is proportional to length, shortening the channel decreases its resistance, causing an increase in current with increase in drain bias for a MOSFET operating in saturation. The effect is more pronounced the shorter the source-to-drain separation, the deeper the drain junction, and the thicker the oxide insulator. The Equation governing output resistance to various parameters is also analyzed. The graph between output resistance and is plotted. Then, we go on to study the effect of channel length modulation with varying modulation parameter. We re-plot the graph of versus V and Output resistance versus V. Finally, we infer the results obtained during both the cases. 392
. THEORY A simple MOS in saturation region is controlled by only Gate-Source voltage (V gs ). n saturation region, the drainsource current ( ) becomes independent of drain-source voltage (V ). The Equations Governing the -V characteristics in saturation region are derived from general equation[]-[4],given by: n w l d V V 2 () p w l d gs tn V V 2 (2) gs tp Equation () is in respect of a NMOS where n = mobility of electrons(~450 cm 2 /V-s),w=width of the inverted channel formed(in our case 60 micron), l=length of channel formed without channel length modulation(6 micron used), = dielectric constant of the metal oxide used as insulator(sio 2 =3.9 ), d=thickness of the metal oxide layer(0nm used), V gs =gate-source voltage(~5v used) V tn = Threshold voltage of NMOS(~V used). V gs and V tn follow the relation V > V gs - V tn, for saturation Mode. (i.e. V >2V) But it is observed that the voltage V influences the channel length of the inverted channel and the channel pinch-off point moves slightly away from the drain. With increase in V it is observed that the channel length reduces and hence the pinch-off point moves further away from the drain towar the source. n such cases l l V Equation (3) with minor variations and algebraic complexities is used to define the transition point and channel length modulation [5]-[9].The above equation can be rewritten as l * l * (4) V Where l =length of inverted channel without modulation, l =length of modulated channel, l =change in length of inverted channel = l -l, λ=channel length modulation constant. Taking the effect of channel length modulation in account equations () and (2) are modified by introducing the factor (λ) : ch 2 V V V w n gs tn l d (3) (5) Equation (2) is in respect of a PMOS where p = mobility of holes (~450 cm 2 /V-s),w=width of the inverted channel formed(60 micron used), l=length of channel formed without channel length modulation(6 micron used), = dielectric constant of the metal oxide used as insulator (SiO 2 =3.9), d=thickness of the metal oxide layer (0 nm used), V gs =gate-source voltage(~ -5V) V tp = Threshold voltage of PMOS(~ - V). V gs and V tp follow the relation : V < V gs - V tp, for saturation Mode. (i.e. V <-2 V) Now, Clearly Equation () and (2) suggest that the variation in is independent of drain-source voltage (V ) in saturation region. ch 2 V V V w p gs tp l d n the above equations, the channel length modulation parameter is kept as a constant but detailed analysis shows that it varies with V. From Equation (4), we try to find out the value of λ at very small variation of length i.e. l ten to zero and V ten to V E, where V E is the constant voltage fitting parameter (generally 4-6 V/µm) (6) 393
l l * V E nternational Journal of Emerging Technology and Advanced Engineering (7) Now the effective characteristic length of the channel continuously decreases with increase in V, and is given by [0] The graphs have been plotted by using equations () and (2), taking λ=0 for without any modulation and λ=0.005 for with modulation. The graphs in Linear region are plotted using equations as per concerned but are not discussed here as we focus on saturation region only. si * d * X dep l' (8) * ox Where si =dielectric constant for semiconductor used (in our case silicon), = dielectric constant of the metal ox oxide layer used(sio 2 used), X dep = thickness of the depletion region(~6 nm used) =Constant Fitting parameter(for our case we take it as unity) Again the thickness of the depletion layer X dep is related to various physical parameters by [0] X dep 2* si*( s V q* N sub BS ) We see that λ varies with varies with l also. Now from equation (8) it is seen that l varies with the parameter X dep, which in fact varies with (9) l from equation (7), hence it s and N sub. t is seen that s varies with V. Hence during channel length modulation the channel length parameter is not a constant with respect to V keeping in view the equations (7),(8) and (9). Fig : versus V plot for NMOS Si-substrate without modulation(green) and with modulation(red) at constant channel length modulation parameter. Range of V is taken from 0-0V. RESULTS AND DSCUSSONS A.Results for ~V graph at constant λ: The drain-source current varies with drain-source voltage in the saturation region due to channel length modulation by equation (5), where λ is taken to be a constant for very low variation of characteristic length. The graph plot has been simulated in MATLAB for both PMOS and NMOS in figure () and figure (2) respectively. Fig 2: versus V plot for PMOS Si-substrate without modulation(green) and with modulation(red) at constant channel length modulation parameter. 394
B.Results for ~V graph at varying λ: Now, from equation (8) it is clear that effective length of inverted channel depen upon the thickness of the depletion region. Modifying Equation (9) as per our experiments by taking VBS =0 and X 2 * *( ) si s dep (0) q * N sub The above equation tells us that thickness of depletion region is a function of surface potential at the threshold of surface inversion, when all other parameters are kept constant. t is observed that the surface potential at inversion threshold decreases with increase in V. Hence From equation (9) X dep also decreases which eventually decreases effective channel length from equation (8). Now since the effective channel length is reduced, l increases and hence from equation (5) and (6) the current increases as λv or l increases. Hence, Our results are well consistent with the theory. The graphs for ~ V for varying λ taking into account equation 7,8,9 for both PMOS and NMOS are given below Fig 4: versus V plot for PMOS Si-substrate at varying channel length modulation parameter. Range of V is taken from 0-0 V The above figure (3) and (4) clearly show that the effective current increases steeply in saturation region as λ varies. n this case the drain-source current () is due to both a bulk phenomenon (flow of current through the channel) and surface phenomenon (due to the electric field).the increase in clearly indicates the fact that there exists a strong electric field at the region where pinch off occurs and this electric field lea higher current flow in the MOS. There is a strong shift from a bulk phenomenon to surface phenomenon in this region, which is an extensive research field nowadays. One can clearly see that with increase in channel length modulation index, the current increases drastically and such a change is in favor of ndustrial applications. B.Results for R o ~ V graph at a constant channel length modulation parameter(λ): Fig 3: versus V plot for NMOS Si-substrate at varying channel length modulation parameter. Range of V is taken from 0-0 V The output resistance of the MOS in saturation region is obtained as R o ch V ch () 395
Evaluating the expression in equation () by using values of ch from equation (5) or (6), and then using the values of Equation () or (2), we get the relation for output resistance for PMOS and NMOS as R o (2) * From Equation (2) it is clear that the channel width modulation affects the output resistance inversely if modulation index is constant. We have studied the dependence of R o versus graph initially for constant λ. The graph is shown below We can clearly see that at the graph satisfies the theoretical assumptions, i.e. The curve follows f(x)~/. But as V increases, the value of increases significantly and establishes a linear plot as seen beyond ( >0.0A). Hence a MOS behaves a voltage dependent current source, which is nothing but can be represented as a linear resistor in small signal model. Hence our simulations are in good agreement with the theory. B.Results for R o ~ V graph at varying channel length modulation parameter(λ): Now, We analyze the situation for varying channel length modulation index as per equation (7), (8) and (9).We, then correlate it with equation() to plot the graph for R o versus graph in the range of 0-0.08A for NMOS and 0- -6mA for PMOS. The graphs can be seen to saturate at different times. Fig 5: Output Resistance ~ curve for constant modulation ndex for NMOS Si-substrate. Range of is taken from 0-0.02A Fig 6: Output Resistance ~ curve for constant modulation ndex for PMOS Si-substrate. Range of is taken from 0-0.02A Fig 7: Graph between output resistance~ for NMOS sisubstrate at varying modulation index. 396
Fig 8 Graph between output resistance~ for PMOS sisubstrate at varying modulation index. We see that in this case, the output resistance still follows the graph of f(x)=/ and gradually behaves as a linear resistor with increase in. Now, we notice that the graphs in this case for both NMOS and PMOS saturate well before the previous case, this is a result of varying modulation index. Hence, we can control the saturation time by varying modulation index. We also see that in this case the resistance becomes zero after a certain increase in which is not observed in previous cases. t suggests a method to design a circuit path with minimum resistance using MOS. This is an interesting governing parameter which can be used to design low dynamic resistance circuits using MOS. We also see that during channel length modulation, there is an amalgam of two phenomena going on, a bulk phenomenon and another surface phenomenon. Both of them together contribute to the current at this stage. The current flow due to electric field developed in the inversion region (surface phenomena) is more significant than the channel conduction current (bulk phenomena) for higher values of V. We have also analyzed the equations relating output resistance to the source-drain current for both constant modulation index and varying modulation index. nitially for the case of constant index, We realized that the graph at the beginning of the saturation perfectly follows a curved shape of f(x)=/, with increasing value of the graph ten to a linear shape. t satisfies the theory that for small signals MOS behaves as a linear resistor i.e. voltage controlled current source. Our results are well consistent for both NMOS and PMOS. We then study the R o versus characteristics for variable modulation index. We see that in this case the current saturates earlier than the previous case. Hence, by altering the value of modulation index one can vary the saturation time of the MOS current. We also see that the output resistance in this case may go to zero unlike previous case, i.e. such a device can provide a good conduction path. Finally we suggest a strong shift from the concept of use of constant modulation index to a variable modulation index for industrial and research activities related to MOS characteristics, especially for small signal analysis V. CONCLUSON We show that in general cases of a MOS operating in saturation region, where modulation index is taken as a constant (for very less change in length of inverted channel) the -V graph is matched in terms of theory. We then show that the modulation index is actually not a constant but varies with inversion threshold voltage, and in such cases the current is increased significantly. The rise in current is observed in both NMOS and PMOS. With increase in V the rise of current increases highly. Such a mechanism can be used to regulate the value of modulation index by controlling the inversion threshold voltage, hence the current can be regulated within a range. 397 REFERENCES []S.R.Hofstein and F.P.Heiman, Silicon insulated-gate field effect transistor, proc EEE,vol.5,pp90-202,963. [2]H.Borkan and P.K.Weimar, Analysis of characteristics of insulated gate thin film transistors, RCA Rev. vol 24,pp 53-65,963 [3]G.T.Wright, space charge limited surface channel mode solid state electron, vol7,pp67-75,964. [4]R.Crawford, MOSFET in circuit design.newyork, McGrawhill, 967,pp 5-69 [5]Z. Liu, C. Hu, J.H. Huang, T.Y. Chan, M.C. Jeng, P.K. Ko, Y.C. Cheng, EEE Vol. 40, No., January 993 [6]G.Merckel,J.Borel,N.Z.Capcea, An accurate large signal MOS transistor model for Computer aided-design, EEE Trans. Electron Devices, vol ED-9,pp 68-690,972 [7]G.T.Wright, current voltage characteristics,channel pinch-off and field dependence of carrier velocity in carrier insulated silicon field effect
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