CMOS LOGIC Inside the CMOS inverter, no I D current flows through transistors when input is logic 1 or logic 0, because

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EEC 40 pring 2003 Lecture 22. Ross EEC 40 pring 2003 Lecture 22. Ross CMO LOGIC Inside the CMO inverter, no I current flows through transistors when input is logic 1 or logic 0, because the NMO transistor is cutoff for logic 0 (0 V) input the PMO transistor is cutoff for logic 1 ( ) input current through the turned on transistor has nowhere to go if next stage consists of transistor gates 1 2 V IN EEC 40 pring 2003 Lecture 22. Ross EEC 40 pring 2003 Lecture 22. Ross V IN = 0 V V IN = NMO transistor cutoff (since V G(N) = V IN = 0 V) acts as open circuit PMO transistor on (V G(P) = V IN = - ) but I (P) = 0 => V (P) = 0 V I (N) (= -I (P) ) PMO transistor cutoff (V G(P) = V IN = 0 V) acts as open circuit NMO transistor on (V G(N) = V IN = ) but I (N) = 0 => V (N) = 0 V I (N) (= -I (P) ) X X

EEC 40 pring 2003 Lecture 22. Ross EEC 40 pring 2003 Lecture 22. Ross EY MOEL OR LOGIC NLYI There is a simpler model for the behavior of transistors in a CMO logic circuit, which applies when the input to the logic circuit is fully logic 0 or fully logic 1. G V G = 0 V Each transistor will be in one of these two situations! V G = (for NMO) V G = - (for PMO) G We can use the model to quickly determine the logical operation of a CMO circuit (but we cannot use it to find circuit currents or voltages that will occur for mid-range input voltages). EEC 40 pring 2003 Lecture 22. Ross EEC 40 pring 2003 Lecture 22. Ross REVIIT CMO INVERTER WITH IMPLE LOGIC MOEL ill in the switch positions below V IN = 0 V V IN =

EEC 40 pring 2003 Lecture 22. Ross EEC 40 pring 2003 Lecture 22. Ross CMO NN PMO 1 PMO 2 NMO 1 NMO 2 EEC 40 pring 2003 Lecture 22. Ross EEC 40 pring 2003 Lecture 22. Ross Verify the logical operation of the CMO NN circuit: =

EEC 40 pring 2003 Lecture 22. Ross EEC 40 pring 2003 Lecture 22. Ross Verify the logical operation of the CMO NN circuit: = = = EEC 40 pring 2003 Lecture 22. Ross EEC 40 pring 2003 Lecture 22. Ross CMO NOR PMO 1 PMO 2 NMO 1 NMO 2

EEC 40 pring 2003 Lecture 22. Ross EEC 40 pring 2003 Lecture 22. Ross Verify the logical operation of the CMO NOR circuit: = EEC 40 pring 2003 Lecture 22. Ross EEC 40 pring 2003 Lecture 22. Ross Verify the logical operation of the CMO NOR circuit: = = =

EEC 40 pring 2003 Lecture 22. Ross EEC 40 pring 2003 Lecture 22. Ross PULL-UP N PULL-OWN EVICE In our logic circuits, the NMO transistor sources are connected to ground, and the PMO sources are connected to. Notice that when NMO transistors are on (when V GN = ) V N is shorted by switch, helping connect output to ground. The NMO transistor functions as a pull-down device; when active, it brings the output to 0 V. When PMO transistors are on (when V GP = - ) V P is shorted by switch, helping connect output to. The PMO transistor functions as a pull-up device; when active, it brings the output to. EEC 40 pring 2003 Lecture 22. Ross EEC 40 pring 2003 Lecture 22. Ross LIMITTION O WITCH MOEL Preview of next class: PMO 1 PMO 2 NMO 1 NMO 2 In reality, the pull-up devices must have some V voltage and current flow to bring the output high since natural capacitance must be charged. imilarly, the pull-down devices must have some V voltage and current flow to bring the output to ground since natural capacitance must be discharged. This is GTE ELY.

EEC 40 pring 2003 Lecture 22. Ross EEC 40 pring 2003 Lecture 22. Ross LIMITTION O WITCH MOEL uppose one needed to fully analyze the circuit for intermediate input voltages. Requires many equations, many unknowns. PMO 1 = PMO 2 = V TH(N) + ε NMO 1 NMO 2 ut, we can at least guess the modes. EEC 40 pring 2003 Lecture 22. Ross EEC 40 pring 2003 Lecture 22. Ross ssume around 5 V, V TH(N) around 1 V, V TH(P) around -1 V, ε around 0.5 V. = PMO 1 PMO 2 = V TH(N) + ε NMO 1 NMO 2 PMO 1 cutoff NMO 1 barely on (V (N2) 0) => saturation NMO 2 fully on, but NMO 1 limits I to small value => triode PMO 2 on, but NMO 1 and PMO 1 make I small => triode

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